drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

555

&otg_master->pll_settings);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1021

bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1049

pll_settings->use_external_clk;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1051

!pll_settings->use_external_clk;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1074

struct pll_settings *pll_settings)

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1127

if (pll_settings->actual_pix_clk_100hz > 6000000UL)

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1138

bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1166

pll_settings->use_external_clk;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1168

!pll_settings->use_external_clk;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1356

struct pll_settings *pll_settings)

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1361

dce112_program_pix_clk(clock_source, pix_clk_params, encoding, pll_settings);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1402

struct pll_settings *pll_settings)

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1418

REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1431

dce112_program_pix_clk(clock_source, pix_clk_params, encoding, pll_settings);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1439

struct pll_settings *pll_settings)

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1444

if (pix_clk_params == NULL || pll_settings == NULL

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1451

memset(pll_settings, 0, sizeof(*pll_settings));

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1468

pll_settings->actual_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1469

pll_settings->adjusted_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1470

pll_settings->calculated_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

191

struct pll_settings *pll_settings,

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

204

pll_settings->adjusted_pix_clk_100hz,

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

223

pll_settings->adjusted_pix_clk_100hz)

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

225

pll_settings->adjusted_pix_clk_100hz

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

226

: pll_settings->adjusted_pix_clk_100hz -

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

231

pll_settings->reference_freq = calc_pll_cs->ref_freq_khz;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

232

pll_settings->reference_divider = ref_divider;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

233

pll_settings->feedback_divider = feedback_divider;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

234

pll_settings->fract_feedback_divider = fract_feedback_divider;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

235

pll_settings->pix_clk_post_divider = post_divider;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

236

pll_settings->calculated_pix_clk_100hz =

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

238

pll_settings->vco_freq =

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

247

struct pll_settings *pll_settings,

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

260

tolerance = (pll_settings->adjusted_pix_clk_100hz * err_tolerance) /

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

275

pll_settings,

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

290

struct pll_settings *pll_settings)

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

298

if (pll_settings->adjusted_pix_clk_100hz == 0) {

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

305

if (pll_settings->pix_clk_post_divider) {

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

306

min_post_divider = pll_settings->pix_clk_post_divider;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

307

max_post_divider = pll_settings->pix_clk_post_divider;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

310

if (min_post_divider * pll_settings->adjusted_pix_clk_100hz <

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

313

pll_settings->adjusted_pix_clk_100hz;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

315

pll_settings->adjusted_pix_clk_100hz) <

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

321

if (max_post_divider * pll_settings->adjusted_pix_clk_100hz

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

324

pll_settings->adjusted_pix_clk_100hz;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

333

if (pll_settings->reference_divider) {

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

334

min_ref_divider = pll_settings->reference_divider;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

335

max_ref_divider = pll_settings->reference_divider;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

378

pll_settings,

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

394

struct pll_settings *pll_settings)

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

444

pll_settings->actual_pix_clk_100hz = actual_pix_clk_100hz;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

445

pll_settings->adjusted_pix_clk_100hz =

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

447

pll_settings->reference_divider =

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

449

pll_settings->pix_clk_post_divider =

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

471

struct pll_settings *pll_settings,

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

482

pll_settings->use_external_clk = (field > 1);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

493

pll_settings->adjusted_pix_clk_100hz / 10);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

496

pll_settings->ss_percentage = ss_data->percentage;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

500

if (!pll_adjust_pix_clk(clk_src, pix_clk_params, pll_settings)) {

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

505

pll_settings->actual_pix_clk_100hz =

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

507

pll_settings->adjusted_pix_clk_100hz =

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

511

pll_settings->adjusted_pix_clk_100hz = 1000000;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

521

pll_settings);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

528

pll_settings);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

535

struct pll_settings *pll_settings,

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

560

pll_settings->actual_pix_clk_100hz = actual_pixel_clock_100hz;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

561

pll_settings->adjusted_pix_clk_100hz = actual_pixel_clock_100hz;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

562

pll_settings->calculated_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

568

struct pll_settings *pll_settings)

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

573

if (pix_clk_params == NULL || pll_settings == NULL

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

580

memset(pll_settings, 0, sizeof(*pll_settings));

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

584

pll_settings->adjusted_pix_clk_100hz = clk_src->ext_clk_khz * 10;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

585

pll_settings->calculated_pix_clk_100hz = clk_src->ext_clk_khz * 10;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

586

pll_settings->actual_pix_clk_100hz =

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

592

pll_settings, pix_clk_params);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

600

struct pll_settings *pll_settings)

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

604

if (pix_clk_params == NULL || pll_settings == NULL

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

611

memset(pll_settings, 0, sizeof(*pll_settings));

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

615

pll_settings->adjusted_pix_clk_100hz = clk_src->ext_clk_khz * 10;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

616

pll_settings->calculated_pix_clk_100hz = clk_src->ext_clk_khz * 10;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

617

pll_settings->actual_pix_clk_100hz =

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

623

pll_settings, pix_clk_params);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

645

const struct pll_settings *pll_settings,

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

662

if (pll_settings == NULL)

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

670

pll_settings->fract_feedback_divider, 1000000);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

671

fb_div = dc_fixpt_add_int(fb_div, pll_settings->feedback_divider);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

693

pll_settings->reference_freq * (uint64_t)1000,

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

694

pll_settings->reference_divider * (uint64_t)ss_data->modulation_freq_hz);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

711

enum signal_type signal, struct pll_settings *pll_settings)

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

720

pll_settings->calculated_pix_clk_100hz / 10);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

725

if (ss_data != NULL && pll_settings->ss_percentage != 0) {

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

726

if (calculate_ss(pll_settings, ss_data, &d_s_data)) {

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

843

struct pll_settings *pll_settings)

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

861

bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

865

bp_pc_params.reference_divider = pll_settings->reference_divider;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

866

bp_pc_params.feedback_divider = pll_settings->feedback_divider;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

868

pll_settings->fract_feedback_divider;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

870

pll_settings->pix_clk_post_divider;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

872

pll_settings->use_external_clk;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

902

pll_settings))

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

918

struct pll_settings *pll_settings)

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

936

bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

942

pll_settings->use_external_clk;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

944

!pll_settings->use_external_clk;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

966

struct pll_settings *pll_settings)

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

992

REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1583

pipe_ctx->pll_settings.ss_percentage;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1659

&pipe_ctx->pll_settings)) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3541

&pipes[i].pll_settings);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1251

&pipe_ctx->pll_settings)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

878

&pipe_ctx->pll_settings)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

498

&pipe_ctx->pll_settings);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1412

&pipe_ctx->pll_settings);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1799

&pipe_ctx->pll_settings);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1086

&pipe_ctx->pll_settings);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

864

&pipe_ctx->pll_settings)) {

drivers/gpu/drm/amd/display/dc/inc/clock_source.h

168

struct pll_settings *);

drivers/gpu/drm/amd/display/dc/inc/clock_source.h

172

struct pll_settings *);

drivers/gpu/drm/amd/display/dc/inc/core_types.h

472

struct pll_settings pll_settings;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

113

&pipes[i]->pll_settings);

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

930

&pipe_ctx->pll_settings);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1072

&pipe_ctx->pll_settings);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1324

&pipe_ctx->pll_settings);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1904

&pipe_ctx->pll_settings);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1698

&pipe_ctx->pll_settings);

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1663

&pipe_ctx->pll_settings);