arch/arm/mach-omap1/clock.c

260

ck_dpll1_p->rate = ptr->pll_rate;

arch/arm/mach-omap1/opp.h

18

unsigned long pll_rate;

drivers/clk/clk-cdce925.c

406

long pll_rate = clk_round_rate(pll, target_rate);

drivers/clk/clk-cdce925.c

410

if (pll_rate <= 0)

drivers/clk/clk-cdce925.c

412

actual_rate = pll_rate / pdiv_now;

drivers/clk/spear/clk-vco-pll.c

67

unsigned long prate, int index, unsigned long *pll_rate)

drivers/clk/spear/clk-vco-pll.c

75

if (pll_rate)

drivers/clk/spear/clk-vco-pll.c

76

*pll_rate = (rate / (1 << rtbl[index].p)) * 10000;

drivers/gpu/drm/mediatek/mtk_dpi.c

569

unsigned long pll_rate;

drivers/gpu/drm/mediatek/mtk_dpi.c

574

pll_rate = vm->pixelclock * factor;

drivers/gpu/drm/mediatek/mtk_dpi.c

577

pll_rate, vm->pixelclock);

drivers/gpu/drm/mediatek/mtk_dpi.c

579

clk_set_rate(dpi->tvd_clk, pll_rate);

drivers/gpu/drm/mediatek/mtk_dpi.c

580

pll_rate = clk_get_rate(dpi->tvd_clk);

drivers/gpu/drm/mediatek/mtk_dpi.c

587

vm->pixelclock = pll_rate / factor;

drivers/gpu/drm/mediatek/mtk_dpi.c

599

pll_rate, vm->pixelclock);

drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c

104

const struct pll_rate *pll_rate = find_rate(req->rate);

drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c

106

req->rate = pll_rate->rate;

drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c

34

static const struct pll_rate freqtbl[] = {

drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c

48

static const struct pll_rate *find_rate(unsigned long rate)

drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c

61

const struct pll_rate *pll_rate = find_rate(lvds_pll->pixclk);

drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c

64

DBG("pixclk=%lu (%lu)", lvds_pll->pixclk, pll_rate->rate);

drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c

66

if (WARN_ON(!pll_rate))

drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c

71

for (i = 0; pll_rate->conf[i].reg; i++)

drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c

72

mdp4_write(mdp4_kms, pll_rate->conf[i].reg, pll_rate->conf[i].val);

drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c

357

static const struct pll_rate *find_rate(unsigned long rate)

drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c

379

const struct pll_rate *pll_rate = find_rate(req->rate);

drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c

381

req->rate = pll_rate->rate;

drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c

390

const struct pll_rate *pll_rate = find_rate(rate);

drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c

395

for (i = 0; i < pll_rate->num_reg; i++)

drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c

396

pll_write(pll, pll_rate->conf[i].reg, pll_rate->conf[i].val);

drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c

40

static const struct pll_rate freqtbl[] = {

drivers/media/i2c/tc358746.c

1107

unsigned long pll_rate = tc358746->pll_rate;

drivers/media/i2c/tc358746.c

1139

mclkdiv = pll_rate / mclk_rate;

drivers/media/i2c/tc358746.c

1143

best_mclk_rate = pll_rate / (2 * 4);

drivers/media/i2c/tc358746.c

1157

best_mclk_rate = pll_rate / (prediv[i] * postdiv);

drivers/media/i2c/tc358746.c

1170

best_mclk_rate = pll_rate / (pre * postdiv);

drivers/media/i2c/tc358746.c

1178

best_mclk_rate = pll_rate / (8 * 512);

drivers/media/i2c/tc358746.c

1222

return tc358746->pll_rate / (prediv * postdiv);

drivers/media/i2c/tc358746.c

1230

req->best_parent_rate = tc358746->pll_rate;

drivers/media/i2c/tc358746.c

1354

tc358746->pll_rate = tc358746_find_pll_settings(tc358746, refclk,

drivers/media/i2c/tc358746.c

1356

if (!tc358746->pll_rate) {

drivers/media/i2c/tc358746.c

1361

err = phy_mipi_dphy_get_default_config_for_hsclk(tc358746->pll_rate,

drivers/media/i2c/tc358746.c

159

unsigned long pll_rate;

drivers/media/i2c/tc358746.c

454

csi_bitrate = tc358746->dphy_cfg.lanes * tc358746->pll_rate;

drivers/mfd/db8500-prcmu.c

1451

rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch);

drivers/mfd/db8500-prcmu.c

1453

rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch);

drivers/mfd/db8500-prcmu.c

1455

rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch);

drivers/mfd/db8500-prcmu.c

1483

rate = pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_FIX);

drivers/mfd/db8500-prcmu.c

1495

rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV);

drivers/mfd/db8500-prcmu.c

1522

return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),

drivers/mfd/db8500-prcmu.c

1548

return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW);

drivers/mfd/db8500-prcmu.c

1550

return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW);

drivers/mfd/db8500-prcmu.c

1554

return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW);

drivers/mfd/db8500-prcmu.c

1556

return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),

drivers/mfd/db8500-prcmu.c

1572

return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, branch);

drivers/mfd/db8500-prcmu.c

1574

return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, branch);

drivers/mfd/db8500-prcmu.c

1576

return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, branch);

drivers/mfd/db8500-prcmu.c

1710

src_rate = pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),

drivers/mfd/db8500-prcmu.c

1878

div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ,

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

126

hdmi_phy->pll_rate = req->rate;

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

219

return hdmi_phy->pll_rate;

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c

309

u32 pixel_clk = hdmi_phy->pll_rate;

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c

426

hdmi_phy->pll_rate = req->rate;

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c

435

return hdmi_phy->pll_rate;

drivers/phy/mediatek/phy-mtk-hdmi.h

39

unsigned long pll_rate;

sound/pci/ctxfi/ctatc.c

1165

if (atc->pll_rate != atc->rsr)

sound/pci/ctxfi/ctatc.c

798

unsigned int rsr = atc->pll_rate ? atc->pll_rate : atc->rsr;

sound/pci/ctxfi/ctatc.c

857

atc->pll_rate = err ? 0 : rate;

sound/pci/ctxfi/ctatc.c

892

if ((rate != atc->pll_rate) && (32000 != rate))

sound/pci/ctxfi/ctatc.h

78

unsigned int pll_rate; /* current rate of Phase Lock Loop */

sound/soc/codecs/adau17x1.c

439

unsigned int pll_rate;

sound/soc/codecs/adau17x1.c

449

pll_rate = 48000 * 1024;

sound/soc/codecs/adau17x1.c

458

pll_rate = 44100 * 1024;

sound/soc/codecs/adau17x1.c

465

clk_get_rate(adau->mclk), pll_rate);

sound/soc/codecs/pcm512x.c

754

unsigned long pll_rate)

sound/soc/codecs/pcm512x.c

765

common = gcd(pll_rate, pllin_rate);

sound/soc/codecs/pcm512x.c

767

pll_rate, pllin_rate, common);

sound/soc/codecs/pcm512x.c

768

num = pll_rate / common;

sound/soc/codecs/pcm512x.c

792

pcm512x->real_pll = pll_rate;

sound/soc/codecs/pcm512x.c

822

pcm512x->real_pll = pll_rate;

sound/soc/codecs/pcm512x.c

841

K = DIV_ROUND_CLOSEST_ULL(10000ULL * pll_rate * P, pllin_rate);

sound/soc/codecs/pcm512x.c

898

unsigned long pll_rate;

sound/soc/codecs/pcm512x.c

951

pll_rate = 4 * sck_rate;

sound/soc/codecs/pcm512x.c

953

ret = pcm512x_find_pll_coeff(dai, pllin_rate, pll_rate);

sound/soc/samsung/snow.c

29

static const unsigned int pll_rate[] = {

sound/soc/samsung/snow.c

78

for (i = 0; i < ARRAY_SIZE(pll_rate); i++) {

sound/soc/samsung/snow.c

79

if ((pll_rate[i] - rclk * psr) <= 2) {

sound/soc/samsung/snow.c

80

freq = pll_rate[i];

sound/soc/ti/j721e-evm.c

555

unsigned int min_rate, max_rate, pll_rate;

sound/soc/ti/j721e-evm.c

585

pll_rate = priv->pll_rates[J721E_CLK_PARENT_44100];

sound/soc/ti/j721e-evm.c

587

pll_rate = priv->pll_rates[J721E_CLK_PARENT_48000];

sound/soc/ti/j721e-evm.c

589

min_rate = pll_rate / J721E_MAX_CLK_HSDIV;

sound/soc/ti/j721e-evm.c

593

pll_rate = priv->pll_rates[J721E_CLK_PARENT_48000];

sound/soc/ti/j721e-evm.c

595

pll_rate = priv->pll_rates[J721E_CLK_PARENT_44100];

sound/soc/ti/j721e-evm.c

597

if (pll_rate > PCM1368A_MAX_SYSCLK)

sound/soc/ti/j721e-evm.c

598

pll_rate = PCM1368A_MAX_SYSCLK;

sound/soc/ti/j721e-evm.c

600

max_rate = pll_rate / ratios_for_pcm3168a[0];