drivers/clk/clk-k230.c

275

K230_CLK_PLL_FORMAT(pll2, 2, CLK_IS_CRITICAL, NULL);

drivers/clk/clk-k230.c

281

&pll2,

drivers/clk/clk-k230.c

292

K230_CLK_FIXED_FACTOR_FORMAT(pll2_div2, 1, 2, 0, &pll2.hw);

drivers/clk/clk-k230.c

293

K230_CLK_FIXED_FACTOR_FORMAT(pll2_div3, 1, 3, 0, &pll2.hw);

drivers/clk/clk-k230.c

294

K230_CLK_FIXED_FACTOR_FORMAT(pll2_div4, 1, 4, 0, &pll2.hw);

drivers/clk/mxs/clk-imx28.c

170

clks[pll2] = mxs_clk_pll("pll2", "ref_xtal", PLL2CTRL0, 23, 50000000);

drivers/clk/qcom/mmcc-msm8960.c

101

{ .hw = &pll2.clkr.hw },

drivers/clk/qcom/mmcc-msm8960.c

114

{ .hw = &pll2.clkr.hw },

drivers/clk/qcom/mmcc-msm8960.c

128

{ .hw = &pll2.clkr.hw },

drivers/clk/qcom/mmcc-msm8960.c

2847

[PLL2] = &pll2.clkr,

drivers/clk/qcom/mmcc-msm8960.c

3025

[PLL2] = &pll2.clkr,

drivers/clk/qcom/mmcc-msm8960.c

42

static struct clk_pll pll2 = {

drivers/clk/spacemit/ccu-k1.c

46

CCU_PLL_DEFINE(pll2, pll2_rate_tbl, APBS_PLL2_SWCR1, APBS_PLL2_SWCR3, MPMU_POSR, POSR_PLL2_LOCK,

drivers/clk/spacemit/ccu-k1.c

66

CCU_FACTOR_GATE_DEFINE(pll2_d1, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(0), 1, 1);

drivers/clk/spacemit/ccu-k1.c

67

CCU_FACTOR_GATE_DEFINE(pll2_d2, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(1), 2, 1);

drivers/clk/spacemit/ccu-k1.c

68

CCU_FACTOR_GATE_DEFINE(pll2_d3, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(2), 3, 1);

drivers/clk/spacemit/ccu-k1.c

69

CCU_FACTOR_GATE_DEFINE(pll2_d4, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(3), 4, 1);

drivers/clk/spacemit/ccu-k1.c

70

CCU_FACTOR_GATE_DEFINE(pll2_d5, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(4), 5, 1);

drivers/clk/spacemit/ccu-k1.c

709

[CLK_PLL2] = &pll2.common.hw,

drivers/clk/spacemit/ccu-k1.c

71

CCU_FACTOR_GATE_DEFINE(pll2_d6, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(5), 6, 1);

drivers/clk/spacemit/ccu-k1.c

72

CCU_FACTOR_GATE_DEFINE(pll2_d7, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(6), 7, 1);

drivers/clk/spacemit/ccu-k1.c

73

CCU_FACTOR_GATE_DEFINE(pll2_d8, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(7), 8, 1);

drivers/clk/spacemit/ccu-k3.c

1037

[CLK_PLL2] = &pll2.common.hw,

drivers/clk/spacemit/ccu-k3.c

58

CCU_PLLA_DEFINE(pll2, pll2_rate_tbl, APBS_PLL2_SWCR1, APBS_PLL2_SWCR2, APBS_PLL2_SWCR3,

drivers/clk/spacemit/ccu-k3.c

86

CCU_FACTOR_GATE_DEFINE(pll2_d1, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(0), 1, 1);

drivers/clk/spacemit/ccu-k3.c

87

CCU_FACTOR_GATE_DEFINE(pll2_d2, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(1), 2, 1);

drivers/clk/spacemit/ccu-k3.c

88

CCU_FACTOR_GATE_DEFINE(pll2_d3, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(2), 3, 1);

drivers/clk/spacemit/ccu-k3.c

89

CCU_FACTOR_GATE_DEFINE(pll2_d4, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(3), 4, 1);

drivers/clk/spacemit/ccu-k3.c

90

CCU_FACTOR_GATE_DEFINE(pll2_d5, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(4), 5, 1);

drivers/clk/spacemit/ccu-k3.c

91

CCU_FACTOR_GATE_DEFINE(pll2_d6, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(5), 6, 1);

drivers/clk/spacemit/ccu-k3.c

92

CCU_FACTOR_GATE_DEFINE(pll2_d7, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(6), 7, 1);

drivers/clk/spacemit/ccu-k3.c

93

CCU_FACTOR_GATE_DEFINE(pll2_d8, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(7), 8, 1);

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

297

static void get_pll_config(struct drm_display_mode *mode, u32 *pll1, u32 *pll2)

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

305

*pll2 = CRT_PLL2_HS_25MHZ;

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

310

*pll2 = hibmc_pll_table[idx].pll2_config_value;

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

326

u32 pll2; /* bit[63:32] of PLL */

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

332

get_pll_config(mode, &pll1, &pll2);

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

333

writel(pll2, priv->mmio + CRT_PLL2_HS);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2103

PORT_PLL_M2_FRAC_MASK, hw_state->pll2);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2223

hw_state->pll2 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 2));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2224

hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2363

hw_state->pll2 = PORT_PLL_M2_FRAC(clk_div->m2 & 0x3fffff);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2397

hw_state->pll2);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2490

hw_state->pll0, hw_state->pll1, hw_state->pll2, hw_state->pll3,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2505

a->pll2 == b->pll2 &&

drivers/gpu/drm/i915/display/intel_dpll_mgr.h

208

u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12;

drivers/gpu/drm/nouveau/dispnv04/hw.c

133

uint32_t pll2, struct nvkm_pll_vals *pllvals)

drivers/gpu/drm/nouveau/dispnv04/hw.c

144

pllvals->NM1 = pll2 & 0xffff;

drivers/gpu/drm/nouveau/dispnv04/hw.c

147

pllvals->NM2 = pll2 >> 16;

drivers/gpu/drm/nouveau/dispnv04/hw.c

150

if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2)

drivers/gpu/drm/nouveau/dispnv04/hw.c

151

pllvals->NM2 = pll2 & 0xffff;

drivers/gpu/drm/nouveau/dispnv04/hw.c

170

uint32_t reg1, pll1, pll2 = 0;

drivers/gpu/drm/nouveau/dispnv04/hw.c

180

pll2 = nvif_rd32(device, reg1 + 4);

drivers/gpu/drm/nouveau/dispnv04/hw.c

184

pll2 = nvif_rd32(device, reg2);

drivers/gpu/drm/nouveau/dispnv04/hw.c

193

pll2 = 0;

drivers/gpu/drm/nouveau/dispnv04/hw.c

196

pll2 = 0;

drivers/gpu/drm/nouveau/dispnv04/hw.c

199

nouveau_hw_decode_pll(dev, reg1, pll1, pll2, pllvals);

drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c

208

uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2;

drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c

218

pll2 = 0;

drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c

227

pll2 |= 0x011f;

drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c

233

if (oldpll1 == pll1 && oldpll2 == pll2)

drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c

266

nvkm_wr32(device, reg2, pll2);

drivers/gpu/drm/tegra/sor.c

1457

value = tegra_sor_readl(sor, sor->soc->regs->pll2);

drivers/gpu/drm/tegra/sor.c

1459

tegra_sor_writel(sor, value, sor->soc->regs->pll2);

drivers/gpu/drm/tegra/sor.c

1467

value = tegra_sor_readl(sor, sor->soc->regs->pll2);

drivers/gpu/drm/tegra/sor.c

1470

tegra_sor_writel(sor, value, sor->soc->regs->pll2);

drivers/gpu/drm/tegra/sor.c

2289

value = tegra_sor_readl(sor, sor->soc->regs->pll2);

drivers/gpu/drm/tegra/sor.c

2291

tegra_sor_writel(sor, value, sor->soc->regs->pll2);

drivers/gpu/drm/tegra/sor.c

2304

value = tegra_sor_readl(sor, sor->soc->regs->pll2);

drivers/gpu/drm/tegra/sor.c

2306

tegra_sor_writel(sor, value, sor->soc->regs->pll2);

drivers/gpu/drm/tegra/sor.c

2310

value = tegra_sor_readl(sor, sor->soc->regs->pll2);

drivers/gpu/drm/tegra/sor.c

2313

tegra_sor_writel(sor, value, sor->soc->regs->pll2);

drivers/gpu/drm/tegra/sor.c

2783

value = tegra_sor_readl(sor, sor->soc->regs->pll2);

drivers/gpu/drm/tegra/sor.c

2785

tegra_sor_writel(sor, value, sor->soc->regs->pll2);

drivers/gpu/drm/tegra/sor.c

2797

value = tegra_sor_readl(sor, sor->soc->regs->pll2);

drivers/gpu/drm/tegra/sor.c

2800

tegra_sor_writel(sor, value, sor->soc->regs->pll2);

drivers/gpu/drm/tegra/sor.c

2804

value = tegra_sor_readl(sor, sor->soc->regs->pll2);

drivers/gpu/drm/tegra/sor.c

2807

tegra_sor_writel(sor, value, sor->soc->regs->pll2);

drivers/gpu/drm/tegra/sor.c

3320

.pll2 = 0x19,

drivers/gpu/drm/tegra/sor.c

3492

.pll2 = 0x19,

drivers/gpu/drm/tegra/sor.c

3553

.pll2 = 0x165,

drivers/gpu/drm/tegra/sor.c

3636

.pll2 = 0x16b,

drivers/gpu/drm/tegra/sor.c

371

unsigned int pll2;

drivers/media/i2c/ov7251.c

108

const struct ov7251_pll2_cfg *pll2;

drivers/media/i2c/ov7251.c

217

.pll2 = &ov7251_pll2_cfg_19_2_mhz,

drivers/media/i2c/ov7251.c

225

.pll2 = &ov7251_pll2_cfg_24_mhz,

drivers/media/i2c/ov7251.c

839

configs->pll2->pre_div);

drivers/media/i2c/ov7251.c

844

configs->pll2->mult);

drivers/media/i2c/ov7251.c

849

configs->pll2->div);

drivers/media/i2c/ov7251.c

854

configs->pll2->sys_div);

drivers/media/i2c/ov7251.c

859

configs->pll2->adc_div);

drivers/mfd/sm501.c

116

static unsigned long decode_div(unsigned long pll2, unsigned long val,

drivers/mfd/sm501.c

121

pll2 = 288 * MHZ;

drivers/mfd/sm501.c

123

return pll2 / div_tab[(val >> lshft) & mask];

drivers/mfd/sm501.c

140

unsigned long pll2 = 0;

drivers/mfd/sm501.c

144

pll2 = 336 * MHZ;

drivers/mfd/sm501.c

147

pll2 = 288 * MHZ;

drivers/mfd/sm501.c

150

pll2 = 240 * MHZ;

drivers/mfd/sm501.c

153

pll2 = 192 * MHZ;

drivers/mfd/sm501.c

157

sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ;

drivers/mfd/sm501.c

160

sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ;

drivers/mfd/sm501.c

167

fmt_freq(pll2), sdclk0, sdclk1);

drivers/mfd/sm501.c

175

fmt_freq(decode_div(pll2, pm0, 24, 1<<29, 31)),

drivers/mfd/sm501.c

176

fmt_freq(decode_div(pll2, pm0, 16, 1<<20, 15)),

drivers/mfd/sm501.c

177

fmt_freq(decode_div(pll2, pm0, 8, 1<<12, 15)),

drivers/mfd/sm501.c

178

fmt_freq(decode_div(pll2, pm0, 0, 1<<4, 15)));

drivers/mfd/sm501.c

184

fmt_freq(decode_div(pll2, pm1, 24, 1<<29, 31)),

drivers/mfd/sm501.c

185

fmt_freq(decode_div(pll2, pm1, 16, 1<<20, 15)),

drivers/mfd/sm501.c

186

fmt_freq(decode_div(pll2, pm1, 8, 1<<12, 15)),

drivers/mfd/sm501.c

187

fmt_freq(decode_div(pll2, pm1, 0, 1<<4, 15)));

sound/soc/codecs/fs-amp-lib.h

128

u16 pll2;

sound/soc/codecs/fs210x.c

685

ret |= fs210x_reg_write(fs210x, FS210X_A2H_PLLCTRL2, pll_div->pll2);

sound/soc/codecs/tscs454.c

133

struct pll pll2;

sound/soc/codecs/tscs454.c

294

pll_init(&tscs454->pll2, 2);

sound/soc/codecs/tscs454.c

3186

aif->pll = &tscs454->pll2;

sound/soc/codecs/tscs454.c

3199

tscs454->internal_rate.pll = &tscs454->pll2;

sound/soc/codecs/tscs454.c

439

mutex_lock(&tscs454->pll2.lock);

sound/soc/codecs/tscs454.c

456

mutex_unlock(&tscs454->pll2.lock);

sound/soc/codecs/tscs454.c

688

mutex_lock(&tscs454->pll2.lock);

sound/soc/codecs/tscs454.c

689

users = tscs454->pll2.users;

sound/soc/codecs/tscs454.c

690

mutex_unlock(&tscs454->pll2.lock);