arch/alpha/include/asm/core_marvel.h
269
#define IO7_PLL_RNGA(pll) (((pll) >> 3) & 0x7)
arch/alpha/include/asm/core_marvel.h
270
#define IO7_PLL_RNGB(pll) (((pll) >> 6) & 0x7)
arch/m68k/coldfire/m5206.c
25
DEFINE_CLK(pll, "pll.0", MCF_CLK);
arch/m68k/coldfire/m523x.c
28
DEFINE_CLK(pll, "pll.0", MCF_CLK);
arch/m68k/coldfire/m5249.c
25
DEFINE_CLK(pll, "pll.0", MCF_CLK);
arch/m68k/coldfire/m525x.c
25
DEFINE_CLK(pll, "pll.0", MCF_CLK);
arch/m68k/coldfire/m5272.c
35
DEFINE_CLK(pll, "pll.0", MCF_CLK);
arch/m68k/coldfire/m527x.c
29
DEFINE_CLK(pll, "pll.0", MCF_CLK);
arch/m68k/coldfire/m528x.c
30
DEFINE_CLK(pll, "pll.0", MCF_CLK);
arch/m68k/coldfire/m5307.c
34
DEFINE_CLK(pll, "pll.0", MCF_CLK);
arch/m68k/coldfire/m5407.c
25
DEFINE_CLK(pll, "pll.0", MCF_CLK);
arch/m68k/coldfire/m54xx.c
34
DEFINE_CLK(pll, "pll.0", MCF_CLK);
arch/m68k/kernel/time.c
109
struct rtc_pll_info pll;
arch/m68k/kernel/time.c
114
if (!mach_get_rtc_pll || mach_get_rtc_pll(&pll))
arch/m68k/kernel/time.c
116
return copy_to_user(argp, &pll, sizeof pll) ? -EFAULT : 0;
arch/m68k/kernel/time.c
123
if (copy_from_user(&pll, argp, sizeof(pll)))
arch/m68k/kernel/time.c
125
return mach_set_rtc_pll(&pll);
arch/m68k/q40/config.c
229
static int q40_get_rtc_pll(struct rtc_pll_info *pll)
arch/m68k/q40/config.c
233
pll->pll_ctrl = 0;
arch/m68k/q40/config.c
234
pll->pll_value = tmp & Q40_RTC_PLL_MASK;
arch/m68k/q40/config.c
236
pll->pll_value = -pll->pll_value;
arch/m68k/q40/config.c
237
pll->pll_max = 31;
arch/m68k/q40/config.c
238
pll->pll_min = -31;
arch/m68k/q40/config.c
239
pll->pll_posmult = 512;
arch/m68k/q40/config.c
240
pll->pll_negmult = 256;
arch/m68k/q40/config.c
241
pll->pll_clock = 125829120;
arch/m68k/q40/config.c
246
static int q40_set_rtc_pll(struct rtc_pll_info *pll)
arch/m68k/q40/config.c
248
if (!pll->pll_ctrl) {
arch/m68k/q40/config.c
251
int tmp = (pll->pll_value & 31) | (pll->pll_value<0 ? 32 : 0) |
arch/m68k/q40/config.c
39
static int q40_get_rtc_pll(struct rtc_pll_info *pll);
arch/m68k/q40/config.c
40
static int q40_set_rtc_pll(struct rtc_pll_info *pll);
arch/mips/ath79/clock.c
105
pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG);
arch/mips/ath79/clock.c
107
div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1;
arch/mips/ath79/clock.c
110
div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
arch/mips/ath79/clock.c
113
div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
arch/mips/ath79/clock.c
116
div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
arch/mips/ath79/clock.c
127
u32 pll;
arch/mips/ath79/clock.c
131
pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG);
arch/mips/ath79/clock.c
133
mult = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK);
arch/mips/ath79/clock.c
134
div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2;
arch/mips/ath79/clock.c
136
ddr_div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
arch/mips/ath79/clock.c
137
ahb_div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
arch/mips/ath79/clock.c
238
u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv;
arch/mips/ath79/clock.c
253
pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);
arch/mips/ath79/clock.c
254
if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
arch/mips/ath79/clock.c
255
out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
arch/mips/ath79/clock.c
257
pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG);
arch/mips/ath79/clock.c
258
nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
arch/mips/ath79/clock.c
260
nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
arch/mips/ath79/clock.c
261
ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
arch/mips/ath79/clock.c
265
pll = __raw_readl(pll_base + AR934X_PLL_CPU_CONFIG_REG);
arch/mips/ath79/clock.c
266
out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
arch/mips/ath79/clock.c
268
ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
arch/mips/ath79/clock.c
270
nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
arch/mips/ath79/clock.c
272
nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
arch/mips/ath79/clock.c
280
pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG);
arch/mips/ath79/clock.c
281
if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
arch/mips/ath79/clock.c
282
out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
arch/mips/ath79/clock.c
284
pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG);
arch/mips/ath79/clock.c
285
nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
arch/mips/ath79/clock.c
287
nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
arch/mips/ath79/clock.c
288
ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
arch/mips/ath79/clock.c
292
pll = __raw_readl(pll_base + AR934X_PLL_DDR_CONFIG_REG);
arch/mips/ath79/clock.c
293
out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
arch/mips/ath79/clock.c
295
ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
arch/mips/ath79/clock.c
297
nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
arch/mips/ath79/clock.c
299
nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
arch/mips/ath79/clock.c
356
u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
arch/mips/ath79/clock.c
368
pll = __raw_readl(pll_base + QCA953X_PLL_CPU_CONFIG_REG);
arch/mips/ath79/clock.c
369
out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
arch/mips/ath79/clock.c
371
ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
arch/mips/ath79/clock.c
373
nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) &
arch/mips/ath79/clock.c
375
frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
arch/mips/ath79/clock.c
382
pll = __raw_readl(pll_base + QCA953X_PLL_DDR_CONFIG_REG);
arch/mips/ath79/clock.c
383
out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
arch/mips/ath79/clock.c
385
ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
arch/mips/ath79/clock.c
387
nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) &
arch/mips/ath79/clock.c
389
frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
arch/mips/ath79/clock.c
439
u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
arch/mips/ath79/clock.c
451
pll = __raw_readl(pll_base + QCA955X_PLL_CPU_CONFIG_REG);
arch/mips/ath79/clock.c
452
out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
arch/mips/ath79/clock.c
454
ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
arch/mips/ath79/clock.c
456
nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) &
arch/mips/ath79/clock.c
458
frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
arch/mips/ath79/clock.c
465
pll = __raw_readl(pll_base + QCA955X_PLL_DDR_CONFIG_REG);
arch/mips/ath79/clock.c
466
out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
arch/mips/ath79/clock.c
468
ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
arch/mips/ath79/clock.c
470
nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) &
arch/mips/ath79/clock.c
472
frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
arch/mips/ath79/clock.c
522
u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv;
arch/mips/ath79/clock.c
544
pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG_REG);
arch/mips/ath79/clock.c
545
out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
arch/mips/ath79/clock.c
547
ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
arch/mips/ath79/clock.c
550
pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG1_REG);
arch/mips/ath79/clock.c
551
nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
arch/mips/ath79/clock.c
553
hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
arch/mips/ath79/clock.c
555
lfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT) &
arch/mips/ath79/clock.c
563
pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG_REG);
arch/mips/ath79/clock.c
564
out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
arch/mips/ath79/clock.c
566
ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
arch/mips/ath79/clock.c
568
pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG1_REG);
arch/mips/ath79/clock.c
569
nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
arch/mips/ath79/clock.c
571
hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
arch/mips/ath79/clock.c
573
lfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT) &
arch/mips/ath79/clock.c
99
u32 pll;
drivers/accel/ivpu/ivpu_drv.c
237
args->value = ivpu_hw_btrs_pll_ratio_to_hz(vdev, vdev->hw->pll.max_ratio);
drivers/accel/ivpu/ivpu_fw.c
692
boot_params->min_freq_pll_ratio = vdev->hw->pll.min_ratio;
drivers/accel/ivpu/ivpu_fw.c
693
boot_params->pn_freq_pll_ratio = vdev->hw->pll.pn_ratio;
drivers/accel/ivpu/ivpu_fw.c
694
boot_params->max_freq_pll_ratio = vdev->hw->pll.max_ratio;
drivers/accel/ivpu/ivpu_hw.c
347
vdev->hw->pll.profiling_freq = PLL_PROFILING_FREQ_DEFAULT;
drivers/accel/ivpu/ivpu_hw.c
352
vdev->hw->pll.profiling_freq = PLL_PROFILING_FREQ_HIGH;
drivers/accel/ivpu/ivpu_hw.c
354
vdev->hw->pll.profiling_freq = PLL_PROFILING_FREQ_DEFAULT;
drivers/accel/ivpu/ivpu_hw.h
43
} pll;
drivers/accel/ivpu/ivpu_hw.h
94
return vdev->hw->pll.profiling_freq;
drivers/accel/ivpu/ivpu_hw_btrs.c
109
hw->pll.min_ratio = clamp_t(u8, ivpu_pll_min_ratio, hw->pll.min_ratio, hw->pll.max_ratio);
drivers/accel/ivpu/ivpu_hw_btrs.c
110
hw->pll.max_ratio = clamp_t(u8, ivpu_pll_max_ratio, hw->pll.min_ratio, hw->pll.max_ratio);
drivers/accel/ivpu/ivpu_hw_btrs.c
111
hw->pll.pn_ratio = clamp_t(u8, hw->pll.pn_ratio, hw->pll.min_ratio, hw->pll.max_ratio);
drivers/accel/ivpu/ivpu_hw_btrs.c
112
hw->pll.cfg_max_ratio = hw->pll.max_ratio;
drivers/accel/ivpu/ivpu_hw_btrs.c
113
hw->pll.cfg_min_ratio = hw->pll.min_ratio;
drivers/accel/ivpu/ivpu_hw_btrs.c
174
hw->pll.profiling_freq = PLL_PROFILING_FREQ_DEFAULT;
drivers/accel/ivpu/ivpu_hw_btrs.c
295
wp->min = hw->pll.min_ratio;
drivers/accel/ivpu/ivpu_hw_btrs.c
296
wp->max = hw->pll.max_ratio;
drivers/accel/ivpu/ivpu_hw_btrs.c
299
wp->target = enable ? hw->pll.pn_ratio : 0;
drivers/accel/ivpu/ivpu_hw_btrs.c
304
wp->target = hw->pll.pn_ratio;
drivers/accel/ivpu/ivpu_hw_btrs.c
541
if (vdev->hw->pll.profiling_freq == PLL_PROFILING_FREQ_DEFAULT)
drivers/accel/ivpu/ivpu_hw_btrs.c
634
u8 min_ratio = clamp_t(u8, cfg_min_ratio, vdev->hw->pll.min_ratio, cfg_max_ratio);
drivers/accel/ivpu/ivpu_hw_btrs.c
635
u8 pn_ratio = clamp_t(u8, vdev->hw->pll.pn_ratio, min_ratio, cfg_max_ratio);
drivers/accel/ivpu/ivpu_hw_btrs.c
660
vdev->hw->pll.cfg_min_ratio = cfg_min_ratio;
drivers/accel/ivpu/ivpu_hw_btrs.c
661
vdev->hw->pll.cfg_max_ratio = cfg_max_ratio;
drivers/accel/ivpu/ivpu_hw_btrs.c
674
u8 cfg_max_ratio = clamp_t(u8, ratio, vdev->hw->pll.min_ratio, vdev->hw->pll.max_ratio);
drivers/accel/ivpu/ivpu_hw_btrs.c
676
return ivpu_hw_btrs_cfg_freq_set(vdev, vdev->hw->pll.cfg_min_ratio, cfg_max_ratio);
drivers/accel/ivpu/ivpu_hw_btrs.c
682
u8 cfg_min_ratio = clamp_t(u8, ratio, vdev->hw->pll.min_ratio, vdev->hw->pll.max_ratio);
drivers/accel/ivpu/ivpu_hw_btrs.c
684
return ivpu_hw_btrs_cfg_freq_set(vdev, cfg_min_ratio, vdev->hw->pll.cfg_max_ratio);
drivers/accel/ivpu/ivpu_hw_btrs.c
689
if (vdev->hw->pll.min_ratio == vdev->hw->pll.cfg_min_ratio &&
drivers/accel/ivpu/ivpu_hw_btrs.c
690
vdev->hw->pll.max_ratio == vdev->hw->pll.cfg_max_ratio)
drivers/accel/ivpu/ivpu_hw_btrs.c
694
vdev->hw->pll.cfg_min_ratio,
drivers/accel/ivpu/ivpu_hw_btrs.c
695
vdev->hw->pll.cfg_max_ratio);
drivers/accel/ivpu/ivpu_hw_btrs.c
708
u32 pll = pll_config_get_mtl(vdev);
drivers/accel/ivpu/ivpu_hw_btrs.c
711
pll, pll_ratio_to_mhz_mtl(pll));
drivers/accel/ivpu/ivpu_hw_btrs.c
762
u32 pll = pll_config_get_lnl(vdev);
drivers/accel/ivpu/ivpu_hw_btrs.c
765
pll, pll_ratio_to_mhz_lnl(pll));
drivers/accel/ivpu/ivpu_hw_btrs.c
80
hw->pll.min_ratio = REG_GET_FLD(VPU_HW_BTRS_MTL_FMIN_FUSE, MIN_RATIO, fmin_fuse);
drivers/accel/ivpu/ivpu_hw_btrs.c
81
hw->pll.pn_ratio = REG_GET_FLD(VPU_HW_BTRS_MTL_FMIN_FUSE, PN_RATIO, fmin_fuse);
drivers/accel/ivpu/ivpu_hw_btrs.c
84
hw->pll.max_ratio = REG_GET_FLD(VPU_HW_BTRS_MTL_FMAX_FUSE, MAX_RATIO, fmax_fuse);
drivers/accel/ivpu/ivpu_hw_btrs.c
93
hw->pll.min_ratio = REG_GET_FLD(VPU_HW_BTRS_LNL_FMIN_FUSE, MIN_RATIO, fmin_fuse);
drivers/accel/ivpu/ivpu_hw_btrs.c
94
hw->pll.pn_ratio = REG_GET_FLD(VPU_HW_BTRS_LNL_FMIN_FUSE, PN_RATIO, fmin_fuse);
drivers/accel/ivpu/ivpu_hw_btrs.c
97
hw->pll.max_ratio = REG_GET_FLD(VPU_HW_BTRS_LNL_FMAX_FUSE, MAX_RATIO, fmax_fuse);
drivers/accel/ivpu/ivpu_hw_ip.c
680
bool high = vdev->hw->pll.profiling_freq == PLL_PROFILING_FREQ_HIGH;
drivers/accel/ivpu/ivpu_sysfs.c
125
u32 freq_mhz = ivpu_hw_btrs_pll_ratio_to_mhz(vdev, vdev->hw->pll.min_ratio);
drivers/accel/ivpu/ivpu_sysfs.c
136
u32 freq_mhz = ivpu_hw_btrs_pll_ratio_to_mhz(vdev, vdev->hw->pll.pn_ratio);
drivers/accel/ivpu/ivpu_sysfs.c
147
u32 freq_mhz = ivpu_hw_btrs_pll_ratio_to_mhz(vdev, vdev->hw->pll.max_ratio);
drivers/accel/ivpu/ivpu_sysfs.c
158
u32 freq_mhz = ivpu_hw_btrs_pll_ratio_to_mhz(vdev, vdev->hw->pll.cfg_min_ratio);
drivers/accel/ivpu/ivpu_sysfs.c
188
u32 freq_mhz = ivpu_hw_btrs_pll_ratio_to_mhz(vdev, vdev->hw->pll.cfg_max_ratio);
drivers/bcma/driver_chipcommon_pmu.c
461
u32 pll;
drivers/bcma/driver_chipcommon_pmu.c
468
pll = BCMA_CC_PMU5356_MAINPLL_PLL0;
drivers/bcma/driver_chipcommon_pmu.c
472
pll = BCMA_CC_PMU5357_MAINPLL_PLL0;
drivers/bcma/driver_chipcommon_pmu.c
475
pll = BCMA_CC_PMU4716_MAINPLL_PLL0;
drivers/bcma/driver_chipcommon_pmu.c
479
return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
drivers/clk/actions/owl-pll.c
119
struct owl_pll *pll = hw_to_owl_pll(hw);
drivers/clk/actions/owl-pll.c
120
struct owl_pll_hw *pll_hw = &pll->pll_hw;
drivers/clk/actions/owl-pll.c
121
const struct owl_clk_common *common = &pll->common;
drivers/clk/actions/owl-pll.c
146
struct owl_pll *pll = hw_to_owl_pll(hw);
drivers/clk/actions/owl-pll.c
147
const struct owl_clk_common *common = &pll->common;
drivers/clk/actions/owl-pll.c
149
owl_pll_set(common, &pll->pll_hw, true);
drivers/clk/actions/owl-pll.c
156
struct owl_pll *pll = hw_to_owl_pll(hw);
drivers/clk/actions/owl-pll.c
157
const struct owl_clk_common *common = &pll->common;
drivers/clk/actions/owl-pll.c
159
owl_pll_set(common, &pll->pll_hw, false);
drivers/clk/actions/owl-pll.c
165
struct owl_pll *pll = hw_to_owl_pll(hw);
drivers/clk/actions/owl-pll.c
166
struct owl_pll_hw *pll_hw = &pll->pll_hw;
drivers/clk/actions/owl-pll.c
167
const struct owl_clk_common *common = &pll->common;
drivers/clk/actions/owl-pll.c
62
struct owl_pll *pll = hw_to_owl_pll(hw);
drivers/clk/actions/owl-pll.c
63
struct owl_pll_hw *pll_hw = &pll->pll_hw;
drivers/clk/actions/owl-pll.c
91
struct owl_pll *pll = hw_to_owl_pll(hw);
drivers/clk/actions/owl-pll.c
92
struct owl_pll_hw *pll_hw = &pll->pll_hw;
drivers/clk/actions/owl-pll.c
93
const struct owl_clk_common *common = &pll->common;
drivers/clk/aspeed/clk-ast2700.c
120
struct ast2700_clk_pll_data pll;
drivers/clk/aspeed/clk-ast2700.c
296
.data = { .pll = { \
drivers/clk/aspeed/clk-ast2700.c
943
const struct ast2700_clk_pll_data *pll = &clk->data.pll;
drivers/clk/aspeed/clk-ast2700.c
945
reg = clk_ctrl->base + pll->reg;
drivers/clk/aspeed/clk-ast2700.c
946
phw = hws[pll->parent_id];
drivers/clk/aspeed/clk-ast2700.c
949
const struct ast2700_clk_pll_data *pll = &clk->data.pll;
drivers/clk/aspeed/clk-ast2700.c
951
reg = clk_ctrl->base + pll->reg;
drivers/clk/aspeed/clk-ast2700.c
952
phw = hws[pll->parent_id];
drivers/clk/aspeed/clk-ast2700.c
955
const struct ast2700_clk_pll_data *pll = &clk->data.pll;
drivers/clk/aspeed/clk-ast2700.c
957
reg = clk_ctrl->base + pll->reg;
drivers/clk/aspeed/clk-ast2700.c
958
phw = hws[pll->parent_id];
drivers/clk/aspeed/clk-ast2700.c
977
const struct ast2700_clk_pll_data *pll = &clk->data.pll;
drivers/clk/aspeed/clk-ast2700.c
979
reg = clk_ctrl->base + pll->reg;
drivers/clk/aspeed/clk-ast2700.c
980
phw = hws[pll->parent_id];
drivers/clk/at91/clk-pll.c
100
struct clk_pll *pll = to_clk_pll(hw);
drivers/clk/at91/clk-pll.c
102
return clk_pll_ready(pll->regmap, pll->id);
drivers/clk/at91/clk-pll.c
107
struct clk_pll *pll = to_clk_pll(hw);
drivers/clk/at91/clk-pll.c
108
unsigned int mask = pll->layout->pllr_mask;
drivers/clk/at91/clk-pll.c
110
regmap_update_bits(pll->regmap, PLL_REG(pll->id), mask, ~mask);
drivers/clk/at91/clk-pll.c
116
struct clk_pll *pll = to_clk_pll(hw);
drivers/clk/at91/clk-pll.c
118
if (!pll->div || !pll->mul)
drivers/clk/at91/clk-pll.c
121
return (parent_rate / pll->div) * (pll->mul + 1);
drivers/clk/at91/clk-pll.c
124
static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate,
drivers/clk/at91/clk-pll.c
128
const struct clk_pll_layout *layout = pll->layout;
drivers/clk/at91/clk-pll.c
130
pll->characteristics;
drivers/clk/at91/clk-pll.c
237
struct clk_pll *pll = to_clk_pll(hw);
drivers/clk/at91/clk-pll.c
239
req->rate = clk_pll_get_best_div_mul(pll, req->rate, req->best_parent_rate,
drivers/clk/at91/clk-pll.c
248
struct clk_pll *pll = to_clk_pll(hw);
drivers/clk/at91/clk-pll.c
254
ret = clk_pll_get_best_div_mul(pll, rate, parent_rate,
drivers/clk/at91/clk-pll.c
259
pll->range = index;
drivers/clk/at91/clk-pll.c
260
pll->div = div;
drivers/clk/at91/clk-pll.c
261
pll->mul = mul;
drivers/clk/at91/clk-pll.c
268
struct clk_pll *pll = to_clk_pll(hw);
drivers/clk/at91/clk-pll.c
271
pll->pms.parent_rate = clk_hw_get_rate(parent_hw);
drivers/clk/at91/clk-pll.c
272
pll->pms.rate = clk_pll_recalc_rate(&pll->hw, pll->pms.parent_rate);
drivers/clk/at91/clk-pll.c
273
pll->pms.status = clk_pll_ready(pll->regmap, PLL_REG(pll->id));
drivers/clk/at91/clk-pll.c
280
struct clk_pll *pll = to_clk_pll(hw);
drivers/clk/at91/clk-pll.c
285
if (pll->characteristics->out)
drivers/clk/at91/clk-pll.c
286
out = pll->characteristics->out[pll->range];
drivers/clk/at91/clk-pll.c
288
regmap_read(pll->regmap, PLL_REG(pll->id), &pllr);
drivers/clk/at91/clk-pll.c
290
calc_rate = (pll->pms.parent_rate / PLL_DIV(pllr)) *
drivers/clk/at91/clk-pll.c
291
(PLL_MUL(pllr, pll->layout) + 1);
drivers/clk/at91/clk-pll.c
295
if (pll->pms.rate != calc_rate ||
drivers/clk/at91/clk-pll.c
296
pll->pms.status != clk_pll_ready(pll->regmap, PLL_REG(pll->id)) ||
drivers/clk/at91/clk-pll.c
319
struct clk_pll *pll;
drivers/clk/at91/clk-pll.c
329
pll = kzalloc_obj(*pll);
drivers/clk/at91/clk-pll.c
330
if (!pll)
drivers/clk/at91/clk-pll.c
339
pll->id = id;
drivers/clk/at91/clk-pll.c
340
pll->hw.init = &init;
drivers/clk/at91/clk-pll.c
341
pll->layout = layout;
drivers/clk/at91/clk-pll.c
342
pll->characteristics = characteristics;
drivers/clk/at91/clk-pll.c
343
pll->regmap = regmap;
drivers/clk/at91/clk-pll.c
345
pll->div = PLL_DIV(pllr);
drivers/clk/at91/clk-pll.c
346
pll->mul = PLL_MUL(pllr, layout);
drivers/clk/at91/clk-pll.c
348
hw = &pll->hw;
drivers/clk/at91/clk-pll.c
349
ret = clk_hw_register(NULL, &pll->hw);
drivers/clk/at91/clk-pll.c
351
kfree(pll);
drivers/clk/at91/clk-pll.c
57
struct clk_pll *pll = to_clk_pll(hw);
drivers/clk/at91/clk-pll.c
58
struct regmap *regmap = pll->regmap;
drivers/clk/at91/clk-pll.c
59
const struct clk_pll_layout *layout = pll->layout;
drivers/clk/at91/clk-pll.c
61
pll->characteristics;
drivers/clk/at91/clk-pll.c
62
u8 id = pll->id;
drivers/clk/at91/clk-pll.c
77
(div == pll->div && mul == pll->mul))
drivers/clk/at91/clk-pll.c
81
out = characteristics->out[pll->range];
drivers/clk/at91/clk-pll.c
85
characteristics->icpll[pll->range] << PLL_ICPR_SHIFT(id));
drivers/clk/at91/clk-pll.c
88
pll->div | (PLL_MAX_COUNT << PLL_COUNT_SHIFT) |
drivers/clk/at91/clk-pll.c
90
((pll->mul & layout->mul_mask) << layout->mul_shift));
drivers/clk/at91/clk-pll.c
92
while (!clk_pll_ready(regmap, pll->id))
drivers/clk/bcm/clk-bcm2835.c
1347
struct bcm2835_pll *pll;
drivers/clk/bcm/clk-bcm2835.c
1360
pll = kzalloc_obj(*pll);
drivers/clk/bcm/clk-bcm2835.c
1361
if (!pll)
drivers/clk/bcm/clk-bcm2835.c
1364
pll->cprman = cprman;
drivers/clk/bcm/clk-bcm2835.c
1365
pll->data = pll_data;
drivers/clk/bcm/clk-bcm2835.c
1366
pll->hw.init = &init;
drivers/clk/bcm/clk-bcm2835.c
1368
ret = devm_clk_hw_register(cprman->dev, &pll->hw);
drivers/clk/bcm/clk-bcm2835.c
1370
kfree(pll);
drivers/clk/bcm/clk-bcm2835.c
1373
return &pll->hw;
drivers/clk/bcm/clk-bcm2835.c
525
struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
drivers/clk/bcm/clk-bcm2835.c
526
struct bcm2835_cprman *cprman = pll->cprman;
drivers/clk/bcm/clk-bcm2835.c
527
const struct bcm2835_pll_data *data = pll->data;
drivers/clk/bcm/clk-bcm2835.c
576
struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
drivers/clk/bcm/clk-bcm2835.c
577
const struct bcm2835_pll_data *data = pll->data;
drivers/clk/bcm/clk-bcm2835.c
595
struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
drivers/clk/bcm/clk-bcm2835.c
596
struct bcm2835_cprman *cprman = pll->cprman;
drivers/clk/bcm/clk-bcm2835.c
597
const struct bcm2835_pll_data *data = pll->data;
drivers/clk/bcm/clk-bcm2835.c
621
struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
drivers/clk/bcm/clk-bcm2835.c
622
struct bcm2835_cprman *cprman = pll->cprman;
drivers/clk/bcm/clk-bcm2835.c
623
const struct bcm2835_pll_data *data = pll->data;
drivers/clk/bcm/clk-bcm2835.c
635
struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
drivers/clk/bcm/clk-bcm2835.c
636
struct bcm2835_cprman *cprman = pll->cprman;
drivers/clk/bcm/clk-bcm2835.c
637
const struct bcm2835_pll_data *data = pll->data;
drivers/clk/bcm/clk-bcm2835.c
689
struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
drivers/clk/bcm/clk-bcm2835.c
690
struct bcm2835_cprman *cprman = pll->cprman;
drivers/clk/bcm/clk-bcm2835.c
691
const struct bcm2835_pll_data *data = pll->data;
drivers/clk/bcm/clk-bcm2835.c
758
struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
drivers/clk/bcm/clk-bcm2835.c
759
struct bcm2835_cprman *cprman = pll->cprman;
drivers/clk/bcm/clk-bcm2835.c
760
const struct bcm2835_pll_data *data = pll->data;
drivers/clk/bcm/clk-iproc-armpll.c
106
static int __get_mdiv(struct iproc_arm_pll *pll)
drivers/clk/bcm/clk-iproc-armpll.c
112
fid = __get_fid(pll);
drivers/clk/bcm/clk-iproc-armpll.c
121
val = readl(pll->base + IPROC_CLK_PLLARMC_OFFSET);
drivers/clk/bcm/clk-iproc-armpll.c
128
val = readl(pll->base + IPROC_CLK_PLLARMCTL5_OFFSET);
drivers/clk/bcm/clk-iproc-armpll.c
141
static unsigned int __get_ndiv(struct iproc_arm_pll *pll)
drivers/clk/bcm/clk-iproc-armpll.c
146
val = readl(pll->base + IPROC_CLK_PLLARM_OFFSET_OFFSET);
drivers/clk/bcm/clk-iproc-armpll.c
160
val = readl(pll->base + IPROC_CLK_PLLARMA_OFFSET);
drivers/clk/bcm/clk-iproc-armpll.c
166
val = readl(pll->base + IPROC_CLK_PLLARMB_OFFSET);
drivers/clk/bcm/clk-iproc-armpll.c
188
struct iproc_arm_pll *pll = to_iproc_arm_pll(hw);
drivers/clk/bcm/clk-iproc-armpll.c
195
val = readl(pll->base + IPROC_CLK_PLLARMC_OFFSET);
drivers/clk/bcm/clk-iproc-armpll.c
197
pll->rate = parent_rate;
drivers/clk/bcm/clk-iproc-armpll.c
198
return pll->rate;
drivers/clk/bcm/clk-iproc-armpll.c
202
val = readl(pll->base + IPROC_CLK_PLLARMA_OFFSET);
drivers/clk/bcm/clk-iproc-armpll.c
204
pll->rate = 0;
drivers/clk/bcm/clk-iproc-armpll.c
213
ndiv = __get_ndiv(pll);
drivers/clk/bcm/clk-iproc-armpll.c
214
mdiv = __get_mdiv(pll);
drivers/clk/bcm/clk-iproc-armpll.c
216
pll->rate = 0;
drivers/clk/bcm/clk-iproc-armpll.c
219
pll->rate = (ndiv * parent_rate) >> 20;
drivers/clk/bcm/clk-iproc-armpll.c
220
pll->rate = (pll->rate / pdiv) / mdiv;
drivers/clk/bcm/clk-iproc-armpll.c
223
pll->rate, parent_rate);
drivers/clk/bcm/clk-iproc-armpll.c
227
return pll->rate;
drivers/clk/bcm/clk-iproc-armpll.c
237
struct iproc_arm_pll *pll;
drivers/clk/bcm/clk-iproc-armpll.c
241
pll = kzalloc_obj(*pll);
drivers/clk/bcm/clk-iproc-armpll.c
242
if (WARN_ON(!pll))
drivers/clk/bcm/clk-iproc-armpll.c
245
pll->base = of_iomap(node, 0);
drivers/clk/bcm/clk-iproc-armpll.c
246
if (WARN_ON(!pll->base))
drivers/clk/bcm/clk-iproc-armpll.c
255
pll->hw.init = &init;
drivers/clk/bcm/clk-iproc-armpll.c
257
ret = clk_hw_register(NULL, &pll->hw);
drivers/clk/bcm/clk-iproc-armpll.c
261
ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll->hw);
drivers/clk/bcm/clk-iproc-armpll.c
268
clk_hw_unregister(&pll->hw);
drivers/clk/bcm/clk-iproc-armpll.c
270
iounmap(pll->base);
drivers/clk/bcm/clk-iproc-armpll.c
272
kfree(pll);
drivers/clk/bcm/clk-iproc-armpll.c
66
static unsigned int __get_fid(struct iproc_arm_pll *pll)
drivers/clk/bcm/clk-iproc-armpll.c
71
val = readl(pll->base + IPROC_CLK_ARM_DIV_OFFSET);
drivers/clk/bcm/clk-iproc-armpll.c
80
val = readl(pll->base + IPROC_CLK_POLICY_FREQ_OFFSET);
drivers/clk/bcm/clk-iproc-armpll.c
84
val = readl(pll->base + IPROC_CLK_POLICY_DBG_OFFSET);
drivers/clk/bcm/clk-iproc-pll.c
118
static int pll_get_rate_index(struct iproc_pll *pll, unsigned int target_rate)
drivers/clk/bcm/clk-iproc-pll.c
122
for (i = 0; i < pll->num_vco_entries; i++)
drivers/clk/bcm/clk-iproc-pll.c
123
if (target_rate == pll->vco_param[i].rate)
drivers/clk/bcm/clk-iproc-pll.c
126
if (i >= pll->num_vco_entries)
drivers/clk/bcm/clk-iproc-pll.c
147
static int pll_wait_for_lock(struct iproc_pll *pll)
drivers/clk/bcm/clk-iproc-pll.c
150
const struct iproc_pll_ctrl *ctrl = pll->ctrl;
drivers/clk/bcm/clk-iproc-pll.c
153
u32 val = readl(pll->status_base + ctrl->status.offset);
drivers/clk/bcm/clk-iproc-pll.c
163
static void iproc_pll_write(const struct iproc_pll *pll, void __iomem *base,
drivers/clk/bcm/clk-iproc-pll.c
166
const struct iproc_pll_ctrl *ctrl = pll->ctrl;
drivers/clk/bcm/clk-iproc-pll.c
171
(base == pll->status_base || base == pll->control_base)))
drivers/clk/bcm/clk-iproc-pll.c
175
static void __pll_disable(struct iproc_pll *pll)
drivers/clk/bcm/clk-iproc-pll.c
177
const struct iproc_pll_ctrl *ctrl = pll->ctrl;
drivers/clk/bcm/clk-iproc-pll.c
181
val = readl(pll->asiu_base + ctrl->asiu.offset);
drivers/clk/bcm/clk-iproc-pll.c
183
iproc_pll_write(pll, pll->asiu_base, ctrl->asiu.offset, val);
drivers/clk/bcm/clk-iproc-pll.c
187
val = readl(pll->control_base + ctrl->aon.offset);
drivers/clk/bcm/clk-iproc-pll.c
189
iproc_pll_write(pll, pll->control_base, ctrl->aon.offset, val);
drivers/clk/bcm/clk-iproc-pll.c
192
if (pll->pwr_base) {
drivers/clk/bcm/clk-iproc-pll.c
194
val = readl(pll->pwr_base + ctrl->aon.offset);
drivers/clk/bcm/clk-iproc-pll.c
196
iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val);
drivers/clk/bcm/clk-iproc-pll.c
200
iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val);
drivers/clk/bcm/clk-iproc-pll.c
204
static int __pll_enable(struct iproc_pll *pll)
drivers/clk/bcm/clk-iproc-pll.c
206
const struct iproc_pll_ctrl *ctrl = pll->ctrl;
drivers/clk/bcm/clk-iproc-pll.c
210
val = readl(pll->control_base + ctrl->aon.offset);
drivers/clk/bcm/clk-iproc-pll.c
212
iproc_pll_write(pll, pll->control_base, ctrl->aon.offset, val);
drivers/clk/bcm/clk-iproc-pll.c
215
if (pll->pwr_base) {
drivers/clk/bcm/clk-iproc-pll.c
217
val = readl(pll->pwr_base + ctrl->aon.offset);
drivers/clk/bcm/clk-iproc-pll.c
220
iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val);
drivers/clk/bcm/clk-iproc-pll.c
225
val = readl(pll->asiu_base + ctrl->asiu.offset);
drivers/clk/bcm/clk-iproc-pll.c
227
iproc_pll_write(pll, pll->asiu_base, ctrl->asiu.offset, val);
drivers/clk/bcm/clk-iproc-pll.c
233
static void __pll_put_in_reset(struct iproc_pll *pll)
drivers/clk/bcm/clk-iproc-pll.c
236
const struct iproc_pll_ctrl *ctrl = pll->ctrl;
drivers/clk/bcm/clk-iproc-pll.c
239
val = readl(pll->control_base + reset->offset);
drivers/clk/bcm/clk-iproc-pll.c
244
iproc_pll_write(pll, pll->control_base, reset->offset, val);
drivers/clk/bcm/clk-iproc-pll.c
247
static void __pll_bring_out_reset(struct iproc_pll *pll, unsigned int kp,
drivers/clk/bcm/clk-iproc-pll.c
251
const struct iproc_pll_ctrl *ctrl = pll->ctrl;
drivers/clk/bcm/clk-iproc-pll.c
255
val = readl(pll->control_base + dig_filter->offset);
drivers/clk/bcm/clk-iproc-pll.c
261
iproc_pll_write(pll, pll->control_base, dig_filter->offset, val);
drivers/clk/bcm/clk-iproc-pll.c
263
val = readl(pll->control_base + reset->offset);
drivers/clk/bcm/clk-iproc-pll.c
268
iproc_pll_write(pll, pll->control_base, reset->offset, val);
drivers/clk/bcm/clk-iproc-pll.c
276
static bool pll_fractional_change_only(struct iproc_pll *pll,
drivers/clk/bcm/clk-iproc-pll.c
279
const struct iproc_pll_ctrl *ctrl = pll->ctrl;
drivers/clk/bcm/clk-iproc-pll.c
285
val = readl(pll->status_base + ctrl->status.offset);
drivers/clk/bcm/clk-iproc-pll.c
289
val = readl(pll->control_base + ctrl->ndiv_int.offset);
drivers/clk/bcm/clk-iproc-pll.c
296
val = readl(pll->control_base + ctrl->pdiv.offset);
drivers/clk/bcm/clk-iproc-pll.c
308
struct iproc_pll *pll = clk->pll;
drivers/clk/bcm/clk-iproc-pll.c
309
const struct iproc_pll_ctrl *ctrl = pll->ctrl;
drivers/clk/bcm/clk-iproc-pll.c
348
ret = __pll_enable(pll);
drivers/clk/bcm/clk-iproc-pll.c
354
if (pll_fractional_change_only(clk->pll, vco)) {
drivers/clk/bcm/clk-iproc-pll.c
357
val = readl(pll->control_base + ctrl->ndiv_frac.offset);
drivers/clk/bcm/clk-iproc-pll.c
361
iproc_pll_write(pll, pll->control_base,
drivers/clk/bcm/clk-iproc-pll.c
368
__pll_put_in_reset(pll);
drivers/clk/bcm/clk-iproc-pll.c
372
val = readl(pll->control_base + ctrl->macro_mode.offset);
drivers/clk/bcm/clk-iproc-pll.c
376
iproc_pll_write(pll, pll->control_base,
drivers/clk/bcm/clk-iproc-pll.c
380
iproc_pll_write(pll, pll->control_base, ctrl->vco_ctrl.u_offset, 0);
drivers/clk/bcm/clk-iproc-pll.c
382
val = readl(pll->control_base + ctrl->vco_ctrl.l_offset);
drivers/clk/bcm/clk-iproc-pll.c
392
iproc_pll_write(pll, pll->control_base, ctrl->vco_ctrl.l_offset, val);
drivers/clk/bcm/clk-iproc-pll.c
395
val = readl(pll->control_base + ctrl->ndiv_int.offset);
drivers/clk/bcm/clk-iproc-pll.c
398
iproc_pll_write(pll, pll->control_base, ctrl->ndiv_int.offset, val);
drivers/clk/bcm/clk-iproc-pll.c
402
val = readl(pll->control_base + ctrl->ndiv_frac.offset);
drivers/clk/bcm/clk-iproc-pll.c
406
iproc_pll_write(pll, pll->control_base, ctrl->ndiv_frac.offset,
drivers/clk/bcm/clk-iproc-pll.c
411
val = readl(pll->control_base + ctrl->pdiv.offset);
drivers/clk/bcm/clk-iproc-pll.c
414
iproc_pll_write(pll, pll->control_base, ctrl->pdiv.offset, val);
drivers/clk/bcm/clk-iproc-pll.c
416
__pll_bring_out_reset(pll, kp, ka, ki);
drivers/clk/bcm/clk-iproc-pll.c
418
ret = pll_wait_for_lock(pll);
drivers/clk/bcm/clk-iproc-pll.c
430
struct iproc_pll *pll = clk->pll;
drivers/clk/bcm/clk-iproc-pll.c
432
return __pll_enable(pll);
drivers/clk/bcm/clk-iproc-pll.c
438
struct iproc_pll *pll = clk->pll;
drivers/clk/bcm/clk-iproc-pll.c
439
const struct iproc_pll_ctrl *ctrl = pll->ctrl;
drivers/clk/bcm/clk-iproc-pll.c
444
__pll_disable(pll);
drivers/clk/bcm/clk-iproc-pll.c
451
struct iproc_pll *pll = clk->pll;
drivers/clk/bcm/clk-iproc-pll.c
452
const struct iproc_pll_ctrl *ctrl = pll->ctrl;
drivers/clk/bcm/clk-iproc-pll.c
462
val = readl(pll->status_base + ctrl->status.offset);
drivers/clk/bcm/clk-iproc-pll.c
471
val = readl(pll->control_base + ctrl->ndiv_int.offset);
drivers/clk/bcm/clk-iproc-pll.c
477
val = readl(pll->control_base + ctrl->ndiv_frac.offset);
drivers/clk/bcm/clk-iproc-pll.c
483
val = readl(pll->control_base + ctrl->pdiv.offset);
drivers/clk/bcm/clk-iproc-pll.c
501
struct iproc_pll *pll = clk->pll;
drivers/clk/bcm/clk-iproc-pll.c
502
const struct iproc_pll_ctrl *ctrl = pll->ctrl;
drivers/clk/bcm/clk-iproc-pll.c
522
if (!pll->vco_param)
drivers/clk/bcm/clk-iproc-pll.c
526
for (i = 0; i < pll->num_vco_entries; i++) {
drivers/clk/bcm/clk-iproc-pll.c
527
diff = abs(req->rate - pll->vco_param[i].rate);
drivers/clk/bcm/clk-iproc-pll.c
537
req->rate = pll->vco_param[best_idx].rate;
drivers/clk/bcm/clk-iproc-pll.c
546
struct iproc_pll *pll = clk->pll;
drivers/clk/bcm/clk-iproc-pll.c
547
const struct iproc_pll_ctrl *ctrl = pll->ctrl;
drivers/clk/bcm/clk-iproc-pll.c
556
rate_index = pll_get_rate_index(pll, rate);
drivers/clk/bcm/clk-iproc-pll.c
560
vco_param = pll->vco_param[rate_index];
drivers/clk/bcm/clk-iproc-pll.c
579
struct iproc_pll *pll = clk->pll;
drivers/clk/bcm/clk-iproc-pll.c
583
val = readl(pll->control_base + ctrl->enable.offset);
drivers/clk/bcm/clk-iproc-pll.c
585
iproc_pll_write(pll, pll->control_base, ctrl->enable.offset, val);
drivers/clk/bcm/clk-iproc-pll.c
588
val = readl(pll->control_base + ctrl->enable.offset);
drivers/clk/bcm/clk-iproc-pll.c
590
iproc_pll_write(pll, pll->control_base, ctrl->enable.offset, val);
drivers/clk/bcm/clk-iproc-pll.c
599
struct iproc_pll *pll = clk->pll;
drivers/clk/bcm/clk-iproc-pll.c
605
val = readl(pll->control_base + ctrl->enable.offset);
drivers/clk/bcm/clk-iproc-pll.c
607
iproc_pll_write(pll, pll->control_base, ctrl->enable.offset, val);
drivers/clk/bcm/clk-iproc-pll.c
615
struct iproc_pll *pll = clk->pll;
drivers/clk/bcm/clk-iproc-pll.c
623
val = readl(pll->control_base + ctrl->mdiv.offset);
drivers/clk/bcm/clk-iproc-pll.c
663
struct iproc_pll *pll = clk->pll;
drivers/clk/bcm/clk-iproc-pll.c
677
val = readl(pll->control_base + ctrl->mdiv.offset);
drivers/clk/bcm/clk-iproc-pll.c
684
iproc_pll_write(pll, pll->control_base, ctrl->mdiv.offset, val);
drivers/clk/bcm/clk-iproc-pll.c
701
static void iproc_pll_sw_cfg(struct iproc_pll *pll)
drivers/clk/bcm/clk-iproc-pll.c
703
const struct iproc_pll_ctrl *ctrl = pll->ctrl;
drivers/clk/bcm/clk-iproc-pll.c
708
val = readl(pll->control_base + ctrl->sw_ctrl.offset);
drivers/clk/bcm/clk-iproc-pll.c
710
iproc_pll_write(pll, pll->control_base, ctrl->sw_ctrl.offset,
drivers/clk/bcm/clk-iproc-pll.c
723
struct iproc_pll *pll;
drivers/clk/bcm/clk-iproc-pll.c
734
pll = kzalloc_obj(*pll);
drivers/clk/bcm/clk-iproc-pll.c
735
if (WARN_ON(!pll))
drivers/clk/bcm/clk-iproc-pll.c
747
pll->control_base = of_iomap(node, 0);
drivers/clk/bcm/clk-iproc-pll.c
748
if (WARN_ON(!pll->control_base))
drivers/clk/bcm/clk-iproc-pll.c
75
struct iproc_pll *pll;
drivers/clk/bcm/clk-iproc-pll.c
752
pll->pwr_base = of_iomap(node, 1);
drivers/clk/bcm/clk-iproc-pll.c
756
pll->asiu_base = of_iomap(node, 2);
drivers/clk/bcm/clk-iproc-pll.c
757
if (WARN_ON(!pll->asiu_base))
drivers/clk/bcm/clk-iproc-pll.c
765
pll->status_base = of_iomap(node, 2);
drivers/clk/bcm/clk-iproc-pll.c
766
if (!pll->status_base)
drivers/clk/bcm/clk-iproc-pll.c
769
pll->status_base = pll->control_base;
drivers/clk/bcm/clk-iproc-pll.c
772
pll->ctrl = pll_ctrl;
drivers/clk/bcm/clk-iproc-pll.c
775
iclk->pll = pll;
drivers/clk/bcm/clk-iproc-pll.c
791
pll->num_vco_entries = num_vco_entries;
drivers/clk/bcm/clk-iproc-pll.c
792
pll->vco_param = vco;
drivers/clk/bcm/clk-iproc-pll.c
795
iproc_pll_sw_cfg(pll);
drivers/clk/bcm/clk-iproc-pll.c
814
iclk->pll = pll;
drivers/clk/bcm/clk-iproc-pll.c
842
if (pll->status_base != pll->control_base)
drivers/clk/bcm/clk-iproc-pll.c
843
iounmap(pll->status_base);
drivers/clk/bcm/clk-iproc-pll.c
846
if (pll->asiu_base)
drivers/clk/bcm/clk-iproc-pll.c
847
iounmap(pll->asiu_base);
drivers/clk/bcm/clk-iproc-pll.c
850
if (pll->pwr_base)
drivers/clk/bcm/clk-iproc-pll.c
851
iounmap(pll->pwr_base);
drivers/clk/bcm/clk-iproc-pll.c
853
iounmap(pll->control_base);
drivers/clk/bcm/clk-iproc-pll.c
862
kfree(pll);
drivers/clk/berlin/berlin2-pll.c
44
struct berlin2_pll *pll = to_berlin2_pll(hw);
drivers/clk/berlin/berlin2-pll.c
45
struct berlin2_pll_map *map = &pll->map;
drivers/clk/berlin/berlin2-pll.c
49
val = readl_relaxed(pll->base + SPLL_CTRL0);
drivers/clk/berlin/berlin2-pll.c
57
val = readl_relaxed(pll->base + SPLL_CTRL1);
drivers/clk/berlin/berlin2-pll.c
82
struct berlin2_pll *pll;
drivers/clk/berlin/berlin2-pll.c
84
pll = kzalloc_obj(*pll);
drivers/clk/berlin/berlin2-pll.c
85
if (!pll)
drivers/clk/berlin/berlin2-pll.c
89
memcpy(&pll->map, map, sizeof(*map));
drivers/clk/berlin/berlin2-pll.c
90
pll->base = base;
drivers/clk/berlin/berlin2-pll.c
91
pll->hw.init = &init;
drivers/clk/berlin/berlin2-pll.c
98
return clk_hw_register(NULL, &pll->hw);
drivers/clk/clk-axm5516.c
51
struct axxia_pllclk *pll = to_axxia_pllclk(aclk);
drivers/clk/clk-axm5516.c
55
regmap_read(aclk->regmap, pll->reg, &control);
drivers/clk/clk-bm1880.c
133
struct bm1880_pll_clock pll;
drivers/clk/clk-bm1880.c
174
.pll.id = _id, \
drivers/clk/clk-bm1880.c
175
.pll.name = _name, \
drivers/clk/clk-bm1880.c
176
.pll.reg = _reg, \
drivers/clk/clk-bm1880.c
498
regval = readl(pll_hw->base + pll_hw->pll.reg);
drivers/clk/clk-bm1880.c
538
__func__, bm1880_clk->pll.name);
drivers/clk/clk-bm1880.c
542
data->hw_data.hws[clks[i].pll.id] = hw;
drivers/clk/clk-bm1880.c
549
clk_hw_unregister(data->hw_data.hws[clks[i].pll.id]);
drivers/clk/clk-cdce706.c
23
#define CDCE706_PLL_M_LOW(pll) (1 + 3 * (pll))
drivers/clk/clk-cdce706.c
24
#define CDCE706_PLL_N_LOW(pll) (2 + 3 * (pll))
drivers/clk/clk-cdce706.c
25
#define CDCE706_PLL_HI(pll) (3 + 3 * (pll))
drivers/clk/clk-cdce706.c
36
#define CDCE706_PLL_MUX_MASK(pll) (0x80 >> (pll))
drivers/clk/clk-cdce706.c
44
#define CDCE706_PLL_FVCO_MASK(pll) (0x80 >> (pll))
drivers/clk/clk-cdce706.c
530
for (i = 0; i < ARRAY_SIZE(cdce->pll); ++i) {
drivers/clk/clk-cdce706.c
542
cdce->pll[i].div = m | ((v & CDCE706_PLL_HI_M_MASK) << 8);
drivers/clk/clk-cdce706.c
543
cdce->pll[i].mul = n | ((v & CDCE706_PLL_HI_N_MASK) <<
drivers/clk/clk-cdce706.c
545
cdce->pll[i].mux = mux & CDCE706_PLL_MUX_MASK(i);
drivers/clk/clk-cdce706.c
548
cdce->pll[i].div, cdce->pll[i].mul, cdce->pll[i].mux);
drivers/clk/clk-cdce706.c
551
ret = cdce706_register_hw(cdce, cdce->pll,
drivers/clk/clk-cdce706.c
552
ARRAY_SIZE(cdce->pll),
drivers/clk/clk-cdce706.c
82
struct cdce706_hw_data pll[3];
drivers/clk/clk-cdce925.c
213
u8 pll[4]; /* Bits are spread out over 4 byte registers */
drivers/clk/clk-cdce925.c
241
pll[0] = n >> 4;
drivers/clk/clk-cdce925.c
242
pll[1] = ((n & 0x0F) << 4) | ((r >> 5) & 0x0F);
drivers/clk/clk-cdce925.c
243
pll[2] = ((r & 0x1F) << 3) | ((q >> 3) & 0x07);
drivers/clk/clk-cdce925.c
244
pll[3] = ((q & 0x07) << 5) | (p << 2) |
drivers/clk/clk-cdce925.c
247
for (i = 0; i < ARRAY_SIZE(pll); ++i)
drivers/clk/clk-cdce925.c
249
reg_ofs + CDCE925_PLL_MULDIV + i, pll[i]);
drivers/clk/clk-cdce925.c
385
struct clk *pll = clk_get_parent(hw->clk);
drivers/clk/clk-cdce925.c
386
struct clk *root = clk_get_parent(pll);
drivers/clk/clk-cdce925.c
406
long pll_rate = clk_round_rate(pll, target_rate);
drivers/clk/clk-cdce925.c
692
data->pll[i].chip = data;
drivers/clk/clk-cdce925.c
693
data->pll[i].hw.init = &init;
drivers/clk/clk-cdce925.c
694
data->pll[i].index = i;
drivers/clk/clk-cdce925.c
695
err = devm_clk_hw_register(&client->dev, &data->pll[i].hw);
drivers/clk/clk-cdce925.c
706
err = clk_set_rate(data->pll[i].hw.clk, value);
drivers/clk/clk-cdce925.c
72
struct clk_cdce925_pll pll[MAX_NUMBER_OF_PLLS];
drivers/clk/clk-eyeq.c
231
const struct eqc_pll *pll;
drivers/clk/clk-eyeq.c
239
pll = &data->plls[i];
drivers/clk/clk-eyeq.c
241
val = readq(base + pll->reg64);
drivers/clk/clk-eyeq.c
247
dev_warn(dev, "failed parsing state of %s\n", pll->name);
drivers/clk/clk-eyeq.c
248
cells->hws[pll->index] = ERR_PTR(ret);
drivers/clk/clk-eyeq.c
253
dev->of_node, pll->name, "ref", 0, mult, div, acc);
drivers/clk/clk-eyeq.c
254
cells->hws[pll->index] = hw;
drivers/clk/clk-eyeq.c
256
dev_warn(dev, "failed registering %s: %pe\n", pll->name, hw);
drivers/clk/clk-eyeq.c
798
const struct eqc_pll *pll = &early_data->early_plls[i];
drivers/clk/clk-eyeq.c
804
val = readq(base + pll->reg64);
drivers/clk/clk-eyeq.c
810
pr_err("failed parsing state of %s\n", pll->name);
drivers/clk/clk-eyeq.c
815
np, pll->name, "ref", 0, mult, div, acc);
drivers/clk/clk-eyeq.c
816
cells->hws[pll->index] = hw;
drivers/clk/clk-eyeq.c
818
pr_err("failed registering %s: %pe\n", pll->name, hw);
drivers/clk/clk-eyeq.c
861
const struct eqc_pll *pll = &early_data->early_plls[i];
drivers/clk/clk-eyeq.c
862
struct clk_hw *hw = cells->hws[pll->index];
drivers/clk/clk-k210.c
354
struct k210_pll *pll)
drivers/clk/clk-k210.c
356
pll->id = pllid;
drivers/clk/clk-k210.c
357
pll->reg = regs + k210_plls_cfg[pllid].reg;
drivers/clk/clk-k210.c
358
pll->lock = regs + K210_SYSCTL_PLL_LOCK;
drivers/clk/clk-k210.c
359
pll->lock_shift = k210_plls_cfg[pllid].lock_shift;
drivers/clk/clk-k210.c
360
pll->lock_width = k210_plls_cfg[pllid].lock_width;
drivers/clk/clk-k210.c
363
static void k210_pll_wait_for_lock(struct k210_pll *pll)
drivers/clk/clk-k210.c
365
u32 reg, mask = GENMASK(pll->lock_shift + pll->lock_width - 1,
drivers/clk/clk-k210.c
366
pll->lock_shift);
drivers/clk/clk-k210.c
369
reg = readl(pll->lock);
drivers/clk/clk-k210.c
373
reg |= BIT(pll->lock_shift + K210_PLL_CLEAR_SLIP);
drivers/clk/clk-k210.c
374
writel(reg, pll->lock);
drivers/clk/clk-k210.c
378
static bool k210_pll_hw_is_enabled(struct k210_pll *pll)
drivers/clk/clk-k210.c
380
u32 reg = readl(pll->reg);
drivers/clk/clk-k210.c
389
static void k210_pll_enable_hw(void __iomem *regs, struct k210_pll *pll)
drivers/clk/clk-k210.c
391
struct k210_pll_cfg *pll_cfg = &k210_plls_cfg[pll->id];
drivers/clk/clk-k210.c
394
if (k210_pll_hw_is_enabled(pll))
drivers/clk/clk-k210.c
401
if (pll->id == K210_PLL0)
drivers/clk/clk-k210.c
405
reg = readl(pll->reg);
drivers/clk/clk-k210.c
412
writel(reg, pll->reg);
drivers/clk/clk-k210.c
419
writel(reg, pll->reg);
drivers/clk/clk-k210.c
421
writel(reg, pll->reg);
drivers/clk/clk-k210.c
425
writel(reg, pll->reg);
drivers/clk/clk-k210.c
427
k210_pll_wait_for_lock(pll);
drivers/clk/clk-k210.c
431
writel(reg, pll->reg);
drivers/clk/clk-k210.c
433
if (pll->id == K210_PLL0)
drivers/clk/clk-k210.c
439
struct k210_pll *pll = to_k210_pll(hw);
drivers/clk/clk-k210.c
440
struct k210_sysclk *ksc = pll->ksc;
drivers/clk/clk-k210.c
445
k210_pll_enable_hw(ksc->regs, pll);
drivers/clk/clk-k210.c
454
struct k210_pll *pll = to_k210_pll(hw);
drivers/clk/clk-k210.c
455
struct k210_sysclk *ksc = pll->ksc;
drivers/clk/clk-k210.c
465
reg = readl(pll->reg);
drivers/clk/clk-k210.c
467
writel(reg, pll->reg);
drivers/clk/clk-k210.c
471
writel(reg, pll->reg);
drivers/clk/clk-k210.c
483
struct k210_pll *pll = to_k210_pll(hw);
drivers/clk/clk-k210.c
484
u32 reg = readl(pll->reg);
drivers/clk/clk-k210.c
509
struct k210_pll *pll = to_k210_pll(hw);
drivers/clk/clk-k210.c
510
struct k210_sysclk *ksc = pll->ksc;
drivers/clk/clk-k210.c
516
reg = readl(pll->reg);
drivers/clk/clk-k210.c
519
writel(reg, pll->reg);
drivers/clk/clk-k210.c
528
struct k210_pll *pll = to_k210_pll(hw);
drivers/clk/clk-k210.c
529
u32 reg = readl(pll->reg);
drivers/clk/clk-k210.c
549
struct k210_pll *pll = &ksc->plls[pllid];
drivers/clk/clk-k210.c
562
pll->hw.init = &init;
drivers/clk/clk-k210.c
563
pll->ksc = ksc;
drivers/clk/clk-k210.c
565
return of_clk_hw_register(np, &pll->hw);
drivers/clk/clk-k230.c
1879
struct k230_pll *pll = hw_to_k230_pll(hw);
drivers/clk/clk-k230.c
1883
return readl_poll_timeout(K230_PLLX_LOCK_ADDR(pll->reg, pll->id), reg,
drivers/clk/clk-k230.c
1888
static inline bool k230_pll_hw_is_enabled(struct k230_pll *pll)
drivers/clk/clk-k230.c
1890
return readl(K230_PLLX_GATE_ADDR(pll->reg, pll->id)) & K230_PLL_GATE_ENABLE;
drivers/clk/clk-k230.c
1893
static void k230_pll_enable_hw(struct k230_pll *pll)
drivers/clk/clk-k230.c
1897
if (k230_pll_hw_is_enabled(pll))
drivers/clk/clk-k230.c
1900
reg = readl(K230_PLLX_GATE_ADDR(pll->reg, pll->id));
drivers/clk/clk-k230.c
1902
writel(reg, K230_PLLX_GATE_ADDR(pll->reg, pll->id));
drivers/clk/clk-k230.c
1907
struct k230_pll *pll = hw_to_k230_pll(hw);
drivers/clk/clk-k230.c
1909
guard(spinlock)(pll->lock);
drivers/clk/clk-k230.c
1911
k230_pll_enable_hw(pll);
drivers/clk/clk-k230.c
1918
struct k230_pll *pll = hw_to_k230_pll(hw);
drivers/clk/clk-k230.c
1921
guard(spinlock)(pll->lock);
drivers/clk/clk-k230.c
1923
reg = readl(K230_PLLX_GATE_ADDR(pll->reg, pll->id));
drivers/clk/clk-k230.c
1926
writel(reg, K230_PLLX_GATE_ADDR(pll->reg, pll->id));
drivers/clk/clk-k230.c
1936
struct k230_pll *pll = hw_to_k230_pll(hw);
drivers/clk/clk-k230.c
1940
guard(spinlock)(pll->lock);
drivers/clk/clk-k230.c
1942
reg = readl(K230_PLLX_BYPASS_ADDR(pll->reg, pll->id));
drivers/clk/clk-k230.c
1946
reg = readl(K230_PLLX_LOCK_ADDR(pll->reg, pll->id));
drivers/clk/clk-k230.c
1950
reg = readl(K230_PLLX_DIV_ADDR(pll->reg, pll->id));
drivers/clk/clk-k230.c
1962
struct k230_pll *pll;
drivers/clk/clk-k230.c
1967
pll = k230_plls[i];
drivers/clk/clk-k230.c
1969
name = pll->hw.init->name;
drivers/clk/clk-k230.c
1970
pll->lock = lock;
drivers/clk/clk-k230.c
1971
pll->reg = reg;
drivers/clk/clk-k230.c
1973
ret = devm_clk_hw_register(&pdev->dev, &pll->hw);
drivers/clk/clk-k230.c
1977
ret = devm_clk_hw_register_clkdev(&pdev->dev, &pll->hw, name, NULL);
drivers/clk/clk-nomadik.c
170
struct clk_pll *pll = to_pll(hw);
drivers/clk/clk-nomadik.c
175
if (pll->id == 1) {
drivers/clk/clk-nomadik.c
180
} else if (pll->id == 2) {
drivers/clk/clk-nomadik.c
190
struct clk_pll *pll = to_pll(hw);
drivers/clk/clk-nomadik.c
195
if (pll->id == 1) {
drivers/clk/clk-nomadik.c
200
} else if (pll->id == 2) {
drivers/clk/clk-nomadik.c
209
struct clk_pll *pll = to_pll(hw);
drivers/clk/clk-nomadik.c
213
if (pll->id == 1) {
drivers/clk/clk-nomadik.c
216
} else if (pll->id == 2) {
drivers/clk/clk-nomadik.c
225
struct clk_pll *pll = to_pll(hw);
drivers/clk/clk-nomadik.c
230
if (pll->id == 1) {
drivers/clk/clk-nomadik.c
240
if (pll->id == 2) {
drivers/clk/clk-nomadik.c
265
struct clk_pll *pll;
drivers/clk/clk-nomadik.c
273
pll = kzalloc_obj(*pll);
drivers/clk/clk-nomadik.c
274
if (!pll)
drivers/clk/clk-nomadik.c
281
pll->hw.init = &init;
drivers/clk/clk-nomadik.c
282
pll->id = id;
drivers/clk/clk-nomadik.c
286
ret = clk_hw_register(dev, &pll->hw);
drivers/clk/clk-nomadik.c
288
kfree(pll);
drivers/clk/clk-nomadik.c
292
return &pll->hw;
drivers/clk/clk-npcm7xx.c
41
struct npcm7xx_clk_pll *pll = to_npcm7xx_clk_pll(hw);
drivers/clk/clk-npcm7xx.c
51
val = readl_relaxed(pll->pllcon);
drivers/clk/clk-npcm7xx.c
72
struct npcm7xx_clk_pll *pll;
drivers/clk/clk-npcm7xx.c
77
pll = kzalloc_obj(*pll);
drivers/clk/clk-npcm7xx.c
78
if (!pll)
drivers/clk/clk-npcm7xx.c
89
pll->pllcon = pllcon;
drivers/clk/clk-npcm7xx.c
90
pll->hw.init = &init;
drivers/clk/clk-npcm7xx.c
92
hw = &pll->hw;
drivers/clk/clk-npcm7xx.c
96
kfree(pll);
drivers/clk/clk-npcm8xx.c
227
struct npcm8xx_clk_pll *pll = to_npcm8xx_clk_pll(hw);
drivers/clk/clk-npcm8xx.c
237
val = readl_relaxed(pll->pllcon);
drivers/clk/clk-npcm8xx.c
259
struct npcm8xx_clk_pll *pll;
drivers/clk/clk-npcm8xx.c
263
pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL);
drivers/clk/clk-npcm8xx.c
264
if (!pll)
drivers/clk/clk-npcm8xx.c
273
pll->pllcon = pllcon;
drivers/clk/clk-npcm8xx.c
274
pll->hw.init = &init;
drivers/clk/clk-npcm8xx.c
276
ret = devm_clk_hw_register(dev, &pll->hw);
drivers/clk/clk-npcm8xx.c
280
return &pll->hw;
drivers/clk/clk-qoriq.c
1009
plat_rate = clk_get_rate(cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk);
drivers/clk/clk-qoriq.c
1214
struct clockgen_pll *pll = &cg->pll[idx];
drivers/clk/clk-qoriq.c
1271
for (i = 0; i < ARRAY_SIZE(pll->div); i++) {
drivers/clk/clk-qoriq.c
1282
snprintf(pll->div[i].name, sizeof(pll->div[i].name),
drivers/clk/clk-qoriq.c
1286
pll->div[i].name, input, 0, mult, i + 1);
drivers/clk/clk-qoriq.c
1289
__func__, pll->div[i].name, PTR_ERR(clk));
drivers/clk/clk-qoriq.c
1293
pll->div[i].clk = clk;
drivers/clk/clk-qoriq.c
1294
ret = clk_register_clkdev(clk, pll->div[i].name, NULL);
drivers/clk/clk-qoriq.c
1297
__func__, pll->div[i].name, ret);
drivers/clk/clk-qoriq.c
1306
for (i = 0; i < ARRAY_SIZE(cg->pll); i++)
drivers/clk/clk-qoriq.c
1312
struct clockgen_pll *pll;
drivers/clk/clk-qoriq.c
1319
pll = &clockgen.pll[idx];
drivers/clk/clk-qoriq.c
1322
BUILD_BUG_ON(ARRAY_SIZE(pll->div) < 4);
drivers/clk/clk-qoriq.c
1332
subclks[0] = pll->div[0].clk;
drivers/clk/clk-qoriq.c
1333
subclks[1] = pll->div[1].clk;
drivers/clk/clk-qoriq.c
1334
subclks[2] = pll->div[3].clk;
drivers/clk/clk-qoriq.c
1336
subclks[0] = pll->div[0].clk;
drivers/clk/clk-qoriq.c
1337
subclks[1] = pll->div[1].clk;
drivers/clk/clk-qoriq.c
1338
subclks[2] = pll->div[2].clk;
drivers/clk/clk-qoriq.c
1339
subclks[3] = pll->div[3].clk;
drivers/clk/clk-qoriq.c
1390
struct clockgen_pll *pll;
drivers/clk/clk-qoriq.c
1423
pll = &cg->pll[PLATFORM_PLL];
drivers/clk/clk-qoriq.c
1424
if (idx >= ARRAY_SIZE(pll->div))
drivers/clk/clk-qoriq.c
1426
clk = pll->div[idx].clk;
drivers/clk/clk-qoriq.c
477
cg->fman[0] = cg->pll[CGA_PLL2].div[PLL_DIV2].clk;
drivers/clk/clk-qoriq.c
479
cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
drivers/clk/clk-qoriq.c
489
cg->fman[0] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk;
drivers/clk/clk-qoriq.c
491
cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
drivers/clk/clk-qoriq.c
494
cg->fman[1] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk;
drivers/clk/clk-qoriq.c
496
cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
drivers/clk/clk-qoriq.c
509
cg->fman[0] = cg->pll[CGA_PLL2].div[div].clk;
drivers/clk/clk-qoriq.c
511
cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
drivers/clk/clk-qoriq.c
524
cg->fman[0] = cg->pll[CGA_PLL3].div[div].clk;
drivers/clk/clk-qoriq.c
526
cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
drivers/clk/clk-qoriq.c
529
cg->fman[1] = cg->pll[CGA_PLL3].div[div].clk;
drivers/clk/clk-qoriq.c
53
int pll; /* CGx_PLLn */
drivers/clk/clk-qoriq.c
531
cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
drivers/clk/clk-qoriq.c
541
cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk;
drivers/clk/clk-qoriq.c
899
int pll, div;
drivers/clk/clk-qoriq.c
904
pll = hwc->info->clksel[idx].pll;
drivers/clk/clk-qoriq.c
907
return &cg->pll[pll].div[div];
drivers/clk/clk-qoriq.c
93
struct clockgen_pll pll[6];
drivers/clk/clk-rp1.c
581
struct rp1_clk_desc *pll = container_of(hw, struct rp1_clk_desc, hw);
drivers/clk/clk-rp1.c
582
struct rp1_clockman *clockman = pll->clockman;
drivers/clk/clk-rp1.c
583
const struct rp1_pll_data *data = pll->data;
drivers/clk/clk-rp1.c
604
struct rp1_clk_desc *pll = container_of(hw, struct rp1_clk_desc, hw);
drivers/clk/clk-rp1.c
605
struct rp1_clockman *clockman = pll->clockman;
drivers/clk/clk-rp1.c
606
const struct rp1_pll_data *data = pll->data;
drivers/clk/clk-si5351.c
1583
drvdata->pll[0].num = 0;
drivers/clk/clk-si5351.c
1584
drvdata->pll[0].drvdata = drvdata;
drivers/clk/clk-si5351.c
1585
drvdata->pll[0].hw.init = &init;
drivers/clk/clk-si5351.c
1592
ret = devm_clk_hw_register(&client->dev, &drvdata->pll[0].hw);
drivers/clk/clk-si5351.c
1599
drvdata->pll[1].num = 1;
drivers/clk/clk-si5351.c
1600
drvdata->pll[1].drvdata = drvdata;
drivers/clk/clk-si5351.c
1601
drvdata->pll[1].hw.init = &init;
drivers/clk/clk-si5351.c
1616
ret = devm_clk_hw_register(&client->dev, &drvdata->pll[1].hw);
drivers/clk/clk-si5351.c
61
struct si5351_hw_data pll[2];
drivers/clk/clk-sp7021.c
552
struct sp_pll *pll;
drivers/clk/clk-sp7021.c
563
pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL);
drivers/clk/clk-sp7021.c
564
if (!pll)
drivers/clk/clk-sp7021.c
567
pll->hw.init = &initd;
drivers/clk/clk-sp7021.c
568
pll->reg = reg;
drivers/clk/clk-sp7021.c
569
pll->pd_bit = pd_bit;
drivers/clk/clk-sp7021.c
570
pll->bp_bit = bp_bit;
drivers/clk/clk-sp7021.c
571
pll->brate = brate;
drivers/clk/clk-sp7021.c
572
pll->div_shift = shift;
drivers/clk/clk-sp7021.c
573
pll->div_width = width;
drivers/clk/clk-sp7021.c
574
spin_lock_init(&pll->lock);
drivers/clk/clk-sp7021.c
576
hw = &pll->hw;
drivers/clk/clk-sparx5.c
147
struct s5_hw_clk *pll = to_s5_pll(hw);
drivers/clk/clk-sparx5.c
148
u32 val = readl(pll->reg);
drivers/clk/clk-sparx5.c
151
writel(val, pll->reg);
drivers/clk/clk-sparx5.c
158
struct s5_hw_clk *pll = to_s5_pll(hw);
drivers/clk/clk-sparx5.c
159
u32 val = readl(pll->reg);
drivers/clk/clk-sparx5.c
162
writel(val, pll->reg);
drivers/clk/clk-sparx5.c
169
struct s5_hw_clk *pll = to_s5_pll(hw);
drivers/clk/clk-sparx5.c
178
val = readl(pll->reg) & PLL_CLK_ENA;
drivers/clk/clk-sparx5.c
187
writel(val, pll->reg);
drivers/clk/clk-sparx5.c
195
struct s5_hw_clk *pll = to_s5_pll(hw);
drivers/clk/clk-sparx5.c
199
val = readl(pll->reg);
drivers/clk/clk-stm32f4.c
639
struct stm32f4_pll *pll = to_stm32f4_pll(gate);
drivers/clk/clk-stm32f4.c
649
bit_status = !(readl(gate->reg) & BIT(pll->bit_rdy_idx));
drivers/clk/clk-stm32f4.c
665
struct stm32f4_pll *pll = to_stm32f4_pll(gate);
drivers/clk/clk-stm32f4.c
669
val = readl(base + pll->offset);
drivers/clk/clk-stm32f4.c
679
struct stm32f4_pll *pll = to_stm32f4_pll(gate);
drivers/clk/clk-stm32f4.c
684
if (n < pll->n_start)
drivers/clk/clk-stm32f4.c
685
n = pll->n_start;
drivers/clk/clk-stm32f4.c
698
struct stm32f4_pll *pll = to_stm32f4_pll(gate);
drivers/clk/clk-stm32f4.c
699
struct stm32f4_pll_ssc *ssc = &pll->ssc_conf;
drivers/clk/clk-stm32f4.c
724
struct stm32f4_pll *pll = to_stm32f4_pll(gate);
drivers/clk/clk-stm32f4.c
737
val = readl(base + pll->offset) & ~STM32F4_RCC_PLLCFGR_N_MASK;
drivers/clk/clk-stm32f4.c
740
writel(val, base + pll->offset);
drivers/clk/clk-stm32f4.c
742
if (pll->ssc_enable)
drivers/clk/clk-stm32f4.c
854
struct stm32f4_pll *pll = to_stm32f4_pll(gate);
drivers/clk/clk-stm32f4.c
868
pll->ssc_enable = true;
drivers/clk/clk-stm32f4.c
869
memcpy(&pll->ssc_conf, conf, sizeof(pll->ssc_conf));
drivers/clk/clk-stm32f4.c
876
val = readl(base + pll->offset);
drivers/clk/clk-stm32f4.c
931
struct stm32f4_pll *pll;
drivers/clk/clk-stm32f4.c
940
pll = kzalloc_obj(*pll);
drivers/clk/clk-stm32f4.c
941
if (!pll)
drivers/clk/clk-stm32f4.c
952
pll->gate.lock = lock;
drivers/clk/clk-stm32f4.c
953
pll->gate.reg = base + STM32F4_RCC_CR;
drivers/clk/clk-stm32f4.c
954
pll->gate.bit_idx = vco->bit_idx;
drivers/clk/clk-stm32f4.c
955
pll->gate.hw.init = &init;
drivers/clk/clk-stm32f4.c
957
pll->offset = vco->offset;
drivers/clk/clk-stm32f4.c
958
pll->n_start = data->n_start;
drivers/clk/clk-stm32f4.c
959
pll->bit_rdy_idx = vco->bit_rdy_idx;
drivers/clk/clk-stm32f4.c
960
pll->status = (readl(base + STM32F4_RCC_CR) >> vco->bit_idx) & 0x1;
drivers/clk/clk-stm32f4.c
962
reg = base + pll->offset;
drivers/clk/clk-stm32f4.c
964
pll_hw = &pll->gate.hw;
drivers/clk/clk-stm32f4.c
967
kfree(pll);
drivers/clk/clk-stm32h7.c
788
struct stm32_pll_obj *pll;
drivers/clk/clk-stm32h7.c
795
pll = kzalloc_obj(*pll);
drivers/clk/clk-stm32h7.c
796
if (!pll)
drivers/clk/clk-stm32h7.c
804
pll->hw.init = &init;
drivers/clk/clk-stm32h7.c
806
hw = &pll->hw;
drivers/clk/clk-stm32h7.c
807
rgate = &pll->rgate;
drivers/clk/clk-stm32h7.c
814
div = &pll->div;
drivers/clk/clk-stm32h7.c
833
kfree(pll);
drivers/clk/clk-versaclock3.c
370
const struct vc3_pll_data *pll = vc3->data;
drivers/clk/clk-versaclock3.c
374
regmap_read(vc3->regmap, pll->int_div_msb_offs, &val);
drivers/clk/clk-versaclock3.c
376
regmap_read(vc3->regmap, pll->int_div_lsb_offs, &val);
drivers/clk/clk-versaclock3.c
379
if (pll->num == VC3_PLL2) {
drivers/clk/clk-versaclock3.c
397
const struct vc3_pll_data *pll = vc3->data;
drivers/clk/clk-versaclock3.c
400
if (req->rate < pll->vco.min)
drivers/clk/clk-versaclock3.c
401
req->rate = pll->vco.min;
drivers/clk/clk-versaclock3.c
402
if (req->rate > pll->vco.max)
drivers/clk/clk-versaclock3.c
403
req->rate = pll->vco.max;
drivers/clk/clk-versaclock3.c
407
if (pll->num == VC3_PLL2) {
drivers/clk/clk-versaclock3.c
431
const struct vc3_pll_data *pll = vc3->data;
drivers/clk/clk-versaclock3.c
434
regmap_read(vc3->regmap, pll->int_div_msb_offs, &val);
drivers/clk/clk-versaclock3.c
436
regmap_write(vc3->regmap, pll->int_div_msb_offs, val);
drivers/clk/clk-versaclock3.c
437
regmap_write(vc3->regmap, pll->int_div_lsb_offs, vc3->div_int & 0xff);
drivers/clk/clk-versaclock3.c
439
if (pll->num == VC3_PLL2) {
drivers/clk/clk-vt8500.c
550
struct clk_pll *pll = to_clk_pll(hw);
drivers/clk/clk-vt8500.c
558
switch (pll->type) {
drivers/clk/clk-vt8500.c
587
spin_lock_irqsave(pll->lock, flags);
drivers/clk/clk-vt8500.c
590
writel(pll_val, pll->reg);
drivers/clk/clk-vt8500.c
593
spin_unlock_irqrestore(pll->lock, flags);
drivers/clk/clk-vt8500.c
601
struct clk_pll *pll = to_clk_pll(hw);
drivers/clk/clk-vt8500.c
606
switch (pll->type) {
drivers/clk/clk-vt8500.c
650
struct clk_pll *pll = to_clk_pll(hw);
drivers/clk/clk-vt8500.c
651
u32 pll_val = readl(pll->reg);
drivers/clk/clk-vt8500.c
654
switch (pll->type) {
drivers/clk/clk-xgene.c
100
nfb = CLKF_RD(pll);
drivers/clk/clk-xgene.c
109
nout = SC_OUTDIV2(pll) ? 2 : 3;
drivers/clk/clk-xgene.c
110
fvco = parent_rate * SC_N_DIV_RD(pll);
drivers/clk/clk-xgene.c
77
u32 pll;
drivers/clk/clk-xgene.c
82
pll = xgene_clk_read(pllclk->reg + pllclk->pll_offset);
drivers/clk/clk-xgene.c
91
fvco = parent_rate * (N_DIV_RD(pll) + 4);
drivers/clk/clk-xgene.c
98
nref = CLKR_RD(pll) + 1;
drivers/clk/clk-xgene.c
99
nout = CLKOD_RD(pll) + 1;
drivers/clk/davinci/pll.c
116
struct davinci_pll_clk *pll = to_davinci_pll_clk(hw);
drivers/clk/davinci/pll.c
120
mult = readl(pll->base + PLLM) & pll->pllm_mask;
drivers/clk/davinci/pll.c
129
struct davinci_pll_clk *pll = to_davinci_pll_clk(hw);
drivers/clk/davinci/pll.c
149
if (mult < pll->pllm_min || mult > pll->pllm_max)
drivers/clk/davinci/pll.c
160
for (mult = pll->pllm_min; mult <= pll->pllm_max; mult++) {
drivers/clk/davinci/pll.c
182
struct davinci_pll_clk *pll = to_davinci_pll_clk(hw);
drivers/clk/davinci/pll.c
186
writel(mult - 1, pll->base + PLLM);
drivers/clk/davinci/pll.c
208
struct davinci_pll_clk *pll = to_davinci_pll_clk(hw);
drivers/clk/davinci/pll.c
212
mult = readl(pll->base + PLLM) & pll->pllm_mask;
drivers/clk/davinci/pll.c
309
struct davinci_pllen_clk *pll = to_davinci_pllen_clk(hw);
drivers/clk/davinci/pll.c
312
ctrl = readl(pll->base + PLLCTL);
drivers/clk/davinci/pll.c
317
writel(ctrl, pll->base + PLLCTL);
drivers/clk/davinci/pll.c
323
writel(ctrl, pll->base + PLLCTL);
drivers/clk/davinci/pll.c
329
writel(ctrl, pll->base + PLLCTL);
drivers/clk/davinci/pll.c
335
writel(ctrl, pll->base + PLLCTL);
drivers/clk/davinci/pll.c
643
struct davinci_pllen_clk *pll = to_davinci_pllen_clk(hw);
drivers/clk/davinci/pll.c
649
pllcmd = readl(pll->base + PLLCMD);
drivers/clk/davinci/pll.c
651
writel(pllcmd, pll->base + PLLCMD);
drivers/clk/davinci/pll.c
656
pllstat = readl(pll->base + PLLSTAT);
drivers/clk/davinci/pll.c
942
struct davinci_pll_clk *pll = to_davinci_pll_clk(hw);
drivers/clk/davinci/pll.c
951
regset->base = pll->base;
drivers/clk/imx/clk-cpu.c
16
struct clk *pll;
drivers/clk/imx/clk-cpu.c
38
req->rate = clk_round_rate(cpu->pll, req->rate);
drivers/clk/imx/clk-cpu.c
55
ret = clk_set_rate(cpu->pll, rate);
drivers/clk/imx/clk-cpu.c
57
clk_set_parent(cpu->mux, cpu->pll);
drivers/clk/imx/clk-cpu.c
61
clk_set_parent(cpu->mux, cpu->pll);
drivers/clk/imx/clk-cpu.c
76
struct clk *div, struct clk *mux, struct clk *pll,
drivers/clk/imx/clk-cpu.c
90
cpu->pll = pll;
drivers/clk/imx/clk-frac-pll.c
104
val = readl_relaxed(pll->base + PLL_CFG0);
drivers/clk/imx/clk-frac-pll.c
106
val = readl_relaxed(pll->base + PLL_CFG1);
drivers/clk/imx/clk-frac-pll.c
160
struct clk_frac_pll *pll = to_clk_frac_pll(hw);
drivers/clk/imx/clk-frac-pll.c
174
val = readl_relaxed(pll->base + PLL_CFG1);
drivers/clk/imx/clk-frac-pll.c
177
writel_relaxed(val, pll->base + PLL_CFG1);
drivers/clk/imx/clk-frac-pll.c
179
val = readl_relaxed(pll->base + PLL_CFG0);
drivers/clk/imx/clk-frac-pll.c
181
writel_relaxed(val, pll->base + PLL_CFG0);
drivers/clk/imx/clk-frac-pll.c
184
val = readl_relaxed(pll->base + PLL_CFG0);
drivers/clk/imx/clk-frac-pll.c
186
writel_relaxed(val, pll->base + PLL_CFG0);
drivers/clk/imx/clk-frac-pll.c
188
ret = clk_wait_ack(pll);
drivers/clk/imx/clk-frac-pll.c
191
val = readl_relaxed(pll->base + PLL_CFG0);
drivers/clk/imx/clk-frac-pll.c
193
writel_relaxed(val, pll->base + PLL_CFG0);
drivers/clk/imx/clk-frac-pll.c
212
struct clk_frac_pll *pll;
drivers/clk/imx/clk-frac-pll.c
216
pll = kzalloc_obj(*pll);
drivers/clk/imx/clk-frac-pll.c
217
if (!pll)
drivers/clk/imx/clk-frac-pll.c
226
pll->base = base;
drivers/clk/imx/clk-frac-pll.c
227
pll->hw.init = &init;
drivers/clk/imx/clk-frac-pll.c
229
hw = &pll->hw;
drivers/clk/imx/clk-frac-pll.c
233
kfree(pll);
drivers/clk/imx/clk-frac-pll.c
44
static int clk_wait_lock(struct clk_frac_pll *pll)
drivers/clk/imx/clk-frac-pll.c
48
return readl_poll_timeout(pll->base, val, val & PLL_LOCK_STATUS, 0,
drivers/clk/imx/clk-frac-pll.c
52
static int clk_wait_ack(struct clk_frac_pll *pll)
drivers/clk/imx/clk-frac-pll.c
57
if (readl_relaxed(pll->base) & (PLL_PD_MASK | PLL_BYPASS_MASK))
drivers/clk/imx/clk-frac-pll.c
61
return readl_poll_timeout(pll->base, val, val & PLL_NEWDIV_ACK, 0,
drivers/clk/imx/clk-frac-pll.c
67
struct clk_frac_pll *pll = to_clk_frac_pll(hw);
drivers/clk/imx/clk-frac-pll.c
70
val = readl_relaxed(pll->base + PLL_CFG0);
drivers/clk/imx/clk-frac-pll.c
72
writel_relaxed(val, pll->base + PLL_CFG0);
drivers/clk/imx/clk-frac-pll.c
74
return clk_wait_lock(pll);
drivers/clk/imx/clk-frac-pll.c
79
struct clk_frac_pll *pll = to_clk_frac_pll(hw);
drivers/clk/imx/clk-frac-pll.c
82
val = readl_relaxed(pll->base + PLL_CFG0);
drivers/clk/imx/clk-frac-pll.c
84
writel_relaxed(val, pll->base + PLL_CFG0);
drivers/clk/imx/clk-frac-pll.c
89
struct clk_frac_pll *pll = to_clk_frac_pll(hw);
drivers/clk/imx/clk-frac-pll.c
92
val = readl_relaxed(pll->base + PLL_CFG0);
drivers/clk/imx/clk-frac-pll.c
99
struct clk_frac_pll *pll = to_clk_frac_pll(hw);
drivers/clk/imx/clk-fracn-gppll.c
129
imx_get_pll_settings(struct clk_fracn_gppll *pll, unsigned long rate)
drivers/clk/imx/clk-fracn-gppll.c
131
const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table;
drivers/clk/imx/clk-fracn-gppll.c
134
for (i = 0; i < pll->rate_count; i++)
drivers/clk/imx/clk-fracn-gppll.c
144
struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
drivers/clk/imx/clk-fracn-gppll.c
145
const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table;
drivers/clk/imx/clk-fracn-gppll.c
149
for (i = 0; i < pll->rate_count; i++)
drivers/clk/imx/clk-fracn-gppll.c
157
req->rate = rate_table[pll->rate_count - 1].rate;
drivers/clk/imx/clk-fracn-gppll.c
164
struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
drivers/clk/imx/clk-fracn-gppll.c
165
const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table;
drivers/clk/imx/clk-fracn-gppll.c
172
pll_numerator = readl_relaxed(pll->base + PLL_NUMERATOR);
drivers/clk/imx/clk-fracn-gppll.c
175
pll_denominator = readl_relaxed(pll->base + PLL_DENOMINATOR);
drivers/clk/imx/clk-fracn-gppll.c
178
pll_div = readl_relaxed(pll->base + PLL_DIV);
drivers/clk/imx/clk-fracn-gppll.c
190
for (i = 0; i < pll->rate_count; i++) {
drivers/clk/imx/clk-fracn-gppll.c
214
if (pll->flags & CLK_FRACN_GPPLL_INTEGER) {
drivers/clk/imx/clk-fracn-gppll.c
227
static int clk_fracn_gppll_wait_lock(struct clk_fracn_gppll *pll)
drivers/clk/imx/clk-fracn-gppll.c
231
return readl_poll_timeout(pll->base + PLL_STATUS, val,
drivers/clk/imx/clk-fracn-gppll.c
238
struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
drivers/clk/imx/clk-fracn-gppll.c
243
rate = imx_get_pll_settings(pll, drate);
drivers/clk/imx/clk-fracn-gppll.c
246
tmp = readl_relaxed(pll->base + PLL_CTRL);
drivers/clk/imx/clk-fracn-gppll.c
248
writel_relaxed(tmp, pll->base + PLL_CTRL);
drivers/clk/imx/clk-fracn-gppll.c
251
tmp = readl_relaxed(pll->base + PLL_CTRL);
drivers/clk/imx/clk-fracn-gppll.c
253
writel_relaxed(tmp, pll->base + PLL_CTRL);
drivers/clk/imx/clk-fracn-gppll.c
257
writel_relaxed(tmp, pll->base + PLL_CTRL);
drivers/clk/imx/clk-fracn-gppll.c
261
writel_relaxed(tmp, pll->base + PLL_CTRL);
drivers/clk/imx/clk-fracn-gppll.c
265
writel_relaxed(pll_div, pll->base + PLL_DIV);
drivers/clk/imx/clk-fracn-gppll.c
266
readl(pll->base + PLL_DIV);
drivers/clk/imx/clk-fracn-gppll.c
267
if (pll->flags & CLK_FRACN_GPPLL_FRACN) {
drivers/clk/imx/clk-fracn-gppll.c
268
writel_relaxed(rate->mfd, pll->base + PLL_DENOMINATOR);
drivers/clk/imx/clk-fracn-gppll.c
269
writel_relaxed(FIELD_PREP(PLL_MFN_MASK, rate->mfn), pll->base + PLL_NUMERATOR);
drivers/clk/imx/clk-fracn-gppll.c
270
readl(pll->base + PLL_NUMERATOR);
drivers/clk/imx/clk-fracn-gppll.c
278
writel_relaxed(tmp, pll->base + PLL_CTRL);
drivers/clk/imx/clk-fracn-gppll.c
279
readl(pll->base + PLL_CTRL);
drivers/clk/imx/clk-fracn-gppll.c
282
ret = clk_fracn_gppll_wait_lock(pll);
drivers/clk/imx/clk-fracn-gppll.c
288
writel_relaxed(tmp, pll->base + PLL_CTRL);
drivers/clk/imx/clk-fracn-gppll.c
290
ana_mfn = readl_relaxed(pll->base + PLL_STATUS);
drivers/clk/imx/clk-fracn-gppll.c
300
struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
drivers/clk/imx/clk-fracn-gppll.c
304
val = readl_relaxed(pll->base + PLL_CTRL);
drivers/clk/imx/clk-fracn-gppll.c
308
if (pll->flags & CLK_FRACN_GPPLL_FRACN)
drivers/clk/imx/clk-fracn-gppll.c
309
writel_relaxed(readl_relaxed(pll->base + PLL_NUMERATOR),
drivers/clk/imx/clk-fracn-gppll.c
310
pll->base + PLL_NUMERATOR);
drivers/clk/imx/clk-fracn-gppll.c
313
writel_relaxed(val, pll->base + PLL_CTRL);
drivers/clk/imx/clk-fracn-gppll.c
316
writel_relaxed(val, pll->base + PLL_CTRL);
drivers/clk/imx/clk-fracn-gppll.c
317
readl(pll->base + PLL_CTRL);
drivers/clk/imx/clk-fracn-gppll.c
319
ret = clk_fracn_gppll_wait_lock(pll);
drivers/clk/imx/clk-fracn-gppll.c
324
writel_relaxed(val, pll->base + PLL_CTRL);
drivers/clk/imx/clk-fracn-gppll.c
327
writel_relaxed(val, pll->base + PLL_CTRL);
drivers/clk/imx/clk-fracn-gppll.c
334
struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
drivers/clk/imx/clk-fracn-gppll.c
337
val = readl_relaxed(pll->base + PLL_CTRL);
drivers/clk/imx/clk-fracn-gppll.c
344
struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
drivers/clk/imx/clk-fracn-gppll.c
347
val = readl_relaxed(pll->base + PLL_CTRL);
drivers/clk/imx/clk-fracn-gppll.c
349
writel_relaxed(val, pll->base + PLL_CTRL);
drivers/clk/imx/clk-fracn-gppll.c
366
struct clk_fracn_gppll *pll;
drivers/clk/imx/clk-fracn-gppll.c
371
pll = kzalloc_obj(*pll);
drivers/clk/imx/clk-fracn-gppll.c
372
if (!pll)
drivers/clk/imx/clk-fracn-gppll.c
381
pll->base = base;
drivers/clk/imx/clk-fracn-gppll.c
382
pll->hw.init = &init;
drivers/clk/imx/clk-fracn-gppll.c
383
pll->rate_table = pll_clk->rate_table;
drivers/clk/imx/clk-fracn-gppll.c
384
pll->rate_count = pll_clk->rate_count;
drivers/clk/imx/clk-fracn-gppll.c
385
pll->flags = pll_flags;
drivers/clk/imx/clk-fracn-gppll.c
387
hw = &pll->hw;
drivers/clk/imx/clk-fracn-gppll.c
392
kfree(pll);
drivers/clk/imx/clk-pll14xx.c
106
static long pll14xx_calc_rate(struct clk_pll14xx *pll, int mdiv, int pdiv,
drivers/clk/imx/clk-pll14xx.c
131
static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rate,
drivers/clk/imx/clk-pll14xx.c
152
tt = imx_get_pll_settings(pll, rate);
drivers/clk/imx/clk-pll14xx.c
155
clk_hw_get_name(&pll->hw), prate, rate);
drivers/clk/imx/clk-pll14xx.c
164
pll_div_ctl0 = readl_relaxed(pll->base + DIV_CTL0);
drivers/clk/imx/clk-pll14xx.c
168
pll_div_ctl1 = readl_relaxed(pll->base + DIV_CTL1);
drivers/clk/imx/clk-pll14xx.c
171
rate_min = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, KDIV_MIN, prate);
drivers/clk/imx/clk-pll14xx.c
172
rate_max = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, KDIV_MAX, prate);
drivers/clk/imx/clk-pll14xx.c
177
clk_hw_get_name(&pll->hw), prate, rate,
drivers/clk/imx/clk-pll14xx.c
179
fout = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, kdiv, prate);
drivers/clk/imx/clk-pll14xx.c
196
fout = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, kdiv, prate);
drivers/clk/imx/clk-pll14xx.c
215
clk_hw_get_name(&pll->hw), prate, rate, t->rate, t->pdiv, t->sdiv,
drivers/clk/imx/clk-pll14xx.c
222
struct clk_pll14xx *pll = to_clk_pll14xx(hw);
drivers/clk/imx/clk-pll14xx.c
223
const struct imx_pll14xx_rate_table *rate_table = pll->rate_table;
drivers/clk/imx/clk-pll14xx.c
227
for (i = 0; i < pll->rate_count; i++)
drivers/clk/imx/clk-pll14xx.c
235
req->rate = rate_table[pll->rate_count - 1].rate;
drivers/clk/imx/clk-pll14xx.c
243
struct clk_pll14xx *pll = to_clk_pll14xx(hw);
drivers/clk/imx/clk-pll14xx.c
246
imx_pll14xx_calc_settings(pll, req->rate, req->best_parent_rate, &t);
drivers/clk/imx/clk-pll14xx.c
256
struct clk_pll14xx *pll = to_clk_pll14xx(hw);
drivers/clk/imx/clk-pll14xx.c
259
pll_div_ctl0 = readl_relaxed(pll->base + DIV_CTL0);
drivers/clk/imx/clk-pll14xx.c
264
if (pll->type == PLL_1443X) {
drivers/clk/imx/clk-pll14xx.c
265
pll_div_ctl1 = readl_relaxed(pll->base + DIV_CTL1);
drivers/clk/imx/clk-pll14xx.c
271
return pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, kdiv, parent_rate);
drivers/clk/imx/clk-pll14xx.c
285
static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll)
drivers/clk/imx/clk-pll14xx.c
289
return readl_poll_timeout(pll->base + GNRL_CTL, val, val & LOCK_STATUS, 0,
drivers/clk/imx/clk-pll14xx.c
296
struct clk_pll14xx *pll = to_clk_pll14xx(hw);
drivers/clk/imx/clk-pll14xx.c
301
rate = imx_get_pll_settings(pll, drate);
drivers/clk/imx/clk-pll14xx.c
308
tmp = readl_relaxed(pll->base + DIV_CTL0);
drivers/clk/imx/clk-pll14xx.c
313
writel_relaxed(tmp, pll->base + DIV_CTL0);
drivers/clk/imx/clk-pll14xx.c
319
tmp = readl_relaxed(pll->base + GNRL_CTL);
drivers/clk/imx/clk-pll14xx.c
321
writel_relaxed(tmp, pll->base + GNRL_CTL);
drivers/clk/imx/clk-pll14xx.c
325
writel_relaxed(tmp, pll->base + GNRL_CTL);
drivers/clk/imx/clk-pll14xx.c
329
writel(tmp, pll->base + GNRL_CTL);
drivers/clk/imx/clk-pll14xx.c
333
writel_relaxed(div_val, pll->base + DIV_CTL0);
drivers/clk/imx/clk-pll14xx.c
345
writel_relaxed(tmp, pll->base + GNRL_CTL);
drivers/clk/imx/clk-pll14xx.c
348
ret = clk_pll14xx_wait_lock(pll);
drivers/clk/imx/clk-pll14xx.c
354
writel_relaxed(tmp, pll->base + GNRL_CTL);
drivers/clk/imx/clk-pll14xx.c
362
struct clk_pll14xx *pll = to_clk_pll14xx(hw);
drivers/clk/imx/clk-pll14xx.c
367
imx_pll14xx_calc_settings(pll, drate, prate, &rate);
drivers/clk/imx/clk-pll14xx.c
369
div_ctl0 = readl_relaxed(pll->base + DIV_CTL0);
drivers/clk/imx/clk-pll14xx.c
375
writel_relaxed(div_ctl0, pll->base + DIV_CTL0);
drivers/clk/imx/clk-pll14xx.c
378
pll->base + DIV_CTL1);
drivers/clk/imx/clk-pll14xx.c
384
gnrl_ctl = readl_relaxed(pll->base + GNRL_CTL);
drivers/clk/imx/clk-pll14xx.c
386
writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL);
drivers/clk/imx/clk-pll14xx.c
390
writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL);
drivers/clk/imx/clk-pll14xx.c
395
writel_relaxed(div_ctl0, pll->base + DIV_CTL0);
drivers/clk/imx/clk-pll14xx.c
397
writel_relaxed(FIELD_PREP(KDIV_MASK, rate.kdiv), pll->base + DIV_CTL1);
drivers/clk/imx/clk-pll14xx.c
409
writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL);
drivers/clk/imx/clk-pll14xx.c
412
ret = clk_pll14xx_wait_lock(pll);
drivers/clk/imx/clk-pll14xx.c
418
writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL);
drivers/clk/imx/clk-pll14xx.c
425
struct clk_pll14xx *pll = to_clk_pll14xx(hw);
drivers/clk/imx/clk-pll14xx.c
433
val = readl_relaxed(pll->base + GNRL_CTL);
drivers/clk/imx/clk-pll14xx.c
437
writel_relaxed(val, pll->base + GNRL_CTL);
drivers/clk/imx/clk-pll14xx.c
439
writel_relaxed(val, pll->base + GNRL_CTL);
drivers/clk/imx/clk-pll14xx.c
441
ret = clk_pll14xx_wait_lock(pll);
drivers/clk/imx/clk-pll14xx.c
446
writel_relaxed(val, pll->base + GNRL_CTL);
drivers/clk/imx/clk-pll14xx.c
453
struct clk_pll14xx *pll = to_clk_pll14xx(hw);
drivers/clk/imx/clk-pll14xx.c
456
val = readl_relaxed(pll->base + GNRL_CTL);
drivers/clk/imx/clk-pll14xx.c
463
struct clk_pll14xx *pll = to_clk_pll14xx(hw);
drivers/clk/imx/clk-pll14xx.c
470
val = readl_relaxed(pll->base + GNRL_CTL);
drivers/clk/imx/clk-pll14xx.c
472
writel_relaxed(val, pll->base + GNRL_CTL);
drivers/clk/imx/clk-pll14xx.c
501
struct clk_pll14xx *pll;
drivers/clk/imx/clk-pll14xx.c
507
pll = kzalloc_obj(*pll);
drivers/clk/imx/clk-pll14xx.c
508
if (!pll)
drivers/clk/imx/clk-pll14xx.c
528
kfree(pll);
drivers/clk/imx/clk-pll14xx.c
532
pll->base = base;
drivers/clk/imx/clk-pll14xx.c
533
pll->hw.init = &init;
drivers/clk/imx/clk-pll14xx.c
534
pll->type = pll_clk->type;
drivers/clk/imx/clk-pll14xx.c
535
pll->rate_table = pll_clk->rate_table;
drivers/clk/imx/clk-pll14xx.c
536
pll->rate_count = pll_clk->rate_count;
drivers/clk/imx/clk-pll14xx.c
538
val = readl_relaxed(pll->base + GNRL_CTL);
drivers/clk/imx/clk-pll14xx.c
540
writel_relaxed(val, pll->base + GNRL_CTL);
drivers/clk/imx/clk-pll14xx.c
542
hw = &pll->hw;
drivers/clk/imx/clk-pll14xx.c
547
kfree(pll);
drivers/clk/imx/clk-pll14xx.c
94
struct clk_pll14xx *pll, unsigned long rate)
drivers/clk/imx/clk-pll14xx.c
96
const struct imx_pll14xx_rate_table *rate_table = pll->rate_table;
drivers/clk/imx/clk-pll14xx.c
99
for (i = 0; i < pll->rate_count; i++)
drivers/clk/imx/clk-pllv1.c
102
if (mfn_is_negative(pll, mfn))
drivers/clk/imx/clk-pllv1.c
117
struct clk_pllv1 *pll;
drivers/clk/imx/clk-pllv1.c
122
pll = kmalloc_obj(*pll);
drivers/clk/imx/clk-pllv1.c
123
if (!pll)
drivers/clk/imx/clk-pllv1.c
126
pll->base = base;
drivers/clk/imx/clk-pllv1.c
127
pll->type = type;
drivers/clk/imx/clk-pllv1.c
135
pll->hw.init = &init;
drivers/clk/imx/clk-pllv1.c
136
hw = &pll->hw;
drivers/clk/imx/clk-pllv1.c
140
kfree(pll);
drivers/clk/imx/clk-pllv1.c
32
static inline bool is_imx1_pllv1(struct clk_pllv1 *pll)
drivers/clk/imx/clk-pllv1.c
34
return pll->type == IMX_PLLV1_IMX1;
drivers/clk/imx/clk-pllv1.c
37
static inline bool is_imx21_pllv1(struct clk_pllv1 *pll)
drivers/clk/imx/clk-pllv1.c
39
return pll->type == IMX_PLLV1_IMX21;
drivers/clk/imx/clk-pllv1.c
42
static inline bool is_imx27_pllv1(struct clk_pllv1 *pll)
drivers/clk/imx/clk-pllv1.c
44
return pll->type == IMX_PLLV1_IMX27;
drivers/clk/imx/clk-pllv1.c
47
static inline bool mfn_is_negative(struct clk_pllv1 *pll, unsigned int mfn)
drivers/clk/imx/clk-pllv1.c
49
return !is_imx1_pllv1(pll) && !is_imx21_pllv1(pll) && (mfn & MFN_SIGN);
drivers/clk/imx/clk-pllv1.c
55
struct clk_pllv1 *pll = to_clk_pllv1(hw);
drivers/clk/imx/clk-pllv1.c
62
reg = readl(pll->base);
drivers/clk/imx/clk-pllv1.c
88
if (mfn_is_negative(pll, mfn)) {
drivers/clk/imx/clk-pllv1.c
89
if (is_imx27_pllv1(pll))
drivers/clk/imx/clk-pllv2.c
114
struct clk_pllv2 *pll = to_clk_pllv2(hw);
drivers/clk/imx/clk-pllv2.c
116
pllbase = pll->base;
drivers/clk/imx/clk-pllv2.c
158
struct clk_pllv2 *pll = to_clk_pllv2(hw);
drivers/clk/imx/clk-pllv2.c
163
pllbase = pll->base;
drivers/clk/imx/clk-pllv2.c
204
struct clk_pllv2 *pll = to_clk_pllv2(hw);
drivers/clk/imx/clk-pllv2.c
209
pllbase = pll->base;
drivers/clk/imx/clk-pllv2.c
232
struct clk_pllv2 *pll = to_clk_pllv2(hw);
drivers/clk/imx/clk-pllv2.c
236
pllbase = pll->base;
drivers/clk/imx/clk-pllv2.c
252
struct clk_pllv2 *pll;
drivers/clk/imx/clk-pllv2.c
257
pll = kzalloc_obj(*pll);
drivers/clk/imx/clk-pllv2.c
258
if (!pll)
drivers/clk/imx/clk-pllv2.c
261
pll->base = base;
drivers/clk/imx/clk-pllv2.c
269
pll->hw.init = &init;
drivers/clk/imx/clk-pllv2.c
270
hw = &pll->hw;
drivers/clk/imx/clk-pllv2.c
274
kfree(pll);
drivers/clk/imx/clk-pllv3.c
103
struct clk_pllv3 *pll = to_clk_pllv3(hw);
drivers/clk/imx/clk-pllv3.c
105
if (readl_relaxed(pll->base) & BM_PLL_LOCK)
drivers/clk/imx/clk-pllv3.c
114
struct clk_pllv3 *pll = to_clk_pllv3(hw);
drivers/clk/imx/clk-pllv3.c
115
u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask;
drivers/clk/imx/clk-pllv3.c
133
struct clk_pllv3 *pll = to_clk_pllv3(hw);
drivers/clk/imx/clk-pllv3.c
143
val = readl_relaxed(pll->base);
drivers/clk/imx/clk-pllv3.c
144
val &= ~(pll->div_mask << pll->div_shift);
drivers/clk/imx/clk-pllv3.c
145
val |= (div << pll->div_shift);
drivers/clk/imx/clk-pllv3.c
146
writel_relaxed(val, pll->base);
drivers/clk/imx/clk-pllv3.c
148
return clk_pllv3_wait_lock(pll);
drivers/clk/imx/clk-pllv3.c
163
struct clk_pllv3 *pll = to_clk_pllv3(hw);
drivers/clk/imx/clk-pllv3.c
164
u32 div = readl_relaxed(pll->base) & pll->div_mask;
drivers/clk/imx/clk-pllv3.c
191
struct clk_pllv3 *pll = to_clk_pllv3(hw);
drivers/clk/imx/clk-pllv3.c
200
val = readl_relaxed(pll->base);
drivers/clk/imx/clk-pllv3.c
201
val &= ~pll->div_mask;
drivers/clk/imx/clk-pllv3.c
203
writel_relaxed(val, pll->base);
drivers/clk/imx/clk-pllv3.c
205
return clk_pllv3_wait_lock(pll);
drivers/clk/imx/clk-pllv3.c
220
struct clk_pllv3 *pll = to_clk_pllv3(hw);
drivers/clk/imx/clk-pllv3.c
221
u32 mfn = readl_relaxed(pll->base + pll->num_offset);
drivers/clk/imx/clk-pllv3.c
222
u32 mfd = readl_relaxed(pll->base + pll->denom_offset);
drivers/clk/imx/clk-pllv3.c
223
u32 div = readl_relaxed(pll->base) & pll->div_mask;
drivers/clk/imx/clk-pllv3.c
269
struct clk_pllv3 *pll = to_clk_pllv3(hw);
drivers/clk/imx/clk-pllv3.c
289
val = readl_relaxed(pll->base);
drivers/clk/imx/clk-pllv3.c
290
val &= ~pll->div_mask;
drivers/clk/imx/clk-pllv3.c
292
writel_relaxed(val, pll->base);
drivers/clk/imx/clk-pllv3.c
293
writel_relaxed(mfn, pll->base + pll->num_offset);
drivers/clk/imx/clk-pllv3.c
294
writel_relaxed(mfd, pll->base + pll->denom_offset);
drivers/clk/imx/clk-pllv3.c
296
return clk_pllv3_wait_lock(pll);
drivers/clk/imx/clk-pllv3.c
353
struct clk_pllv3 *pll = to_clk_pllv3(hw);
drivers/clk/imx/clk-pllv3.c
356
mf.mfn = readl_relaxed(pll->base + pll->num_offset);
drivers/clk/imx/clk-pllv3.c
357
mf.mfd = readl_relaxed(pll->base + pll->denom_offset);
drivers/clk/imx/clk-pllv3.c
358
mf.mfi = (readl_relaxed(pll->base) & pll->div_mask) ? 22 : 20;
drivers/clk/imx/clk-pllv3.c
377
struct clk_pllv3 *pll = to_clk_pllv3(hw);
drivers/clk/imx/clk-pllv3.c
382
val = readl_relaxed(pll->base);
drivers/clk/imx/clk-pllv3.c
384
val &= ~pll->div_mask; /* clear bit for mfi=20 */
drivers/clk/imx/clk-pllv3.c
386
val |= pll->div_mask; /* set bit for mfi=22 */
drivers/clk/imx/clk-pllv3.c
387
writel_relaxed(val, pll->base);
drivers/clk/imx/clk-pllv3.c
389
writel_relaxed(mf.mfn, pll->base + pll->num_offset);
drivers/clk/imx/clk-pllv3.c
390
writel_relaxed(mf.mfd, pll->base + pll->denom_offset);
drivers/clk/imx/clk-pllv3.c
392
return clk_pllv3_wait_lock(pll);
drivers/clk/imx/clk-pllv3.c
407
struct clk_pllv3 *pll = to_clk_pllv3(hw);
drivers/clk/imx/clk-pllv3.c
409
return pll->ref_clock;
drivers/clk/imx/clk-pllv3.c
423
struct clk_pllv3 *pll;
drivers/clk/imx/clk-pllv3.c
429
pll = kzalloc_obj(*pll);
drivers/clk/imx/clk-pllv3.c
430
if (!pll)
drivers/clk/imx/clk-pllv3.c
433
pll->power_bit = BM_PLL_POWER;
drivers/clk/imx/clk-pllv3.c
434
pll->num_offset = PLL_NUM_OFFSET;
drivers/clk/imx/clk-pllv3.c
435
pll->denom_offset = PLL_DENOM_OFFSET;
drivers/clk/imx/clk-pllv3.c
443
pll->num_offset = PLL_VF610_NUM_OFFSET;
drivers/clk/imx/clk-pllv3.c
444
pll->denom_offset = PLL_VF610_DENOM_OFFSET;
drivers/clk/imx/clk-pllv3.c
447
pll->div_shift = 1;
drivers/clk/imx/clk-pllv3.c
451
pll->powerup_set = true;
drivers/clk/imx/clk-pllv3.c
454
pll->num_offset = PLL_IMX7_NUM_OFFSET;
drivers/clk/imx/clk-pllv3.c
455
pll->denom_offset = PLL_IMX7_DENOM_OFFSET;
drivers/clk/imx/clk-pllv3.c
461
pll->power_bit = IMX7_ENET_PLL_POWER;
drivers/clk/imx/clk-pllv3.c
462
pll->ref_clock = 1000000000;
drivers/clk/imx/clk-pllv3.c
466
pll->ref_clock = 500000000;
drivers/clk/imx/clk-pllv3.c
470
pll->power_bit = IMX7_DDR_PLL_POWER;
drivers/clk/imx/clk-pllv3.c
471
pll->num_offset = PLL_IMX7_NUM_OFFSET;
drivers/clk/imx/clk-pllv3.c
472
pll->denom_offset = PLL_IMX7_DENOM_OFFSET;
drivers/clk/imx/clk-pllv3.c
478
pll->base = base;
drivers/clk/imx/clk-pllv3.c
479
pll->div_mask = div_mask;
drivers/clk/imx/clk-pllv3.c
487
pll->hw.init = &init;
drivers/clk/imx/clk-pllv3.c
488
hw = &pll->hw;
drivers/clk/imx/clk-pllv3.c
492
kfree(pll);
drivers/clk/imx/clk-pllv3.c
61
static int clk_pllv3_wait_lock(struct clk_pllv3 *pll)
drivers/clk/imx/clk-pllv3.c
63
u32 val = readl_relaxed(pll->base) & pll->power_bit;
drivers/clk/imx/clk-pllv3.c
66
if ((pll->powerup_set && !val) || (!pll->powerup_set && val))
drivers/clk/imx/clk-pllv3.c
69
return readl_relaxed_poll_timeout(pll->base, val, val & BM_PLL_LOCK,
drivers/clk/imx/clk-pllv3.c
75
struct clk_pllv3 *pll = to_clk_pllv3(hw);
drivers/clk/imx/clk-pllv3.c
78
val = readl_relaxed(pll->base);
drivers/clk/imx/clk-pllv3.c
79
if (pll->powerup_set)
drivers/clk/imx/clk-pllv3.c
80
val |= pll->power_bit;
drivers/clk/imx/clk-pllv3.c
82
val &= ~pll->power_bit;
drivers/clk/imx/clk-pllv3.c
83
writel_relaxed(val, pll->base);
drivers/clk/imx/clk-pllv3.c
85
return clk_pllv3_wait_lock(pll);
drivers/clk/imx/clk-pllv3.c
90
struct clk_pllv3 *pll = to_clk_pllv3(hw);
drivers/clk/imx/clk-pllv3.c
93
val = readl_relaxed(pll->base);
drivers/clk/imx/clk-pllv3.c
94
if (pll->powerup_set)
drivers/clk/imx/clk-pllv3.c
95
val &= ~pll->power_bit;
drivers/clk/imx/clk-pllv3.c
97
val |= pll->power_bit;
drivers/clk/imx/clk-pllv3.c
98
writel_relaxed(val, pll->base);
drivers/clk/imx/clk-pllv4.c
101
struct clk_pllv4 *pll = to_clk_pllv4(hw);
drivers/clk/imx/clk-pllv4.c
109
if (pll->use_mult_range) {
drivers/clk/imx/clk-pllv4.c
165
static bool clk_pllv4_is_valid_mult(struct clk_pllv4 *pll, unsigned int mult)
drivers/clk/imx/clk-pllv4.c
170
if (pll->use_mult_range) {
drivers/clk/imx/clk-pllv4.c
187
struct clk_pllv4 *pll = to_clk_pllv4(hw);
drivers/clk/imx/clk-pllv4.c
193
if (!clk_pllv4_is_valid_mult(pll, mult))
drivers/clk/imx/clk-pllv4.c
204
val = readl_relaxed(pll->base + pll->cfg_offset);
drivers/clk/imx/clk-pllv4.c
207
writel_relaxed(val, pll->base + pll->cfg_offset);
drivers/clk/imx/clk-pllv4.c
209
writel_relaxed(mfn, pll->base + pll->num_offset);
drivers/clk/imx/clk-pllv4.c
210
writel_relaxed(mfd, pll->base + pll->denom_offset);
drivers/clk/imx/clk-pllv4.c
218
struct clk_pllv4 *pll = to_clk_pllv4(hw);
drivers/clk/imx/clk-pllv4.c
220
val = readl_relaxed(pll->base);
drivers/clk/imx/clk-pllv4.c
222
writel_relaxed(val, pll->base);
drivers/clk/imx/clk-pllv4.c
224
return clk_pllv4_wait_lock(pll);
drivers/clk/imx/clk-pllv4.c
230
struct clk_pllv4 *pll = to_clk_pllv4(hw);
drivers/clk/imx/clk-pllv4.c
232
val = readl_relaxed(pll->base);
drivers/clk/imx/clk-pllv4.c
234
writel_relaxed(val, pll->base);
drivers/clk/imx/clk-pllv4.c
249
struct clk_pllv4 *pll;
drivers/clk/imx/clk-pllv4.c
254
pll = kzalloc_obj(*pll);
drivers/clk/imx/clk-pllv4.c
255
if (!pll)
drivers/clk/imx/clk-pllv4.c
258
pll->base = base;
drivers/clk/imx/clk-pllv4.c
262
pll->cfg_offset = IMX8ULP_PLL_CFG_OFFSET;
drivers/clk/imx/clk-pllv4.c
263
pll->num_offset = IMX8ULP_PLL_NUM_OFFSET;
drivers/clk/imx/clk-pllv4.c
264
pll->denom_offset = IMX8ULP_PLL_DENOM_OFFSET;
drivers/clk/imx/clk-pllv4.c
266
pll->use_mult_range = true;
drivers/clk/imx/clk-pllv4.c
268
pll->cfg_offset = PLL_CFG_OFFSET;
drivers/clk/imx/clk-pllv4.c
269
pll->num_offset = PLL_NUM_OFFSET;
drivers/clk/imx/clk-pllv4.c
270
pll->denom_offset = PLL_DENOM_OFFSET;
drivers/clk/imx/clk-pllv4.c
279
pll->hw.init = &init;
drivers/clk/imx/clk-pllv4.c
281
hw = &pll->hw;
drivers/clk/imx/clk-pllv4.c
284
kfree(pll);
drivers/clk/imx/clk-pllv4.c
60
static inline int clk_pllv4_wait_lock(struct clk_pllv4 *pll)
drivers/clk/imx/clk-pllv4.c
64
return readl_poll_timeout(pll->base + PLL_CSR_OFFSET,
drivers/clk/imx/clk-pllv4.c
70
struct clk_pllv4 *pll = to_clk_pllv4(hw);
drivers/clk/imx/clk-pllv4.c
72
if (readl_relaxed(pll->base) & PLL_EN)
drivers/clk/imx/clk-pllv4.c
81
struct clk_pllv4 *pll = to_clk_pllv4(hw);
drivers/clk/imx/clk-pllv4.c
85
mult = readl_relaxed(pll->base + pll->cfg_offset);
drivers/clk/imx/clk-pllv4.c
89
mfn = readl_relaxed(pll->base + pll->num_offset);
drivers/clk/imx/clk-pllv4.c
90
mfd = readl_relaxed(pll->base + pll->denom_offset);
drivers/clk/imx/clk-sscg-pll.c
102
val = readl_relaxed(pll->base + PLL_CFG0);
drivers/clk/imx/clk-sscg-pll.c
106
return readl_poll_timeout(pll->base, val, val & PLL_LOCK_MASK,
drivers/clk/imx/clk-sscg-pll.c
298
struct clk_sscg_pll *pll = to_clk_sscg_pll(hw);
drivers/clk/imx/clk-sscg-pll.c
300
u32 val = readl_relaxed(pll->base + PLL_CFG0);
drivers/clk/imx/clk-sscg-pll.c
307
struct clk_sscg_pll *pll = to_clk_sscg_pll(hw);
drivers/clk/imx/clk-sscg-pll.c
310
val = readl_relaxed(pll->base + PLL_CFG0);
drivers/clk/imx/clk-sscg-pll.c
312
writel_relaxed(val, pll->base + PLL_CFG0);
drivers/clk/imx/clk-sscg-pll.c
314
return clk_sscg_pll_wait_lock(pll);
drivers/clk/imx/clk-sscg-pll.c
319
struct clk_sscg_pll *pll = to_clk_sscg_pll(hw);
drivers/clk/imx/clk-sscg-pll.c
322
val = readl_relaxed(pll->base + PLL_CFG0);
drivers/clk/imx/clk-sscg-pll.c
324
writel_relaxed(val, pll->base + PLL_CFG0);
drivers/clk/imx/clk-sscg-pll.c
330
struct clk_sscg_pll *pll = to_clk_sscg_pll(hw);
drivers/clk/imx/clk-sscg-pll.c
334
val = readl_relaxed(pll->base + PLL_CFG2);
drivers/clk/imx/clk-sscg-pll.c
343
val = readl(pll->base + PLL_CFG0);
drivers/clk/imx/clk-sscg-pll.c
361
struct clk_sscg_pll *pll = to_clk_sscg_pll(hw);
drivers/clk/imx/clk-sscg-pll.c
362
struct clk_sscg_pll_setup *setup = &pll->setup;
drivers/clk/imx/clk-sscg-pll.c
366
val = readl(pll->base + PLL_CFG0);
drivers/clk/imx/clk-sscg-pll.c
369
writel(val, pll->base + PLL_CFG0);
drivers/clk/imx/clk-sscg-pll.c
371
val = readl_relaxed(pll->base + PLL_CFG2);
drivers/clk/imx/clk-sscg-pll.c
379
writel_relaxed(val, pll->base + PLL_CFG2);
drivers/clk/imx/clk-sscg-pll.c
381
return clk_sscg_pll_wait_lock(pll);
drivers/clk/imx/clk-sscg-pll.c
386
struct clk_sscg_pll *pll = to_clk_sscg_pll(hw);
drivers/clk/imx/clk-sscg-pll.c
388
u8 ret = pll->parent;
drivers/clk/imx/clk-sscg-pll.c
390
val = readl(pll->base + PLL_CFG0);
drivers/clk/imx/clk-sscg-pll.c
392
ret = pll->bypass2;
drivers/clk/imx/clk-sscg-pll.c
394
ret = pll->bypass1;
drivers/clk/imx/clk-sscg-pll.c
400
struct clk_sscg_pll *pll = to_clk_sscg_pll(hw);
drivers/clk/imx/clk-sscg-pll.c
403
val = readl(pll->base + PLL_CFG0);
drivers/clk/imx/clk-sscg-pll.c
405
val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, pll->setup.bypass);
drivers/clk/imx/clk-sscg-pll.c
406
writel(val, pll->base + PLL_CFG0);
drivers/clk/imx/clk-sscg-pll.c
408
return clk_sscg_pll_wait_lock(pll);
drivers/clk/imx/clk-sscg-pll.c
418
struct clk_sscg_pll *pll = to_clk_sscg_pll(hw);
drivers/clk/imx/clk-sscg-pll.c
419
struct clk_sscg_pll_setup *setup = &pll->setup;
drivers/clk/imx/clk-sscg-pll.c
429
bypass_parent_index = pll->bypass2;
drivers/clk/imx/clk-sscg-pll.c
432
bypass_parent_index = pll->bypass1;
drivers/clk/imx/clk-sscg-pll.c
435
bypass_parent_index = pll->parent;
drivers/clk/imx/clk-sscg-pll.c
456
struct clk_sscg_pll *pll = to_clk_sscg_pll(hw);
drivers/clk/imx/clk-sscg-pll.c
457
struct clk_sscg_pll_setup *setup = &pll->setup;
drivers/clk/imx/clk-sscg-pll.c
507
struct clk_sscg_pll *pll;
drivers/clk/imx/clk-sscg-pll.c
512
pll = kzalloc_obj(*pll);
drivers/clk/imx/clk-sscg-pll.c
513
if (!pll)
drivers/clk/imx/clk-sscg-pll.c
516
pll->parent = parent;
drivers/clk/imx/clk-sscg-pll.c
517
pll->bypass1 = bypass1;
drivers/clk/imx/clk-sscg-pll.c
518
pll->bypass2 = bypass2;
drivers/clk/imx/clk-sscg-pll.c
520
pll->base = base;
drivers/clk/imx/clk-sscg-pll.c
528
pll->hw.init = &init;
drivers/clk/imx/clk-sscg-pll.c
530
hw = &pll->hw;
drivers/clk/imx/clk-sscg-pll.c
534
kfree(pll);
drivers/clk/imx/clk-sscg-pll.c
98
static int clk_sscg_pll_wait_lock(struct clk_sscg_pll *pll)
drivers/clk/imx/clk.h
104
#define imx_clk_cpu(name, parent_name, div, mux, pll, step) \
drivers/clk/imx/clk.h
105
to_clk(imx_clk_hw_cpu(name, parent_name, div, mux, pll, step))
drivers/clk/imx/clk.h
402
struct clk *div, struct clk *mux, struct clk *pll,
drivers/clk/ingenic/cgu.c
158
const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
drivers/clk/ingenic/cgu.c
209
const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
drivers/clk/ingenic/cgu.c
254
const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
drivers/clk/ingenic/cgu.c
288
const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
drivers/clk/ingenic/cgu.c
309
const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
drivers/clk/ingenic/cgu.c
91
pll_info = &clk_info->pll;
drivers/clk/ingenic/cgu.h
177
struct ingenic_cgu_pll_info pll;
drivers/clk/ingenic/jz4725b-cgu.c
57
.pll = {
drivers/clk/ingenic/jz4740-cgu.c
72
.pll = {
drivers/clk/ingenic/jz4755-cgu.c
54
.pll = {
drivers/clk/ingenic/jz4760-cgu.c
120
.pll = {
drivers/clk/ingenic/jz4760-cgu.c
95
.pll = {
drivers/clk/ingenic/jz4770-cgu.c
105
.pll = {
drivers/clk/ingenic/jz4770-cgu.c
129
.pll = {
drivers/clk/ingenic/jz4780-cgu.c
295
.pll = DEF_PLL(APLL),
drivers/clk/ingenic/jz4780-cgu.c
301
.pll = DEF_PLL(MPLL),
drivers/clk/ingenic/jz4780-cgu.c
307
.pll = DEF_PLL(EPLL),
drivers/clk/ingenic/jz4780-cgu.c
313
.pll = DEF_PLL(VPLL),
drivers/clk/ingenic/x1000-cgu.c
221
.pll = {
drivers/clk/ingenic/x1000-cgu.c
244
.pll = {
drivers/clk/ingenic/x1000-cgu.c
365
.pll = {
drivers/clk/ingenic/x1830-cgu.c
115
.pll = {
drivers/clk/ingenic/x1830-cgu.c
138
.pll = {
drivers/clk/ingenic/x1830-cgu.c
161
.pll = {
drivers/clk/ingenic/x1830-cgu.c
184
.pll = {
drivers/clk/keystone/pll.c
126
struct clk_pll *pll;
drivers/clk/keystone/pll.c
129
pll = kzalloc_obj(*pll);
drivers/clk/keystone/pll.c
130
if (!pll)
drivers/clk/keystone/pll.c
139
pll->pll_data = pll_data;
drivers/clk/keystone/pll.c
140
pll->hw.init = &init;
drivers/clk/keystone/pll.c
142
clk = clk_register(NULL, &pll->hw);
drivers/clk/keystone/pll.c
148
kfree(pll);
drivers/clk/keystone/pll.c
78
struct clk_pll *pll = to_clk_pll(hw);
drivers/clk/keystone/pll.c
79
struct clk_pll_data *pll_data = pll->pll_data;
drivers/clk/mediatek/clk-fhctl.c
116
static int hopping_hw_flow(struct mtk_clk_pll *pll, struct fh_pll_regs *regs,
drivers/clk/mediatek/clk-fhctl.c
126
fhctl_set_ssc_regs(pll, regs, data, 0);
drivers/clk/mediatek/clk-fhctl.c
128
writel((readl(pll->pcw_addr) & dds_mask) | data->tgl_org,
drivers/clk/mediatek/clk-fhctl.c
144
pr_warn("%s: FHCTL hopping timeout\n", pll->data->name);
drivers/clk/mediatek/clk-fhctl.c
145
dump_hw(pll, regs, data);
drivers/clk/mediatek/clk-fhctl.c
148
con_pcw_tmp = readl(pll->pcw_addr) & (~dds_mask);
drivers/clk/mediatek/clk-fhctl.c
152
writel(con_pcw_tmp, pll->pcw_addr);
drivers/clk/mediatek/clk-fhctl.c
156
fhctl_set_ssc_regs(pll, regs, data, state->ssc_rate);
drivers/clk/mediatek/clk-fhctl.c
161
static unsigned int __get_postdiv(struct mtk_clk_pll *pll)
drivers/clk/mediatek/clk-fhctl.c
165
regval = readl(pll->pd_addr) >> pll->data->pd_shift;
drivers/clk/mediatek/clk-fhctl.c
171
static void __set_postdiv(struct mtk_clk_pll *pll, unsigned int postdiv)
drivers/clk/mediatek/clk-fhctl.c
175
regval = readl(pll->pd_addr);
drivers/clk/mediatek/clk-fhctl.c
176
regval &= ~(POSTDIV_MASK << pll->data->pd_shift);
drivers/clk/mediatek/clk-fhctl.c
177
regval |= (ffs(postdiv) - 1) << pll->data->pd_shift;
drivers/clk/mediatek/clk-fhctl.c
178
writel(regval, pll->pd_addr);
drivers/clk/mediatek/clk-fhctl.c
187
struct mtk_clk_pll *pll = &fh->clk_pll;
drivers/clk/mediatek/clk-fhctl.c
194
pll_postdiv = __get_postdiv(pll);
drivers/clk/mediatek/clk-fhctl.c
197
__set_postdiv(pll, postdiv);
drivers/clk/mediatek/clk-fhctl.c
202
ret = hopping_hw_flow(pll, regs, data, state, new_dds);
drivers/clk/mediatek/clk-fhctl.c
207
__set_postdiv(pll, postdiv);
drivers/clk/mediatek/clk-fhctl.c
217
struct mtk_clk_pll *pll = &fh->clk_pll;
drivers/clk/mediatek/clk-fhctl.c
223
fhctl_set_ssc_regs(pll, regs, data, rate);
drivers/clk/mediatek/clk-fhctl.c
55
static void dump_hw(struct mtk_clk_pll *pll, struct fh_pll_regs *regs,
drivers/clk/mediatek/clk-fhctl.c
65
pr_info("pcw<%x>\n", readl(pll->pcw_addr));
drivers/clk/mediatek/clk-fhctl.c
68
static int fhctl_set_ssc_regs(struct mtk_clk_pll *pll, struct fh_pll_regs *regs,
drivers/clk/mediatek/clk-fhctl.c
89
writel((readl(pll->pcw_addr) & data->dds_mask) | data->tgl_org,
drivers/clk/mediatek/clk-pll.c
101
static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
drivers/clk/mediatek/clk-pll.c
107
__mtk_pll_tuner_disable(pll);
drivers/clk/mediatek/clk-pll.c
110
val = readl(pll->pd_addr);
drivers/clk/mediatek/clk-pll.c
111
val &= ~(POSTDIV_MASK << pll->data->pd_shift);
drivers/clk/mediatek/clk-pll.c
112
val |= (ffs(postdiv) - 1) << pll->data->pd_shift;
drivers/clk/mediatek/clk-pll.c
115
if (pll->pd_addr != pll->pcw_addr) {
drivers/clk/mediatek/clk-pll.c
116
writel(val, pll->pd_addr);
drivers/clk/mediatek/clk-pll.c
117
val = readl(pll->pcw_addr);
drivers/clk/mediatek/clk-pll.c
121
val &= ~GENMASK(pll->data->pcw_shift + pll->data->pcwbits - 1,
drivers/clk/mediatek/clk-pll.c
122
pll->data->pcw_shift);
drivers/clk/mediatek/clk-pll.c
123
val |= pcw << pll->data->pcw_shift;
drivers/clk/mediatek/clk-pll.c
124
writel(val, pll->pcw_addr);
drivers/clk/mediatek/clk-pll.c
125
chg = readl(pll->pcw_chg_addr) |
drivers/clk/mediatek/clk-pll.c
126
BIT(pll->data->pcw_chg_bit ? : PCW_CHG_BIT);
drivers/clk/mediatek/clk-pll.c
127
writel(chg, pll->pcw_chg_addr);
drivers/clk/mediatek/clk-pll.c
128
if (pll->tuner_addr)
drivers/clk/mediatek/clk-pll.c
129
writel(val + 1, pll->tuner_addr);
drivers/clk/mediatek/clk-pll.c
132
__mtk_pll_tuner_enable(pll);
drivers/clk/mediatek/clk-pll.c
146
void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
drivers/clk/mediatek/clk-pll.c
149
unsigned long fmin = pll->data->fmin ? pll->data->fmin : (1000 * MHZ);
drivers/clk/mediatek/clk-pll.c
150
const struct mtk_pll_div_table *div_table = pll->data->div_table;
drivers/clk/mediatek/clk-pll.c
155
if (freq > pll->data->fmax)
drivers/clk/mediatek/clk-pll.c
156
freq = pll->data->fmax;
drivers/clk/mediatek/clk-pll.c
176
ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;
drivers/clk/mediatek/clk-pll.c
177
_pcw = ((u64)freq << val) << (pll->data->pcwbits - ibits);
drivers/clk/mediatek/clk-pll.c
186
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
drivers/clk/mediatek/clk-pll.c
190
mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate);
drivers/clk/mediatek/clk-pll.c
191
mtk_pll_set_rate_regs(pll, pcw, postdiv);
drivers/clk/mediatek/clk-pll.c
198
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
drivers/clk/mediatek/clk-pll.c
202
postdiv = (readl(pll->pd_addr) >> pll->data->pd_shift) & POSTDIV_MASK;
drivers/clk/mediatek/clk-pll.c
205
pcw = readl(pll->pcw_addr) >> pll->data->pcw_shift;
drivers/clk/mediatek/clk-pll.c
206
pcw &= GENMASK(pll->data->pcwbits - 1, 0);
drivers/clk/mediatek/clk-pll.c
208
return __mtk_pll_recalc_rate(pll, parent_rate, pcw, postdiv);
drivers/clk/mediatek/clk-pll.c
213
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
drivers/clk/mediatek/clk-pll.c
217
mtk_pll_calc_values(pll, &pcw, &postdiv, req->rate,
drivers/clk/mediatek/clk-pll.c
220
req->rate = __mtk_pll_recalc_rate(pll, req->best_parent_rate, pcw,
drivers/clk/mediatek/clk-pll.c
228
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
drivers/clk/mediatek/clk-pll.c
231
r = readl(pll->pwr_addr) | CON0_PWR_ON;
drivers/clk/mediatek/clk-pll.c
232
writel(r, pll->pwr_addr);
drivers/clk/mediatek/clk-pll.c
235
r = readl(pll->pwr_addr) & ~CON0_ISO_EN;
drivers/clk/mediatek/clk-pll.c
236
writel(r, pll->pwr_addr);
drivers/clk/mediatek/clk-pll.c
239
r = readl(pll->en_addr) | BIT(pll->data->pll_en_bit);
drivers/clk/mediatek/clk-pll.c
240
writel(r, pll->en_addr);
drivers/clk/mediatek/clk-pll.c
242
if (pll->data->en_mask) {
drivers/clk/mediatek/clk-pll.c
243
r = readl(pll->base_addr + REG_CON0) | pll->data->en_mask;
drivers/clk/mediatek/clk-pll.c
244
writel(r, pll->base_addr + REG_CON0);
drivers/clk/mediatek/clk-pll.c
247
__mtk_pll_tuner_enable(pll);
drivers/clk/mediatek/clk-pll.c
251
if (pll->data->flags & HAVE_RST_BAR) {
drivers/clk/mediatek/clk-pll.c
252
r = readl(pll->base_addr + REG_CON0);
drivers/clk/mediatek/clk-pll.c
253
r |= pll->data->rst_bar_mask;
drivers/clk/mediatek/clk-pll.c
254
writel(r, pll->base_addr + REG_CON0);
drivers/clk/mediatek/clk-pll.c
262
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
drivers/clk/mediatek/clk-pll.c
265
if (pll->data->flags & HAVE_RST_BAR) {
drivers/clk/mediatek/clk-pll.c
266
r = readl(pll->base_addr + REG_CON0);
drivers/clk/mediatek/clk-pll.c
267
r &= ~pll->data->rst_bar_mask;
drivers/clk/mediatek/clk-pll.c
268
writel(r, pll->base_addr + REG_CON0);
drivers/clk/mediatek/clk-pll.c
271
__mtk_pll_tuner_disable(pll);
drivers/clk/mediatek/clk-pll.c
273
if (pll->data->en_mask) {
drivers/clk/mediatek/clk-pll.c
274
r = readl(pll->base_addr + REG_CON0) & ~pll->data->en_mask;
drivers/clk/mediatek/clk-pll.c
275
writel(r, pll->base_addr + REG_CON0);
drivers/clk/mediatek/clk-pll.c
278
r = readl(pll->en_addr) & ~BIT(pll->data->pll_en_bit);
drivers/clk/mediatek/clk-pll.c
279
writel(r, pll->en_addr);
drivers/clk/mediatek/clk-pll.c
281
r = readl(pll->pwr_addr) | CON0_ISO_EN;
drivers/clk/mediatek/clk-pll.c
282
writel(r, pll->pwr_addr);
drivers/clk/mediatek/clk-pll.c
284
r = readl(pll->pwr_addr) & ~CON0_PWR_ON;
drivers/clk/mediatek/clk-pll.c
285
writel(r, pll->pwr_addr);
drivers/clk/mediatek/clk-pll.c
290
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
drivers/clk/mediatek/clk-pll.c
292
writel(BIT(pll->data->pll_en_bit), pll->en_set_addr);
drivers/clk/mediatek/clk-pll.c
302
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
drivers/clk/mediatek/clk-pll.c
304
writel(BIT(pll->data->pll_en_bit), pll->en_clr_addr);
drivers/clk/mediatek/clk-pll.c
326
struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll,
drivers/clk/mediatek/clk-pll.c
335
pll->base_addr = base + data->reg;
drivers/clk/mediatek/clk-pll.c
336
pll->pwr_addr = base + data->pwr_reg;
drivers/clk/mediatek/clk-pll.c
337
pll->pd_addr = base + data->pd_reg;
drivers/clk/mediatek/clk-pll.c
338
pll->pcw_addr = base + data->pcw_reg;
drivers/clk/mediatek/clk-pll.c
340
pll->pcw_chg_addr = base + data->pcw_chg_reg;
drivers/clk/mediatek/clk-pll.c
342
pll->pcw_chg_addr = pll->base_addr + REG_CON1;
drivers/clk/mediatek/clk-pll.c
344
pll->tuner_addr = base + data->tuner_reg;
drivers/clk/mediatek/clk-pll.c
346
pll->tuner_en_addr = base + data->tuner_en_reg;
drivers/clk/mediatek/clk-pll.c
348
pll->en_addr = base + data->en_reg;
drivers/clk/mediatek/clk-pll.c
350
pll->en_addr = pll->base_addr + REG_CON0;
drivers/clk/mediatek/clk-pll.c
352
pll->en_set_addr = base + data->en_set_reg;
drivers/clk/mediatek/clk-pll.c
354
pll->en_clr_addr = base + data->en_clr_reg;
drivers/clk/mediatek/clk-pll.c
355
pll->hw.init = &init;
drivers/clk/mediatek/clk-pll.c
356
pll->data = data;
drivers/clk/mediatek/clk-pll.c
358
pll->fenc_addr = base + data->fenc_sta_ofs;
drivers/clk/mediatek/clk-pll.c
36
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
drivers/clk/mediatek/clk-pll.c
372
ret = clk_hw_register(pll->dev, &pll->hw);
drivers/clk/mediatek/clk-pll.c
377
return &pll->hw;
drivers/clk/mediatek/clk-pll.c
38
return (readl(pll->en_addr) & BIT(pll->data->pll_en_bit)) != 0;
drivers/clk/mediatek/clk-pll.c
384
struct mtk_clk_pll *pll;
drivers/clk/mediatek/clk-pll.c
388
pll = kzalloc_obj(*pll);
drivers/clk/mediatek/clk-pll.c
389
if (!pll)
drivers/clk/mediatek/clk-pll.c
392
pll->dev = dev;
drivers/clk/mediatek/clk-pll.c
394
hw = mtk_clk_register_pll_ops(pll, data, base, pll_ops);
drivers/clk/mediatek/clk-pll.c
396
kfree(pll);
drivers/clk/mediatek/clk-pll.c
403
struct mtk_clk_pll *pll;
drivers/clk/mediatek/clk-pll.c
408
pll = to_mtk_clk_pll(hw);
drivers/clk/mediatek/clk-pll.c
411
kfree(pll);
drivers/clk/mediatek/clk-pll.c
429
const struct mtk_pll_data *pll = &plls[i];
drivers/clk/mediatek/clk-pll.c
43
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
drivers/clk/mediatek/clk-pll.c
431
if (!IS_ERR_OR_NULL(clk_data->hws[pll->id])) {
drivers/clk/mediatek/clk-pll.c
433
dev->of_node, pll->id);
drivers/clk/mediatek/clk-pll.c
437
hw = mtk_clk_register_pll(dev, pll, base);
drivers/clk/mediatek/clk-pll.c
440
pr_err("Failed to register clk %s: %pe\n", pll->name,
drivers/clk/mediatek/clk-pll.c
445
clk_data->hws[pll->id] = hw;
drivers/clk/mediatek/clk-pll.c
45
return !!(readl(pll->fenc_addr) & BIT(pll->data->fenc_sta_bit));
drivers/clk/mediatek/clk-pll.c
452
const struct mtk_pll_data *pll = &plls[i];
drivers/clk/mediatek/clk-pll.c
454
mtk_clk_unregister_pll(clk_data->hws[pll->id]);
drivers/clk/mediatek/clk-pll.c
455
clk_data->hws[pll->id] = ERR_PTR(-ENOENT);
drivers/clk/mediatek/clk-pll.c
467
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
drivers/clk/mediatek/clk-pll.c
469
return pll->base_addr - data->reg;
drivers/clk/mediatek/clk-pll.c
48
static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
drivers/clk/mediatek/clk-pll.c
482
const struct mtk_pll_data *pll = &plls[i - 1];
drivers/clk/mediatek/clk-pll.c
484
if (IS_ERR_OR_NULL(clk_data->hws[pll->id]))
drivers/clk/mediatek/clk-pll.c
493
base = mtk_clk_pll_get_base(clk_data->hws[pll->id], pll);
drivers/clk/mediatek/clk-pll.c
495
mtk_clk_unregister_pll(clk_data->hws[pll->id]);
drivers/clk/mediatek/clk-pll.c
496
clk_data->hws[pll->id] = ERR_PTR(-ENOENT);
drivers/clk/mediatek/clk-pll.c
51
int pcwbits = pll->data->pcwbits;
drivers/clk/mediatek/clk-pll.c
58
ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;
drivers/clk/mediatek/clk-pll.c
75
static void __mtk_pll_tuner_enable(struct mtk_clk_pll *pll)
drivers/clk/mediatek/clk-pll.c
79
if (pll->tuner_en_addr) {
drivers/clk/mediatek/clk-pll.c
80
r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit);
drivers/clk/mediatek/clk-pll.c
81
writel(r, pll->tuner_en_addr);
drivers/clk/mediatek/clk-pll.c
82
} else if (pll->tuner_addr) {
drivers/clk/mediatek/clk-pll.c
83
r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;
drivers/clk/mediatek/clk-pll.c
84
writel(r, pll->tuner_addr);
drivers/clk/mediatek/clk-pll.c
88
static void __mtk_pll_tuner_disable(struct mtk_clk_pll *pll)
drivers/clk/mediatek/clk-pll.c
92
if (pll->tuner_en_addr) {
drivers/clk/mediatek/clk-pll.c
93
r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);
drivers/clk/mediatek/clk-pll.c
94
writel(r, pll->tuner_en_addr);
drivers/clk/mediatek/clk-pll.c
95
} else if (pll->tuner_addr) {
drivers/clk/mediatek/clk-pll.c
96
r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;
drivers/clk/mediatek/clk-pll.c
97
writel(r, pll->tuner_addr);
drivers/clk/mediatek/clk-pll.h
103
void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
drivers/clk/mediatek/clk-pll.h
109
struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll,
drivers/clk/mediatek/clk-pllfh.c
216
const struct mtk_pll_data *pll = &plls[i];
drivers/clk/mediatek/clk-pllfh.c
220
pllfh = get_pllfh_by_id(pllfhs, num_fhs, pll->id);
drivers/clk/mediatek/clk-pllfh.c
224
hw = mtk_clk_register_pllfh(dev, pll, pllfh, base);
drivers/clk/mediatek/clk-pllfh.c
226
hw = mtk_clk_register_pll(dev, pll, base);
drivers/clk/mediatek/clk-pllfh.c
23
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
drivers/clk/mediatek/clk-pllfh.c
230
use_fhctl ? "fhpll" : "pll", pll->name,
drivers/clk/mediatek/clk-pllfh.c
235
clk_data->hws[pll->id] = hw;
drivers/clk/mediatek/clk-pllfh.c
242
const struct mtk_pll_data *pll = &plls[i];
drivers/clk/mediatek/clk-pllfh.c
246
pllfh = get_pllfh_by_id(pllfhs, num_fhs, pll->id);
drivers/clk/mediatek/clk-pllfh.c
25
return container_of(pll, struct mtk_fh, clk_pll);
drivers/clk/mediatek/clk-pllfh.c
250
mtk_clk_unregister_pllfh(clk_data->hws[pll->id]);
drivers/clk/mediatek/clk-pllfh.c
252
mtk_clk_unregister_pll(clk_data->hws[pll->id]);
drivers/clk/mediatek/clk-pllfh.c
254
clk_data->hws[pll->id] = ERR_PTR(-ENOENT);
drivers/clk/mediatek/clk-pllfh.c
274
const struct mtk_pll_data *pll = &plls[i - 1];
drivers/clk/mediatek/clk-pllfh.c
278
if (IS_ERR_OR_NULL(clk_data->hws[pll->id]))
drivers/clk/mediatek/clk-pllfh.c
281
pllfh = get_pllfh_by_id(pllfhs, num_fhs, pll->id);
drivers/clk/mediatek/clk-pllfh.c
286
mtk_clk_unregister_pllfh(clk_data->hws[pll->id]);
drivers/clk/mediatek/clk-pllfh.c
288
base = mtk_clk_pll_get_base(clk_data->hws[pll->id],
drivers/clk/mediatek/clk-pllfh.c
289
pll);
drivers/clk/mediatek/clk-pllfh.c
290
mtk_clk_unregister_pll(clk_data->hws[pll->id]);
drivers/clk/mediatek/clk-pllfh.c
293
clk_data->hws[pll->id] = ERR_PTR(-ENOENT);
drivers/clk/mediatek/clk-pllfh.c
31
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
drivers/clk/mediatek/clk-pllfh.c
36
mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate);
drivers/clk/meson/clk-pll.c
102
struct meson_clk_pll_data *pll)
drivers/clk/meson/clk-pll.c
104
unsigned int frac_max = pll->frac_max ? pll->frac_max :
drivers/clk/meson/clk-pll.c
105
(1 << pll->frac.width);
drivers/clk/meson/clk-pll.c
112
if (pll->flags & CLK_MESON_PLL_ROUND_CLOSEST)
drivers/clk/meson/clk-pll.c
125
struct meson_clk_pll_data *pll)
drivers/clk/meson/clk-pll.c
127
if (__pll_round_closest_mult(pll)) {
drivers/clk/meson/clk-pll.c
143
struct meson_clk_pll_data *pll)
drivers/clk/meson/clk-pll.c
145
if (!pll->table[index].n)
drivers/clk/meson/clk-pll.c
148
*m = pll->table[index].m;
drivers/clk/meson/clk-pll.c
149
*n = pll->table[index].n;
drivers/clk/meson/clk-pll.c
157
struct meson_clk_pll_data *pll)
drivers/clk/meson/clk-pll.c
161
if (__pll_round_closest_mult(pll))
drivers/clk/meson/clk-pll.c
172
struct meson_clk_pll_data *pll)
drivers/clk/meson/clk-pll.c
177
if (*n >= (1 << pll->n.width))
drivers/clk/meson/clk-pll.c
182
if (rate <= pll->range->min * parent_rate) {
drivers/clk/meson/clk-pll.c
183
*m = pll->range->min;
drivers/clk/meson/clk-pll.c
185
} else if (rate >= pll->range->max * parent_rate) {
drivers/clk/meson/clk-pll.c
186
*m = pll->range->max;
drivers/clk/meson/clk-pll.c
191
*m = meson_clk_get_pll_range_m(rate, parent_rate, *n, pll);
drivers/clk/meson/clk-pll.c
194
if (*m >= (1 << pll->m.width))
drivers/clk/meson/clk-pll.c
205
struct meson_clk_pll_data *pll)
drivers/clk/meson/clk-pll.c
207
if (pll->range)
drivers/clk/meson/clk-pll.c
209
index, m, n, pll);
drivers/clk/meson/clk-pll.c
210
else if (pll->table)
drivers/clk/meson/clk-pll.c
211
return meson_clk_get_pll_table_index(index, m, n, pll);
drivers/clk/meson/clk-pll.c
220
struct meson_clk_pll_data *pll)
drivers/clk/meson/clk-pll.c
228
i, &m, &n, pll);
drivers/clk/meson/clk-pll.c
232
now = __pll_params_to_rate(parent_rate, m, n, 0, pll);
drivers/clk/meson/clk-pll.c
233
if (meson_clk_pll_is_better(rate, best, now, pll)) {
drivers/clk/meson/clk-pll.c
250
struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
drivers/clk/meson/clk-pll.c
256
&m, &n, pll);
drivers/clk/meson/clk-pll.c
260
round = __pll_params_to_rate(req->best_parent_rate, m, n, 0, pll);
drivers/clk/meson/clk-pll.c
262
if (!MESON_PARM_APPLICABLE(&pll->frac) || req->rate == round) {
drivers/clk/meson/clk-pll.c
271
frac = __pll_params_with_frac(req->rate, req->best_parent_rate, m, n, pll);
drivers/clk/meson/clk-pll.c
272
req->rate = __pll_params_to_rate(req->best_parent_rate, m, n, frac, pll);
drivers/clk/meson/clk-pll.c
280
struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
drivers/clk/meson/clk-pll.c
285
if (meson_parm_read(clk->map, &pll->l))
drivers/clk/meson/clk-pll.c
297
struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
drivers/clk/meson/clk-pll.c
299
if (MESON_PARM_APPLICABLE(&pll->rst) &&
drivers/clk/meson/clk-pll.c
300
meson_parm_read(clk->map, &pll->rst))
drivers/clk/meson/clk-pll.c
303
if (!meson_parm_read(clk->map, &pll->en) ||
drivers/clk/meson/clk-pll.c
304
!meson_parm_read(clk->map, &pll->l))
drivers/clk/meson/clk-pll.c
313
struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
drivers/clk/meson/clk-pll.c
324
if ((pll->flags & CLK_MESON_PLL_NOINIT_ENABLED) &&
drivers/clk/meson/clk-pll.c
328
if (pll->init_count) {
drivers/clk/meson/clk-pll.c
329
if (MESON_PARM_APPLICABLE(&pll->rst))
drivers/clk/meson/clk-pll.c
330
meson_parm_write(clk->map, &pll->rst, 1);
drivers/clk/meson/clk-pll.c
332
regmap_multi_reg_write(clk->map, pll->init_regs,
drivers/clk/meson/clk-pll.c
333
pll->init_count);
drivers/clk/meson/clk-pll.c
335
if (MESON_PARM_APPLICABLE(&pll->rst))
drivers/clk/meson/clk-pll.c
336
meson_parm_write(clk->map, &pll->rst, 0);
drivers/clk/meson/clk-pll.c
359
struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
drivers/clk/meson/clk-pll.c
366
if (MESON_PARM_APPLICABLE(&pll->rst))
drivers/clk/meson/clk-pll.c
367
meson_parm_write(clk->map, &pll->rst, 1);
drivers/clk/meson/clk-pll.c
370
meson_parm_write(clk->map, &pll->en, 1);
drivers/clk/meson/clk-pll.c
373
if (MESON_PARM_APPLICABLE(&pll->rst))
drivers/clk/meson/clk-pll.c
374
meson_parm_write(clk->map, &pll->rst, 0);
drivers/clk/meson/clk-pll.c
384
if (MESON_PARM_APPLICABLE(&pll->current_en)) {
drivers/clk/meson/clk-pll.c
386
meson_parm_write(clk->map, &pll->current_en, 1);
drivers/clk/meson/clk-pll.c
390
if (MESON_PARM_APPLICABLE(&pll->l_detect)) {
drivers/clk/meson/clk-pll.c
391
meson_parm_write(clk->map, &pll->l_detect, 1);
drivers/clk/meson/clk-pll.c
392
meson_parm_write(clk->map, &pll->l_detect, 0);
drivers/clk/meson/clk-pll.c
404
struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
drivers/clk/meson/clk-pll.c
407
if (MESON_PARM_APPLICABLE(&pll->rst))
drivers/clk/meson/clk-pll.c
408
meson_parm_write(clk->map, &pll->rst, 1);
drivers/clk/meson/clk-pll.c
411
meson_parm_write(clk->map, &pll->en, 0);
drivers/clk/meson/clk-pll.c
414
if (MESON_PARM_APPLICABLE(&pll->current_en))
drivers/clk/meson/clk-pll.c
415
meson_parm_write(clk->map, &pll->current_en, 0);
drivers/clk/meson/clk-pll.c
422
struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
drivers/clk/meson/clk-pll.c
432
ret = meson_clk_get_pll_settings(rate, parent_rate, &m, &n, pll);
drivers/clk/meson/clk-pll.c
436
enabled = meson_parm_read(clk->map, &pll->en);
drivers/clk/meson/clk-pll.c
440
meson_parm_write(clk->map, &pll->n, n);
drivers/clk/meson/clk-pll.c
441
meson_parm_write(clk->map, &pll->m, m);
drivers/clk/meson/clk-pll.c
443
if (MESON_PARM_APPLICABLE(&pll->frac)) {
drivers/clk/meson/clk-pll.c
444
frac = __pll_params_with_frac(rate, parent_rate, m, n, pll);
drivers/clk/meson/clk-pll.c
445
meson_parm_write(clk->map, &pll->frac, frac);
drivers/clk/meson/clk-pll.c
45
static int __pll_round_closest_mult(struct meson_clk_pll_data *pll)
drivers/clk/meson/clk-pll.c
47
if ((pll->flags & CLK_MESON_PLL_ROUND_CLOSEST) &&
drivers/clk/meson/clk-pll.c
48
!MESON_PARM_APPLICABLE(&pll->frac))
drivers/clk/meson/clk-pll.c
57
struct meson_clk_pll_data *pll)
drivers/clk/meson/clk-pll.c
60
unsigned int frac_max = pll->frac_max ? pll->frac_max :
drivers/clk/meson/clk-pll.c
61
(1 << pll->frac.width);
drivers/clk/meson/clk-pll.c
63
if (frac && MESON_PARM_APPLICABLE(&pll->frac)) {
drivers/clk/meson/clk-pll.c
76
struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
drivers/clk/meson/clk-pll.c
79
n = meson_parm_read(clk->map, &pll->n);
drivers/clk/meson/clk-pll.c
89
m = meson_parm_read(clk->map, &pll->m);
drivers/clk/meson/clk-pll.c
91
frac = MESON_PARM_APPLICABLE(&pll->frac) ?
drivers/clk/meson/clk-pll.c
92
meson_parm_read(clk->map, &pll->frac) :
drivers/clk/meson/clk-pll.c
95
return __pll_params_to_rate(parent_rate, m, n, frac, pll);
drivers/clk/microchip/clk-pic32.c
593
static unsigned long spll_calc_mult_div(struct pic32_sys_pll *pll,
drivers/clk/microchip/clk-pic32.c
603
parent_rate /= pll->idiv;
drivers/clk/microchip/clk-pic32.c
642
struct pic32_sys_pll *pll = clkhw_to_spll(hw);
drivers/clk/microchip/clk-pic32.c
647
v = readl(pll->ctrl_reg);
drivers/clk/microchip/clk-pic32.c
655
pll_in_rate = parent_rate / pll->idiv;
drivers/clk/microchip/clk-pic32.c
666
struct pic32_sys_pll *pll = clkhw_to_spll(hw);
drivers/clk/microchip/clk-pic32.c
668
req->rate = spll_calc_mult_div(pll, req->rate, req->best_parent_rate,
drivers/clk/microchip/clk-pic32.c
677
struct pic32_sys_pll *pll = clkhw_to_spll(hw);
drivers/clk/microchip/clk-pic32.c
682
ret = spll_calc_mult_div(pll, rate, parent_rate, &mult, &odiv);
drivers/clk/microchip/clk-pic32.c
697
spin_lock_irqsave(&pll->core->reg_lock, flags);
drivers/clk/microchip/clk-pic32.c
700
v = readl(pll->ctrl_reg);
drivers/clk/microchip/clk-pic32.c
708
writel(v, pll->ctrl_reg);
drivers/clk/microchip/clk-pic32.c
716
err = readl_poll_timeout_atomic(pll->status_reg, v,
drivers/clk/microchip/clk-pic32.c
717
v & pll->lock_mask, 1, 100);
drivers/clk/microchip/clk-pic32.c
718
spin_unlock_irqrestore(&pll->core->reg_lock, flags);
drivers/clk/mmp/clk-pll.c
107
struct mmp_clk_pll *pll;
drivers/clk/mmp/clk-pll.c
111
pll = kzalloc_obj(*pll);
drivers/clk/mmp/clk-pll.c
112
if (!pll)
drivers/clk/mmp/clk-pll.c
121
pll->default_rate = default_rate;
drivers/clk/mmp/clk-pll.c
122
pll->enable_reg = enable_reg;
drivers/clk/mmp/clk-pll.c
123
pll->enable = enable;
drivers/clk/mmp/clk-pll.c
124
pll->reg = reg;
drivers/clk/mmp/clk-pll.c
125
pll->shift = shift;
drivers/clk/mmp/clk-pll.c
127
pll->input_rate = input_rate;
drivers/clk/mmp/clk-pll.c
128
pll->postdiv_reg = postdiv_reg;
drivers/clk/mmp/clk-pll.c
129
pll->postdiv_shift = postdiv_shift;
drivers/clk/mmp/clk-pll.c
131
pll->hw.init = &init;
drivers/clk/mmp/clk-pll.c
133
clk = clk_register(NULL, &pll->hw);
drivers/clk/mmp/clk-pll.c
136
kfree(pll);
drivers/clk/mmp/clk-pll.c
31
struct mmp_clk_pll *pll = to_clk_mmp_pll(hw);
drivers/clk/mmp/clk-pll.c
34
val = readl_relaxed(pll->enable_reg);
drivers/clk/mmp/clk-pll.c
35
if ((val & pll->enable) == pll->enable)
drivers/clk/mmp/clk-pll.c
39
if (pll->default_rate > 0)
drivers/clk/mmp/clk-pll.c
48
struct mmp_clk_pll *pll = to_clk_mmp_pll(hw);
drivers/clk/mmp/clk-pll.c
53
val = readl_relaxed(pll->enable_reg);
drivers/clk/mmp/clk-pll.c
54
if ((val & pll->enable) != pll->enable)
drivers/clk/mmp/clk-pll.c
55
return pll->default_rate;
drivers/clk/mmp/clk-pll.c
57
if (pll->reg) {
drivers/clk/mmp/clk-pll.c
58
val = readl_relaxed(pll->reg);
drivers/clk/mmp/clk-pll.c
59
fbdiv = (val >> pll->shift) & 0x1ff;
drivers/clk/mmp/clk-pll.c
60
refdiv = (val >> (pll->shift + 9)) & 0x1f;
drivers/clk/mmp/clk-pll.c
66
if (pll->postdiv_reg) {
drivers/clk/mmp/clk-pll.c
70
val = readl_relaxed(pll->postdiv_reg);
drivers/clk/mmp/clk-pll.c
71
postdiv = (val >> pll->postdiv_shift) & 0x7;
drivers/clk/mmp/clk-pll.c
73
rate = pll->input_rate;
drivers/clk/mxs/clk-imx23.c
113
clks[pll] = mxs_clk_pll("pll", "ref_xtal", PLLCTRL0, 16, 480000000);
drivers/clk/mxs/clk-pll.c
100
pll->rate = rate;
drivers/clk/mxs/clk-pll.c
101
pll->power = power;
drivers/clk/mxs/clk-pll.c
102
pll->hw.init = &init;
drivers/clk/mxs/clk-pll.c
104
clk = clk_register(NULL, &pll->hw);
drivers/clk/mxs/clk-pll.c
106
kfree(pll);
drivers/clk/mxs/clk-pll.c
34
struct clk_pll *pll = to_clk_pll(hw);
drivers/clk/mxs/clk-pll.c
36
writel_relaxed(1 << pll->power, pll->base + SET);
drivers/clk/mxs/clk-pll.c
45
struct clk_pll *pll = to_clk_pll(hw);
drivers/clk/mxs/clk-pll.c
47
writel_relaxed(1 << pll->power, pll->base + CLR);
drivers/clk/mxs/clk-pll.c
52
struct clk_pll *pll = to_clk_pll(hw);
drivers/clk/mxs/clk-pll.c
54
writel_relaxed(1 << 31, pll->base + CLR);
drivers/clk/mxs/clk-pll.c
61
struct clk_pll *pll = to_clk_pll(hw);
drivers/clk/mxs/clk-pll.c
63
writel_relaxed(1 << 31, pll->base + SET);
drivers/clk/mxs/clk-pll.c
69
struct clk_pll *pll = to_clk_pll(hw);
drivers/clk/mxs/clk-pll.c
71
return pll->rate;
drivers/clk/mxs/clk-pll.c
85
struct clk_pll *pll;
drivers/clk/mxs/clk-pll.c
89
pll = kzalloc_obj(*pll);
drivers/clk/mxs/clk-pll.c
90
if (!pll)
drivers/clk/mxs/clk-pll.c
99
pll->base = base;
drivers/clk/nuvoton/clk-ma35d1-pll.c
123
static int ma35d1_pll_find_closest(struct ma35d1_clk_pll *pll, unsigned long rate,
drivers/clk/nuvoton/clk-ma35d1-pll.c
135
if (pll->mode == PLL_MODE_INT) {
drivers/clk/nuvoton/clk-ma35d1-pll.c
155
if (pll->mode != PLL_MODE_INT)
drivers/clk/nuvoton/clk-ma35d1-pll.c
188
struct ma35d1_clk_pll *pll = to_ma35d1_clk_pll(hw);
drivers/clk/nuvoton/clk-ma35d1-pll.c
196
ret = ma35d1_pll_find_closest(pll, rate, parent_rate, reg_ctl, &pll_freq);
drivers/clk/nuvoton/clk-ma35d1-pll.c
200
switch (pll->mode) {
drivers/clk/nuvoton/clk-ma35d1-pll.c
215
writel_relaxed(reg_ctl[0], pll->ctl0_base);
drivers/clk/nuvoton/clk-ma35d1-pll.c
216
writel_relaxed(reg_ctl[1], pll->ctl1_base);
drivers/clk/nuvoton/clk-ma35d1-pll.c
217
writel_relaxed(reg_ctl[2], pll->ctl2_base);
drivers/clk/nuvoton/clk-ma35d1-pll.c
223
struct ma35d1_clk_pll *pll = to_ma35d1_clk_pll(hw);
drivers/clk/nuvoton/clk-ma35d1-pll.c
230
switch (pll->id) {
drivers/clk/nuvoton/clk-ma35d1-pll.c
232
reg_ctl[0] = readl_relaxed(pll->ctl0_base);
drivers/clk/nuvoton/clk-ma35d1-pll.c
239
reg_ctl[0] = readl_relaxed(pll->ctl0_base);
drivers/clk/nuvoton/clk-ma35d1-pll.c
240
reg_ctl[1] = readl_relaxed(pll->ctl1_base);
drivers/clk/nuvoton/clk-ma35d1-pll.c
241
pll_freq = ma35d1_calc_pll_freq(pll->mode, reg_ctl, parent_rate);
drivers/clk/nuvoton/clk-ma35d1-pll.c
250
struct ma35d1_clk_pll *pll = to_ma35d1_clk_pll(hw);
drivers/clk/nuvoton/clk-ma35d1-pll.c
258
ret = ma35d1_pll_find_closest(pll, req->rate, req->best_parent_rate,
drivers/clk/nuvoton/clk-ma35d1-pll.c
263
switch (pll->id) {
drivers/clk/nuvoton/clk-ma35d1-pll.c
265
reg_ctl[0] = readl_relaxed(pll->ctl0_base);
drivers/clk/nuvoton/clk-ma35d1-pll.c
274
reg_ctl[0] = readl_relaxed(pll->ctl0_base);
drivers/clk/nuvoton/clk-ma35d1-pll.c
275
reg_ctl[1] = readl_relaxed(pll->ctl1_base);
drivers/clk/nuvoton/clk-ma35d1-pll.c
276
pll_freq = ma35d1_calc_pll_freq(pll->mode, reg_ctl, req->best_parent_rate);
drivers/clk/nuvoton/clk-ma35d1-pll.c
289
struct ma35d1_clk_pll *pll = to_ma35d1_clk_pll(hw);
drivers/clk/nuvoton/clk-ma35d1-pll.c
290
u32 val = readl_relaxed(pll->ctl1_base);
drivers/clk/nuvoton/clk-ma35d1-pll.c
297
struct ma35d1_clk_pll *pll = to_ma35d1_clk_pll(hw);
drivers/clk/nuvoton/clk-ma35d1-pll.c
300
val = readl_relaxed(pll->ctl1_base);
drivers/clk/nuvoton/clk-ma35d1-pll.c
302
writel_relaxed(val, pll->ctl1_base);
drivers/clk/nuvoton/clk-ma35d1-pll.c
308
struct ma35d1_clk_pll *pll = to_ma35d1_clk_pll(hw);
drivers/clk/nuvoton/clk-ma35d1-pll.c
311
val = readl_relaxed(pll->ctl1_base);
drivers/clk/nuvoton/clk-ma35d1-pll.c
313
writel_relaxed(val, pll->ctl1_base);
drivers/clk/nuvoton/clk-ma35d1-pll.c
335
struct ma35d1_clk_pll *pll;
drivers/clk/nuvoton/clk-ma35d1-pll.c
339
pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL);
drivers/clk/nuvoton/clk-ma35d1-pll.c
340
if (!pll)
drivers/clk/nuvoton/clk-ma35d1-pll.c
343
pll->id = id;
drivers/clk/nuvoton/clk-ma35d1-pll.c
344
pll->mode = u8mode;
drivers/clk/nuvoton/clk-ma35d1-pll.c
345
pll->ctl0_base = base + REG_PLL_CTL0_OFFSET;
drivers/clk/nuvoton/clk-ma35d1-pll.c
346
pll->ctl1_base = base + REG_PLL_CTL1_OFFSET;
drivers/clk/nuvoton/clk-ma35d1-pll.c
347
pll->ctl2_base = base + REG_PLL_CTL2_OFFSET;
drivers/clk/nuvoton/clk-ma35d1-pll.c
360
pll->hw.init = &init;
drivers/clk/nuvoton/clk-ma35d1-pll.c
361
hw = &pll->hw;
drivers/clk/nxp/clk-lpc18xx-cgu.c
264
struct lpc18xx_pll pll;
drivers/clk/nxp/clk-lpc18xx-cgu.c
349
struct lpc18xx_pll *pll = to_lpc_pll(hw);
drivers/clk/nxp/clk-lpc18xx-cgu.c
352
ctrl = readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
drivers/clk/nxp/clk-lpc18xx-cgu.c
353
mdiv = readl(pll->reg + LPC18XX_CGU_PLL0USB_MDIV);
drivers/clk/nxp/clk-lpc18xx-cgu.c
354
npdiv = readl(pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV);
drivers/clk/nxp/clk-lpc18xx-cgu.c
397
struct lpc18xx_pll *pll = to_lpc_pll(hw);
drivers/clk/nxp/clk-lpc18xx-cgu.c
417
ctrl = readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
drivers/clk/nxp/clk-lpc18xx-cgu.c
421
writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
drivers/clk/nxp/clk-lpc18xx-cgu.c
424
writel(m, pll->reg + LPC18XX_CGU_PLL0USB_MDIV);
drivers/clk/nxp/clk-lpc18xx-cgu.c
425
writel(LPC18XX_PLL0_NP_DIVS_1, pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV);
drivers/clk/nxp/clk-lpc18xx-cgu.c
429
writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
drivers/clk/nxp/clk-lpc18xx-cgu.c
432
stat = readl(pll->reg + LPC18XX_CGU_PLL0USB_STAT);
drivers/clk/nxp/clk-lpc18xx-cgu.c
435
writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
drivers/clk/nxp/clk-lpc18xx-cgu.c
455
struct lpc18xx_pll *pll = to_lpc_pll(hw);
drivers/clk/nxp/clk-lpc18xx-cgu.c
460
ctrl = readl(pll->reg + LPC18XX_CGU_PLL1_CTRL);
drivers/clk/nxp/clk-lpc18xx-cgu.c
585
clk->pll.reg = base;
drivers/clk/nxp/clk-lpc18xx-cgu.c
593
&clk->pll.hw, clk->pll_ops,
drivers/clk/nxp/clk-lpc32xx.c
1062
struct lpc32xx_pll_clk pll;
drivers/clk/nxp/clk-lpc32xx.c
1104
.pll = { \
drivers/clk/nxp/clk-lpc32xx.c
1420
hw = &clk_hw->hw0.pll.hw;
drivers/clk/pistachio/clk-pll.c
107
struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
drivers/clk/pistachio/clk-pll.c
110
val = pll_readl(pll, PLL_CTRL3) & PLL_FRAC_CTRL3_DSMPD;
drivers/clk/pistachio/clk-pll.c
116
struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
drivers/clk/pistachio/clk-pll.c
119
val = pll_readl(pll, PLL_CTRL3);
drivers/clk/pistachio/clk-pll.c
125
pll_writel(pll, val, PLL_CTRL3);
drivers/clk/pistachio/clk-pll.c
129
pll_get_params(struct pistachio_clk_pll *pll, unsigned long fref,
drivers/clk/pistachio/clk-pll.c
134
for (i = 0; i < pll->nr_rates; i++) {
drivers/clk/pistachio/clk-pll.c
135
if (pll->rates[i].fref == fref && pll->rates[i].fout == fout)
drivers/clk/pistachio/clk-pll.c
136
return &pll->rates[i];
drivers/clk/pistachio/clk-pll.c
144
struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
drivers/clk/pistachio/clk-pll.c
147
for (i = 0; i < pll->nr_rates; i++) {
drivers/clk/pistachio/clk-pll.c
148
if (i > 0 && pll->rates[i].fref == req->best_parent_rate &&
drivers/clk/pistachio/clk-pll.c
149
pll->rates[i].fout <= req->rate) {
drivers/clk/pistachio/clk-pll.c
150
req->rate = pll->rates[i - 1].fout;
drivers/clk/pistachio/clk-pll.c
156
req->rate = pll->rates[0].fout;
drivers/clk/pistachio/clk-pll.c
163
struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
drivers/clk/pistachio/clk-pll.c
166
val = pll_readl(pll, PLL_CTRL3);
drivers/clk/pistachio/clk-pll.c
169
pll_writel(pll, val, PLL_CTRL3);
drivers/clk/pistachio/clk-pll.c
171
val = pll_readl(pll, PLL_CTRL4);
drivers/clk/pistachio/clk-pll.c
173
pll_writel(pll, val, PLL_CTRL4);
drivers/clk/pistachio/clk-pll.c
175
pll_lock(pll);
drivers/clk/pistachio/clk-pll.c
182
struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
drivers/clk/pistachio/clk-pll.c
185
val = pll_readl(pll, PLL_CTRL3);
drivers/clk/pistachio/clk-pll.c
187
pll_writel(pll, val, PLL_CTRL3);
drivers/clk/pistachio/clk-pll.c
192
struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
drivers/clk/pistachio/clk-pll.c
194
return !(pll_readl(pll, PLL_CTRL3) & PLL_FRAC_CTRL3_PD);
drivers/clk/pistachio/clk-pll.c
200
struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
drivers/clk/pistachio/clk-pll.c
209
params = pll_get_params(pll, parent_rate, rate);
drivers/clk/pistachio/clk-pll.c
230
val = pll_readl(pll, PLL_CTRL1);
drivers/clk/pistachio/clk-pll.c
235
pll_writel(pll, val, PLL_CTRL1);
drivers/clk/pistachio/clk-pll.c
237
val = pll_readl(pll, PLL_CTRL2);
drivers/clk/pistachio/clk-pll.c
259
pll_writel(pll, val, PLL_CTRL2);
drivers/clk/pistachio/clk-pll.c
268
pll_lock(pll);
drivers/clk/pistachio/clk-pll.c
276
struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
drivers/clk/pistachio/clk-pll.c
279
val = pll_readl(pll, PLL_CTRL1);
drivers/clk/pistachio/clk-pll.c
283
val = pll_readl(pll, PLL_CTRL2);
drivers/clk/pistachio/clk-pll.c
320
struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
drivers/clk/pistachio/clk-pll.c
323
val = pll_readl(pll, PLL_CTRL1);
drivers/clk/pistachio/clk-pll.c
326
pll_writel(pll, val, PLL_CTRL1);
drivers/clk/pistachio/clk-pll.c
328
val = pll_readl(pll, PLL_CTRL2);
drivers/clk/pistachio/clk-pll.c
330
pll_writel(pll, val, PLL_CTRL2);
drivers/clk/pistachio/clk-pll.c
332
pll_lock(pll);
drivers/clk/pistachio/clk-pll.c
339
struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
drivers/clk/pistachio/clk-pll.c
342
val = pll_readl(pll, PLL_CTRL1);
drivers/clk/pistachio/clk-pll.c
344
pll_writel(pll, val, PLL_CTRL1);
drivers/clk/pistachio/clk-pll.c
349
struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
drivers/clk/pistachio/clk-pll.c
351
return !(pll_readl(pll, PLL_CTRL1) & PLL_INT_CTRL1_PD);
drivers/clk/pistachio/clk-pll.c
357
struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
drivers/clk/pistachio/clk-pll.c
366
params = pll_get_params(pll, parent_rate, rate);
drivers/clk/pistachio/clk-pll.c
383
val = pll_readl(pll, PLL_CTRL1);
drivers/clk/pistachio/clk-pll.c
405
pll_writel(pll, val, PLL_CTRL1);
drivers/clk/pistachio/clk-pll.c
408
pll_lock(pll);
drivers/clk/pistachio/clk-pll.c
416
struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
drivers/clk/pistachio/clk-pll.c
420
val = pll_readl(pll, PLL_CTRL1);
drivers/clk/pistachio/clk-pll.c
456
struct pistachio_clk_pll *pll;
drivers/clk/pistachio/clk-pll.c
460
pll = kzalloc_obj(*pll);
drivers/clk/pistachio/clk-pll.c
461
if (!pll)
drivers/clk/pistachio/clk-pll.c
484
kfree(pll);
drivers/clk/pistachio/clk-pll.c
488
pll->hw.init = &init;
drivers/clk/pistachio/clk-pll.c
489
pll->base = base;
drivers/clk/pistachio/clk-pll.c
490
pll->rates = rates;
drivers/clk/pistachio/clk-pll.c
491
pll->nr_rates = nr_rates;
drivers/clk/pistachio/clk-pll.c
493
clk = clk_register(NULL, &pll->hw);
drivers/clk/pistachio/clk-pll.c
495
kfree(pll);
drivers/clk/pistachio/clk-pll.c
501
struct pistachio_pll *pll,
drivers/clk/pistachio/clk-pll.c
508
clk = pll_register(pll[i].name, pll[i].parent,
drivers/clk/pistachio/clk-pll.c
509
0, p->base + pll[i].reg_base,
drivers/clk/pistachio/clk-pll.c
510
pll[i].type, pll[i].rates,
drivers/clk/pistachio/clk-pll.c
511
pll[i].nr_rates);
drivers/clk/pistachio/clk-pll.c
512
p->clk_data.clks[pll[i].id] = clk;
drivers/clk/pistachio/clk-pll.c
78
static inline u32 pll_readl(struct pistachio_clk_pll *pll, u32 reg)
drivers/clk/pistachio/clk-pll.c
80
return readl(pll->base + reg);
drivers/clk/pistachio/clk-pll.c
83
static inline void pll_writel(struct pistachio_clk_pll *pll, u32 val, u32 reg)
drivers/clk/pistachio/clk-pll.c
85
writel(val, pll->base + reg);
drivers/clk/pistachio/clk-pll.c
88
static inline void pll_lock(struct pistachio_clk_pll *pll)
drivers/clk/pistachio/clk-pll.c
90
while (!(pll_readl(pll, PLL_STATUS) & PLL_STATUS_LOCK))
drivers/clk/pistachio/clk.h
165
struct pistachio_pll *pll,
drivers/clk/qcom/a53-pll.c
109
pll->l_reg = 0x04;
drivers/clk/qcom/a53-pll.c
110
pll->m_reg = 0x08;
drivers/clk/qcom/a53-pll.c
111
pll->n_reg = 0x0c;
drivers/clk/qcom/a53-pll.c
112
pll->config_reg = 0x14;
drivers/clk/qcom/a53-pll.c
113
pll->mode_reg = 0x00;
drivers/clk/qcom/a53-pll.c
114
pll->status_reg = 0x1c;
drivers/clk/qcom/a53-pll.c
115
pll->status_bit = 16;
drivers/clk/qcom/a53-pll.c
117
pll->freq_tbl = qcom_a53pll_get_freq_tbl(dev);
drivers/clk/qcom/a53-pll.c
118
if (!pll->freq_tbl) {
drivers/clk/qcom/a53-pll.c
120
pll->freq_tbl = a53pll_freq;
drivers/clk/qcom/a53-pll.c
134
pll->clkr.hw.init = &init;
drivers/clk/qcom/a53-pll.c
136
ret = devm_clk_register_regmap(dev, &pll->clkr);
drivers/clk/qcom/a53-pll.c
143
&pll->clkr.hw);
drivers/clk/qcom/a53-pll.c
92
struct clk_pll *pll;
drivers/clk/qcom/a53-pll.c
97
pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL);
drivers/clk/qcom/a53-pll.c
98
if (!pll)
drivers/clk/qcom/apss-ipq-pll.c
133
struct clk_alpha_pll *pll;
drivers/clk/qcom/apss-ipq-pll.c
139
.pll = &ipq_pll_stromer,
drivers/clk/qcom/apss-ipq-pll.c
145
.pll = &ipq_pll_stromer_plus,
drivers/clk/qcom/apss-ipq-pll.c
151
.pll = &ipq_pll_huayra,
drivers/clk/qcom/apss-ipq-pll.c
157
.pll = &ipq_pll_huayra,
drivers/clk/qcom/apss-ipq-pll.c
163
.pll = &ipq_pll_huayra,
drivers/clk/qcom/apss-ipq-pll.c
195
clk_alpha_pll_configure(data->pll, regmap, data->pll_config);
drivers/clk/qcom/apss-ipq-pll.c
198
clk_stromer_pll_configure(data->pll, regmap, data->pll_config);
drivers/clk/qcom/apss-ipq-pll.c
200
ret = devm_clk_register_regmap(dev, &data->pll->clkr);
drivers/clk/qcom/apss-ipq-pll.c
205
&data->pll->clkr.hw);
drivers/clk/qcom/clk-alpha-pll.c
1027
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
1032
regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
drivers/clk/qcom/clk-alpha-pll.c
1035
regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha);
drivers/clk/qcom/clk-alpha-pll.c
1048
regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
drivers/clk/qcom/clk-alpha-pll.c
1051
return wait_for_pll_enable_lock(pll);
drivers/clk/qcom/clk-alpha-pll.c
1054
regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
drivers/clk/qcom/clk-alpha-pll.c
1055
regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
drivers/clk/qcom/clk-alpha-pll.c
1058
regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
drivers/clk/qcom/clk-alpha-pll.c
1061
regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
drivers/clk/qcom/clk-alpha-pll.c
1078
static int trion_pll_is_enabled(struct clk_alpha_pll *pll,
drivers/clk/qcom/clk-alpha-pll.c
1084
ret = regmap_read(regmap, PLL_MODE(pll), &mode_val);
drivers/clk/qcom/clk-alpha-pll.c
1085
ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_val);
drivers/clk/qcom/clk-alpha-pll.c
1094
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
1096
return trion_pll_is_enabled(pll, pll->clkr.regmap);
drivers/clk/qcom/clk-alpha-pll.c
1101
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
1102
struct regmap *regmap = pll->clkr.regmap;
drivers/clk/qcom/clk-alpha-pll.c
1106
ret = regmap_read(regmap, PLL_MODE(pll), &val);
drivers/clk/qcom/clk-alpha-pll.c
1115
return wait_for_pll_enable_active(pll);
drivers/clk/qcom/clk-alpha-pll.c
1119
regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
drivers/clk/qcom/clk-alpha-pll.c
1121
ret = wait_for_pll_enable_lock(pll);
drivers/clk/qcom/clk-alpha-pll.c
1126
ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
drivers/clk/qcom/clk-alpha-pll.c
1132
return regmap_update_bits(regmap, PLL_MODE(pll),
drivers/clk/qcom/clk-alpha-pll.c
1138
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
1139
struct regmap *regmap = pll->clkr.regmap;
drivers/clk/qcom/clk-alpha-pll.c
1143
ret = regmap_read(regmap, PLL_MODE(pll), &val);
drivers/clk/qcom/clk-alpha-pll.c
1154
ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
drivers/clk/qcom/clk-alpha-pll.c
1159
ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
drivers/clk/qcom/clk-alpha-pll.c
1165
regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
drivers/clk/qcom/clk-alpha-pll.c
1166
regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
drivers/clk/qcom/clk-alpha-pll.c
1172
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
1173
u32 l, frac, alpha_width = pll_alpha_width(pll);
drivers/clk/qcom/clk-alpha-pll.c
1175
if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l))
drivers/clk/qcom/clk-alpha-pll.c
1178
if (regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac))
drivers/clk/qcom/clk-alpha-pll.c
1234
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
drivers/clk/qcom/clk-alpha-pll.c
1237
if (regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl))
drivers/clk/qcom/clk-alpha-pll.c
1241
ctl &= PLL_POST_DIV_MASK(pll);
drivers/clk/qcom/clk-alpha-pll.c
1265
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
drivers/clk/qcom/clk-alpha-pll.c
1268
if (pll->width == 2)
drivers/clk/qcom/clk-alpha-pll.c
1273
return divider_determine_rate(hw, req, table, pll->width,
drivers/clk/qcom/clk-alpha-pll.c
1280
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
drivers/clk/qcom/clk-alpha-pll.c
1283
regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
drivers/clk/qcom/clk-alpha-pll.c
1286
ctl &= BIT(pll->width) - 1;
drivers/clk/qcom/clk-alpha-pll.c
1301
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
drivers/clk/qcom/clk-alpha-pll.c
1307
return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
drivers/clk/qcom/clk-alpha-pll.c
1308
PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
drivers/clk/qcom/clk-alpha-pll.c
1325
void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
drivers/clk/qcom/clk-alpha-pll.c
1330
clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
drivers/clk/qcom/clk-alpha-pll.c
1331
clk_alpha_pll_write_config(regmap, PLL_FRAC(pll), config->alpha);
drivers/clk/qcom/clk-alpha-pll.c
1332
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
drivers/clk/qcom/clk-alpha-pll.c
1334
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
drivers/clk/qcom/clk-alpha-pll.c
1336
clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
drivers/clk/qcom/clk-alpha-pll.c
1338
clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll),
drivers/clk/qcom/clk-alpha-pll.c
1340
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
drivers/clk/qcom/clk-alpha-pll.c
1342
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
drivers/clk/qcom/clk-alpha-pll.c
1348
regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
drivers/clk/qcom/clk-alpha-pll.c
1351
if (pll->flags & SUPPORTS_FSM_LEGACY_MODE)
drivers/clk/qcom/clk-alpha-pll.c
1352
regmap_update_bits(regmap, PLL_MODE(pll), PLL_FSM_LEGACY_MODE,
drivers/clk/qcom/clk-alpha-pll.c
1355
regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
drivers/clk/qcom/clk-alpha-pll.c
1358
regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
drivers/clk/qcom/clk-alpha-pll.c
1365
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
1367
struct regmap *regmap = pll->clkr.regmap;
drivers/clk/qcom/clk-alpha-pll.c
1369
ret = regmap_read(regmap, PLL_MODE(pll), &val);
drivers/clk/qcom/clk-alpha-pll.c
1378
return wait_for_pll_enable_active(pll);
drivers/clk/qcom/clk-alpha-pll.c
1381
ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val);
drivers/clk/qcom/clk-alpha-pll.c
1389
ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
drivers/clk/qcom/clk-alpha-pll.c
1393
ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
drivers/clk/qcom/clk-alpha-pll.c
1397
ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N,
drivers/clk/qcom/clk-alpha-pll.c
1402
ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
drivers/clk/qcom/clk-alpha-pll.c
1406
ret = wait_for_pll_enable_lock(pll);
drivers/clk/qcom/clk-alpha-pll.c
1410
ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
drivers/clk/qcom/clk-alpha-pll.c
1415
return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL,
drivers/clk/qcom/clk-alpha-pll.c
1422
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
1424
struct regmap *regmap = pll->clkr.regmap;
drivers/clk/qcom/clk-alpha-pll.c
1426
ret = regmap_read(regmap, PLL_MODE(pll), &val);
drivers/clk/qcom/clk-alpha-pll.c
1436
ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
drivers/clk/qcom/clk-alpha-pll.c
1441
ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
drivers/clk/qcom/clk-alpha-pll.c
1446
regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
drivers/clk/qcom/clk-alpha-pll.c
1452
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
1453
u32 l, frac, alpha_width = pll_alpha_width(pll);
drivers/clk/qcom/clk-alpha-pll.c
1455
if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l))
drivers/clk/qcom/clk-alpha-pll.c
1458
if (regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac))
drivers/clk/qcom/clk-alpha-pll.c
1485
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
1486
u32 l, alpha_width = pll_alpha_width(pll);
drivers/clk/qcom/clk-alpha-pll.c
1497
regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
drivers/clk/qcom/clk-alpha-pll.c
1498
regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a);
drivers/clk/qcom/clk-alpha-pll.c
1500
return __clk_alpha_pll_update_latch(pll);
drivers/clk/qcom/clk-alpha-pll.c
1505
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
1509
u32 cal_l, val, alpha_width = pll_alpha_width(pll);
drivers/clk/qcom/clk-alpha-pll.c
1515
ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
drivers/clk/qcom/clk-alpha-pll.c
1523
vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw));
drivers/clk/qcom/clk-alpha-pll.c
1529
cal_freq = DIV_ROUND_CLOSEST((pll->vco_table[0].min_freq +
drivers/clk/qcom/clk-alpha-pll.c
1530
pll->vco_table[0].max_freq) * 54, 100);
drivers/clk/qcom/clk-alpha-pll.c
1544
regmap_write(pll->clkr.regmap, PLL_CAL_L_VAL(pll), cal_l);
drivers/clk/qcom/clk-alpha-pll.c
1581
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
drivers/clk/qcom/clk-alpha-pll.c
1585
ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
drivers/clk/qcom/clk-alpha-pll.c
1589
val >>= pll->post_div_shift;
drivers/clk/qcom/clk-alpha-pll.c
1590
val &= BIT(pll->width) - 1;
drivers/clk/qcom/clk-alpha-pll.c
1592
for (i = 0; i < pll->num_post_div; i++) {
drivers/clk/qcom/clk-alpha-pll.c
1593
if (pll->post_div_table[i].val == val) {
drivers/clk/qcom/clk-alpha-pll.c
1594
div = pll->post_div_table[i].div;
drivers/clk/qcom/clk-alpha-pll.c
1605
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
drivers/clk/qcom/clk-alpha-pll.c
1606
struct regmap *regmap = pll->clkr.regmap;
drivers/clk/qcom/clk-alpha-pll.c
1609
if (regmap_read(regmap, PLL_USER_CTL(pll), &val))
drivers/clk/qcom/clk-alpha-pll.c
1612
val >>= pll->post_div_shift;
drivers/clk/qcom/clk-alpha-pll.c
1613
val &= PLL_POST_DIV_MASK(pll);
drivers/clk/qcom/clk-alpha-pll.c
1615
for (i = 0; i < pll->num_post_div; i++) {
drivers/clk/qcom/clk-alpha-pll.c
1616
if (pll->post_div_table[i].val == val) {
drivers/clk/qcom/clk-alpha-pll.c
1617
div = pll->post_div_table[i].div;
drivers/clk/qcom/clk-alpha-pll.c
1628
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
drivers/clk/qcom/clk-alpha-pll.c
1630
return divider_determine_rate(hw, req, pll->post_div_table, pll->width,
drivers/clk/qcom/clk-alpha-pll.c
1638
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
drivers/clk/qcom/clk-alpha-pll.c
1639
struct regmap *regmap = pll->clkr.regmap;
drivers/clk/qcom/clk-alpha-pll.c
1643
for (i = 0; i < pll->num_post_div; i++) {
drivers/clk/qcom/clk-alpha-pll.c
1644
if (pll->post_div_table[i].div == div) {
drivers/clk/qcom/clk-alpha-pll.c
1645
val = pll->post_div_table[i].val;
drivers/clk/qcom/clk-alpha-pll.c
1650
return regmap_update_bits(regmap, PLL_USER_CTL(pll),
drivers/clk/qcom/clk-alpha-pll.c
1651
PLL_POST_DIV_MASK(pll) << pll->post_div_shift,
drivers/clk/qcom/clk-alpha-pll.c
1652
val << pll->post_div_shift);
drivers/clk/qcom/clk-alpha-pll.c
1665
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
drivers/clk/qcom/clk-alpha-pll.c
1667
return divider_determine_rate(hw, req, pll->post_div_table, pll->width,
drivers/clk/qcom/clk-alpha-pll.c
1674
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
drivers/clk/qcom/clk-alpha-pll.c
1681
ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
drivers/clk/qcom/clk-alpha-pll.c
1689
for (i = 0; i < pll->num_post_div; i++) {
drivers/clk/qcom/clk-alpha-pll.c
1690
if (pll->post_div_table[i].div == div) {
drivers/clk/qcom/clk-alpha-pll.c
1691
val = pll->post_div_table[i].val;
drivers/clk/qcom/clk-alpha-pll.c
1696
return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
drivers/clk/qcom/clk-alpha-pll.c
1697
(BIT(pll->width) - 1) << pll->post_div_shift,
drivers/clk/qcom/clk-alpha-pll.c
1698
val << pll->post_div_shift);
drivers/clk/qcom/clk-alpha-pll.c
1715
void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
drivers/clk/qcom/clk-alpha-pll.c
1722
if (trion_pll_is_enabled(pll, regmap)) {
drivers/clk/qcom/clk-alpha-pll.c
1727
clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
drivers/clk/qcom/clk-alpha-pll.c
1728
regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL);
drivers/clk/qcom/clk-alpha-pll.c
1729
clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
drivers/clk/qcom/clk-alpha-pll.c
1730
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
drivers/clk/qcom/clk-alpha-pll.c
1732
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
drivers/clk/qcom/clk-alpha-pll.c
1734
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll),
drivers/clk/qcom/clk-alpha-pll.c
1736
clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
drivers/clk/qcom/clk-alpha-pll.c
1738
clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll),
drivers/clk/qcom/clk-alpha-pll.c
1740
clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll),
drivers/clk/qcom/clk-alpha-pll.c
1742
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
drivers/clk/qcom/clk-alpha-pll.c
1744
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
drivers/clk/qcom/clk-alpha-pll.c
1746
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll),
drivers/clk/qcom/clk-alpha-pll.c
1749
regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
drivers/clk/qcom/clk-alpha-pll.c
1753
regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
drivers/clk/qcom/clk-alpha-pll.c
1756
regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
drivers/clk/qcom/clk-alpha-pll.c
1759
regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
drivers/clk/qcom/clk-alpha-pll.c
1769
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
1774
regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val);
drivers/clk/qcom/clk-alpha-pll.c
1799
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
1801
u32 val, l, alpha_width = pll_alpha_width(pll);
drivers/clk/qcom/clk-alpha-pll.c
1811
regmap_update_bits(pll->clkr.regmap, PLL_L_VAL(pll), LUCID_EVO_PLL_L_VAL_MASK, l);
drivers/clk/qcom/clk-alpha-pll.c
1812
regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
drivers/clk/qcom/clk-alpha-pll.c
1815
ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, latch_bit);
drivers/clk/qcom/clk-alpha-pll.c
1821
regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
drivers/clk/qcom/clk-alpha-pll.c
1828
ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, 0);
drivers/clk/qcom/clk-alpha-pll.c
1833
ret = wait_for_pll_enable_lock(pll);
drivers/clk/qcom/clk-alpha-pll.c
1878
void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
drivers/clk/qcom/clk-alpha-pll.c
1881
clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
drivers/clk/qcom/clk-alpha-pll.c
1882
clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
drivers/clk/qcom/clk-alpha-pll.c
1883
clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
drivers/clk/qcom/clk-alpha-pll.c
1885
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
drivers/clk/qcom/clk-alpha-pll.c
1887
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
drivers/clk/qcom/clk-alpha-pll.c
1889
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
drivers/clk/qcom/clk-alpha-pll.c
1891
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
drivers/clk/qcom/clk-alpha-pll.c
1899
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
1900
u32 l, alpha_width = pll_alpha_width(pll);
drivers/clk/qcom/clk-alpha-pll.c
1911
regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
drivers/clk/qcom/clk-alpha-pll.c
1912
regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
drivers/clk/qcom/clk-alpha-pll.c
1915
return wait_for_pll_enable_lock(pll);
drivers/clk/qcom/clk-alpha-pll.c
1937
void clk_lucid_5lpe_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
drivers/clk/qcom/clk-alpha-pll.c
1944
if (trion_pll_is_enabled(pll, regmap)) {
drivers/clk/qcom/clk-alpha-pll.c
1949
clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
drivers/clk/qcom/clk-alpha-pll.c
1950
regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL);
drivers/clk/qcom/clk-alpha-pll.c
1951
clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
drivers/clk/qcom/clk-alpha-pll.c
1952
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
drivers/clk/qcom/clk-alpha-pll.c
1954
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
drivers/clk/qcom/clk-alpha-pll.c
1956
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll),
drivers/clk/qcom/clk-alpha-pll.c
1958
clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
drivers/clk/qcom/clk-alpha-pll.c
1960
clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll),
drivers/clk/qcom/clk-alpha-pll.c
1962
clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll),
drivers/clk/qcom/clk-alpha-pll.c
1964
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
drivers/clk/qcom/clk-alpha-pll.c
1966
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
drivers/clk/qcom/clk-alpha-pll.c
1968
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll),
drivers/clk/qcom/clk-alpha-pll.c
1972
regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
drivers/clk/qcom/clk-alpha-pll.c
1975
regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
drivers/clk/qcom/clk-alpha-pll.c
1978
regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
drivers/clk/qcom/clk-alpha-pll.c
1984
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
1988
ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
drivers/clk/qcom/clk-alpha-pll.c
1997
return wait_for_pll_enable_lock(pll);
drivers/clk/qcom/clk-alpha-pll.c
2001
if (trion_pll_is_enabled(pll, pll->clkr.regmap))
drivers/clk/qcom/clk-alpha-pll.c
2004
ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
drivers/clk/qcom/clk-alpha-pll.c
2008
regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN);
drivers/clk/qcom/clk-alpha-pll.c
2010
ret = wait_for_pll_enable_lock(pll);
drivers/clk/qcom/clk-alpha-pll.c
2015
ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK);
drivers/clk/qcom/clk-alpha-pll.c
2020
return regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
drivers/clk/qcom/clk-alpha-pll.c
2025
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
2029
ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
drivers/clk/qcom/clk-alpha-pll.c
2040
ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
drivers/clk/qcom/clk-alpha-pll.c
2045
ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
drivers/clk/qcom/clk-alpha-pll.c
2050
regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY);
drivers/clk/qcom/clk-alpha-pll.c
2059
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
2065
regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
drivers/clk/qcom/clk-alpha-pll.c
2094
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
drivers/clk/qcom/clk-alpha-pll.c
2095
struct regmap *regmap = pll->clkr.regmap;
drivers/clk/qcom/clk-alpha-pll.c
2103
ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
drivers/clk/qcom/clk-alpha-pll.c
2110
if (!pll->post_div_table) {
drivers/clk/qcom/clk-alpha-pll.c
2112
clk_hw_get_name(&pll->clkr.hw));
drivers/clk/qcom/clk-alpha-pll.c
2117
for (i = 0; i < pll->num_post_div; i++) {
drivers/clk/qcom/clk-alpha-pll.c
2118
if (pll->post_div_table[i].div == div) {
drivers/clk/qcom/clk-alpha-pll.c
2119
val = pll->post_div_table[i].val;
drivers/clk/qcom/clk-alpha-pll.c
2124
mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift);
drivers/clk/qcom/clk-alpha-pll.c
2125
return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
drivers/clk/qcom/clk-alpha-pll.c
2126
mask, val << pll->post_div_shift);
drivers/clk/qcom/clk-alpha-pll.c
2162
void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
drivers/clk/qcom/clk-alpha-pll.c
2165
clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
drivers/clk/qcom/clk-alpha-pll.c
2166
clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
drivers/clk/qcom/clk-alpha-pll.c
2167
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
drivers/clk/qcom/clk-alpha-pll.c
2168
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
drivers/clk/qcom/clk-alpha-pll.c
2169
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
drivers/clk/qcom/clk-alpha-pll.c
2170
clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
drivers/clk/qcom/clk-alpha-pll.c
2171
clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
drivers/clk/qcom/clk-alpha-pll.c
2172
clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val);
drivers/clk/qcom/clk-alpha-pll.c
2173
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
drivers/clk/qcom/clk-alpha-pll.c
2174
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
drivers/clk/qcom/clk-alpha-pll.c
2175
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
drivers/clk/qcom/clk-alpha-pll.c
2177
regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, 0);
drivers/clk/qcom/clk-alpha-pll.c
2180
regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
drivers/clk/qcom/clk-alpha-pll.c
2183
regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
drivers/clk/qcom/clk-alpha-pll.c
2186
regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
drivers/clk/qcom/clk-alpha-pll.c
2192
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
2193
struct regmap *regmap = pll->clkr.regmap;
drivers/clk/qcom/clk-alpha-pll.c
2197
regmap_read(regmap, PLL_MODE(pll), &val);
drivers/clk/qcom/clk-alpha-pll.c
2204
return wait_for_pll_enable_active(pll);
drivers/clk/qcom/clk-alpha-pll.c
2208
regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL);
drivers/clk/qcom/clk-alpha-pll.c
2216
regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
drivers/clk/qcom/clk-alpha-pll.c
2219
regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
drivers/clk/qcom/clk-alpha-pll.c
2221
regmap_read(regmap, PLL_TEST_CTL(pll), &val);
drivers/clk/qcom/clk-alpha-pll.c
2225
ret = wait_for_zonda_pll_freq_lock(pll);
drivers/clk/qcom/clk-alpha-pll.c
2227
ret = wait_for_pll_enable_lock(pll);
drivers/clk/qcom/clk-alpha-pll.c
2232
regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK);
drivers/clk/qcom/clk-alpha-pll.c
2235
regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
drivers/clk/qcom/clk-alpha-pll.c
2242
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
2243
struct regmap *regmap = pll->clkr.regmap;
drivers/clk/qcom/clk-alpha-pll.c
2246
regmap_read(regmap, PLL_MODE(pll), &val);
drivers/clk/qcom/clk-alpha-pll.c
2255
regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
drivers/clk/qcom/clk-alpha-pll.c
2258
regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, 0);
drivers/clk/qcom/clk-alpha-pll.c
2261
regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0);
drivers/clk/qcom/clk-alpha-pll.c
2264
regmap_write(regmap, PLL_OPMODE(pll), 0x0);
drivers/clk/qcom/clk-alpha-pll.c
2280
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
2283
u32 l, alpha_width = pll_alpha_width(pll);
drivers/clk/qcom/clk-alpha-pll.c
2296
regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
drivers/clk/qcom/clk-alpha-pll.c
2297
regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
drivers/clk/qcom/clk-alpha-pll.c
2306
regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val);
drivers/clk/qcom/clk-alpha-pll.c
2310
ret = wait_for_zonda_pll_freq_lock(pll);
drivers/clk/qcom/clk-alpha-pll.c
2312
ret = wait_for_pll_enable_lock(pll);
drivers/clk/qcom/clk-alpha-pll.c
2331
void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
drivers/clk/qcom/clk-alpha-pll.c
2340
if (trion_pll_is_enabled(pll, regmap)) {
drivers/clk/qcom/clk-alpha-pll.c
2350
clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval);
drivers/clk/qcom/clk-alpha-pll.c
2351
clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
drivers/clk/qcom/clk-alpha-pll.c
2352
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
drivers/clk/qcom/clk-alpha-pll.c
2353
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
drivers/clk/qcom/clk-alpha-pll.c
2354
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
drivers/clk/qcom/clk-alpha-pll.c
2355
clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
drivers/clk/qcom/clk-alpha-pll.c
2356
clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
drivers/clk/qcom/clk-alpha-pll.c
2357
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
drivers/clk/qcom/clk-alpha-pll.c
2358
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
drivers/clk/qcom/clk-alpha-pll.c
2359
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
drivers/clk/qcom/clk-alpha-pll.c
2360
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val);
drivers/clk/qcom/clk-alpha-pll.c
2363
regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
drivers/clk/qcom/clk-alpha-pll.c
2366
regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
drivers/clk/qcom/clk-alpha-pll.c
2367
regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
drivers/clk/qcom/clk-alpha-pll.c
2371
void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
drivers/clk/qcom/clk-alpha-pll.c
2378
clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval);
drivers/clk/qcom/clk-alpha-pll.c
2379
clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
drivers/clk/qcom/clk-alpha-pll.c
2380
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
drivers/clk/qcom/clk-alpha-pll.c
2381
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
drivers/clk/qcom/clk-alpha-pll.c
2382
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
drivers/clk/qcom/clk-alpha-pll.c
2383
clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
drivers/clk/qcom/clk-alpha-pll.c
2384
clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
drivers/clk/qcom/clk-alpha-pll.c
2385
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
drivers/clk/qcom/clk-alpha-pll.c
2386
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
drivers/clk/qcom/clk-alpha-pll.c
2387
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
drivers/clk/qcom/clk-alpha-pll.c
2388
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val);
drivers/clk/qcom/clk-alpha-pll.c
2391
regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
drivers/clk/qcom/clk-alpha-pll.c
2394
regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
drivers/clk/qcom/clk-alpha-pll.c
2395
regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
drivers/clk/qcom/clk-alpha-pll.c
2401
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
2402
struct regmap *regmap = pll->clkr.regmap;
drivers/clk/qcom/clk-alpha-pll.c
2406
ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
drivers/clk/qcom/clk-alpha-pll.c
2415
return wait_for_pll_enable_lock(pll);
drivers/clk/qcom/clk-alpha-pll.c
2419
if (trion_pll_is_enabled(pll, regmap))
drivers/clk/qcom/clk-alpha-pll.c
2422
ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
drivers/clk/qcom/clk-alpha-pll.c
2427
regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
drivers/clk/qcom/clk-alpha-pll.c
2429
ret = wait_for_pll_enable_lock(pll);
drivers/clk/qcom/clk-alpha-pll.c
2434
ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK);
drivers/clk/qcom/clk-alpha-pll.c
2439
ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
drivers/clk/qcom/clk-alpha-pll.c
2450
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
2451
struct regmap *regmap = pll->clkr.regmap;
drivers/clk/qcom/clk-alpha-pll.c
2455
ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
drivers/clk/qcom/clk-alpha-pll.c
2466
ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
drivers/clk/qcom/clk-alpha-pll.c
2471
ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
drivers/clk/qcom/clk-alpha-pll.c
2476
regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
drivers/clk/qcom/clk-alpha-pll.c
2479
regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 0);
drivers/clk/qcom/clk-alpha-pll.c
2484
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
2490
regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
drivers/clk/qcom/clk-alpha-pll.c
2530
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
2531
struct regmap *regmap = pll->clkr.regmap;
drivers/clk/qcom/clk-alpha-pll.c
2534
if (regmap_read(regmap, PLL_L_VAL(pll), &l))
drivers/clk/qcom/clk-alpha-pll.c
2538
if (regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac))
drivers/clk/qcom/clk-alpha-pll.c
2541
return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll));
drivers/clk/qcom/clk-alpha-pll.c
2590
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
2591
struct regmap *regmap = pll->clkr.regmap;
drivers/clk/qcom/clk-alpha-pll.c
2595
regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
drivers/clk/qcom/clk-alpha-pll.c
2596
regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
drivers/clk/qcom/clk-alpha-pll.c
2597
regmap_update_bits(regmap, PLL_MODE(pll), PONGO_XO_PRESENT, PONGO_XO_PRESENT);
drivers/clk/qcom/clk-alpha-pll.c
2600
pll->clkr.regmap = regmap;
drivers/clk/qcom/clk-alpha-pll.c
2601
ret = wait_for_pll_enable_lock(pll);
drivers/clk/qcom/clk-alpha-pll.c
2604
regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
drivers/clk/qcom/clk-alpha-pll.c
2609
regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
drivers/clk/qcom/clk-alpha-pll.c
2612
regmap_update_bits(regmap, PLL_MODE(pll), PONGO_CLOCK_SELECT,
drivers/clk/qcom/clk-alpha-pll.c
2620
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
2621
struct regmap *regmap = pll->clkr.regmap;
drivers/clk/qcom/clk-alpha-pll.c
2625
if (trion_pll_is_enabled(pll, regmap))
drivers/clk/qcom/clk-alpha-pll.c
2628
ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
drivers/clk/qcom/clk-alpha-pll.c
2633
regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
drivers/clk/qcom/clk-alpha-pll.c
2635
ret = wait_for_pll_enable_lock(pll);
drivers/clk/qcom/clk-alpha-pll.c
2640
ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
drivers/clk/qcom/clk-alpha-pll.c
2652
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
2653
struct regmap *regmap = pll->clkr.regmap;
drivers/clk/qcom/clk-alpha-pll.c
2657
ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
drivers/clk/qcom/clk-alpha-pll.c
2662
regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
drivers/clk/qcom/clk-alpha-pll.c
2668
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
2669
struct regmap *regmap = pll->clkr.regmap;
drivers/clk/qcom/clk-alpha-pll.c
2672
if (regmap_read(regmap, PLL_L_VAL(pll), &l))
drivers/clk/qcom/clk-alpha-pll.c
2677
return alpha_pll_calc_rate(parent_rate, l, 0, pll_alpha_width(pll));
drivers/clk/qcom/clk-alpha-pll.c
2688
void clk_pongo_elu_pll_configure(struct clk_alpha_pll *pll,
drivers/clk/qcom/clk-alpha-pll.c
2694
regmap_update_bits(regmap, PLL_USER_CTL(pll), PONGO_PLL_OUT_MASK,
drivers/clk/qcom/clk-alpha-pll.c
2697
if (trion_pll_is_enabled(pll, regmap))
drivers/clk/qcom/clk-alpha-pll.c
2700
if (regmap_read(regmap, PLL_L_VAL(pll), &val))
drivers/clk/qcom/clk-alpha-pll.c
2706
clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
drivers/clk/qcom/clk-alpha-pll.c
2707
clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
drivers/clk/qcom/clk-alpha-pll.c
2708
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
drivers/clk/qcom/clk-alpha-pll.c
2709
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
drivers/clk/qcom/clk-alpha-pll.c
2710
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
drivers/clk/qcom/clk-alpha-pll.c
2711
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U2(pll), config->config_ctl_hi2_val);
drivers/clk/qcom/clk-alpha-pll.c
2712
clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
drivers/clk/qcom/clk-alpha-pll.c
2714
clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
drivers/clk/qcom/clk-alpha-pll.c
2715
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
drivers/clk/qcom/clk-alpha-pll.c
2716
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
drivers/clk/qcom/clk-alpha-pll.c
2717
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
drivers/clk/qcom/clk-alpha-pll.c
2718
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val);
drivers/clk/qcom/clk-alpha-pll.c
2719
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U3(pll), config->test_ctl_hi3_val);
drivers/clk/qcom/clk-alpha-pll.c
2722
regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
drivers/clk/qcom/clk-alpha-pll.c
2726
void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
drivers/clk/qcom/clk-alpha-pll.c
2729
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
drivers/clk/qcom/clk-alpha-pll.c
2730
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
drivers/clk/qcom/clk-alpha-pll.c
2731
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
drivers/clk/qcom/clk-alpha-pll.c
2732
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
drivers/clk/qcom/clk-alpha-pll.c
2733
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
drivers/clk/qcom/clk-alpha-pll.c
2734
clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
drivers/clk/qcom/clk-alpha-pll.c
2735
clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
drivers/clk/qcom/clk-alpha-pll.c
2736
clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
drivers/clk/qcom/clk-alpha-pll.c
2738
regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
drivers/clk/qcom/clk-alpha-pll.c
2740
regmap_update_bits(regmap, PLL_MODE(pll),
drivers/clk/qcom/clk-alpha-pll.c
2749
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
2752
if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l))
drivers/clk/qcom/clk-alpha-pll.c
2761
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
2768
if (!pll->vco_table || alpha_pll_find_vco(pll, req->rate))
drivers/clk/qcom/clk-alpha-pll.c
2771
min_freq = pll->vco_table[0].min_freq;
drivers/clk/qcom/clk-alpha-pll.c
2772
max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
drivers/clk/qcom/clk-alpha-pll.c
2788
void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
drivers/clk/qcom/clk-alpha-pll.c
2793
regmap_write(regmap, PLL_L_VAL(pll), config->l);
drivers/clk/qcom/clk-alpha-pll.c
2794
regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
drivers/clk/qcom/clk-alpha-pll.c
2795
regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
drivers/clk/qcom/clk-alpha-pll.c
2797
if (pll_has_64bit_config(pll))
drivers/clk/qcom/clk-alpha-pll.c
2798
regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
drivers/clk/qcom/clk-alpha-pll.c
2801
if (pll_alpha_width(pll) > 32)
drivers/clk/qcom/clk-alpha-pll.c
2802
regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi);
drivers/clk/qcom/clk-alpha-pll.c
2824
regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
drivers/clk/qcom/clk-alpha-pll.c
2833
regmap_update_bits(regmap, PLL_USER_CTL_U(pll), mask_u, val_u);
drivers/clk/qcom/clk-alpha-pll.c
2834
regmap_write(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
drivers/clk/qcom/clk-alpha-pll.c
2835
regmap_write(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
drivers/clk/qcom/clk-alpha-pll.c
2837
if (pll->flags & SUPPORTS_FSM_MODE)
drivers/clk/qcom/clk-alpha-pll.c
2838
qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
drivers/clk/qcom/clk-alpha-pll.c
2857
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
2864
regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
drivers/clk/qcom/clk-alpha-pll.c
2867
regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
drivers/clk/qcom/clk-alpha-pll.c
2868
regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
drivers/clk/qcom/clk-alpha-pll.c
2871
regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
drivers/clk/qcom/clk-alpha-pll.c
2882
regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE,
drivers/clk/qcom/clk-alpha-pll.c
2885
ret = wait_for_pll_update(pll);
drivers/clk/qcom/clk-alpha-pll.c
2889
return wait_for_pll_enable_lock(pll);
drivers/clk/qcom/clk-alpha-pll.c
2906
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
2907
u32 l, alpha_width = pll_alpha_width(pll);
drivers/clk/qcom/clk-alpha-pll.c
2913
ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &pll_mode);
drivers/clk/qcom/clk-alpha-pll.c
2917
regmap_write(pll->clkr.regmap, PLL_MODE(pll), 0);
drivers/clk/qcom/clk-alpha-pll.c
2922
regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
drivers/clk/qcom/clk-alpha-pll.c
2927
regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
drivers/clk/qcom/clk-alpha-pll.c
2928
regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
drivers/clk/qcom/clk-alpha-pll.c
2931
regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
drivers/clk/qcom/clk-alpha-pll.c
2934
regmap_write(pll->clkr.regmap, PLL_MODE(pll), PLL_BYPASSNL);
drivers/clk/qcom/clk-alpha-pll.c
2938
regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N,
drivers/clk/qcom/clk-alpha-pll.c
2944
ret = wait_for_pll_enable_lock(pll);
drivers/clk/qcom/clk-alpha-pll.c
2952
regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL,
drivers/clk/qcom/clk-alpha-pll.c
2968
void clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
drivers/clk/qcom/clk-alpha-pll.c
2971
clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
drivers/clk/qcom/clk-alpha-pll.c
2972
clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
drivers/clk/qcom/clk-alpha-pll.c
2973
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
drivers/clk/qcom/clk-alpha-pll.c
2974
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
drivers/clk/qcom/clk-alpha-pll.c
2975
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
drivers/clk/qcom/clk-alpha-pll.c
2976
clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
drivers/clk/qcom/clk-alpha-pll.c
2977
clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
drivers/clk/qcom/clk-alpha-pll.c
2978
clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val);
drivers/clk/qcom/clk-alpha-pll.c
2979
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
drivers/clk/qcom/clk-alpha-pll.c
2980
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
drivers/clk/qcom/clk-alpha-pll.c
2981
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
drivers/clk/qcom/clk-alpha-pll.c
2984
regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
drivers/clk/qcom/clk-alpha-pll.c
2998
void qcom_clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap)
drivers/clk/qcom/clk-alpha-pll.c
3000
const struct clk_init_data *init = pll->clkr.hw.init;
drivers/clk/qcom/clk-alpha-pll.c
3002
switch (GET_PLL_TYPE(pll)) {
drivers/clk/qcom/clk-alpha-pll.c
3004
clk_lucid_ole_pll_configure(pll, regmap, pll->config);
drivers/clk/qcom/clk-alpha-pll.c
3007
clk_lucid_evo_pll_configure(pll, regmap, pll->config);
drivers/clk/qcom/clk-alpha-pll.c
3010
clk_taycan_elu_pll_configure(pll, regmap, pll->config);
drivers/clk/qcom/clk-alpha-pll.c
3014
clk_rivian_evo_pll_configure(pll, regmap, pll->config);
drivers/clk/qcom/clk-alpha-pll.c
3017
clk_trion_pll_configure(pll, regmap, pll->config);
drivers/clk/qcom/clk-alpha-pll.c
3020
clk_huayra_2290_pll_configure(pll, regmap, pll->config);
drivers/clk/qcom/clk-alpha-pll.c
3023
clk_fabia_pll_configure(pll, regmap, pll->config);
drivers/clk/qcom/clk-alpha-pll.c
3026
clk_agera_pll_configure(pll, regmap, pll->config);
drivers/clk/qcom/clk-alpha-pll.c
3029
clk_pongo_elu_pll_configure(pll, regmap, pll->config);
drivers/clk/qcom/clk-alpha-pll.c
3033
clk_zonda_pll_configure(pll, regmap, pll->config);
drivers/clk/qcom/clk-alpha-pll.c
3037
clk_stromer_pll_configure(pll, regmap, pll->config);
drivers/clk/qcom/clk-alpha-pll.c
3045
clk_alpha_pll_configure(pll, regmap, pll->config);
drivers/clk/qcom/clk-alpha-pll.c
3054
static int clk_alpha_pll_slew_update(struct clk_alpha_pll *pll)
drivers/clk/qcom/clk-alpha-pll.c
3059
regmap_set_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE);
drivers/clk/qcom/clk-alpha-pll.c
3060
regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
drivers/clk/qcom/clk-alpha-pll.c
3062
ret = wait_for_pll_update(pll);
drivers/clk/qcom/clk-alpha-pll.c
3071
return wait_for_pll_enable_lock(pll);
drivers/clk/qcom/clk-alpha-pll.c
3077
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
3089
curr_vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw));
drivers/clk/qcom/clk-alpha-pll.c
3095
vco = alpha_pll_find_vco(pll, freq_hz);
drivers/clk/qcom/clk-alpha-pll.c
3108
clk_alpha_pll_update_configs(pll, NULL, l, a, ALPHA_REG_BITWIDTH, false);
drivers/clk/qcom/clk-alpha-pll.c
3114
return clk_alpha_pll_slew_update(pll);
drivers/clk/qcom/clk-alpha-pll.c
3126
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
3140
vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw));
drivers/clk/qcom/clk-alpha-pll.c
3151
calibration_freq = (pll->vco_table[0].min_freq + pll->vco_table[0].max_freq) / 2;
drivers/clk/qcom/clk-alpha-pll.c
3160
clk_alpha_pll_update_configs(pll, vco, l, a, ALPHA_REG_BITWIDTH, false);
drivers/clk/qcom/clk-alpha-pll.c
3179
clk_alpha_pll_update_configs(pll, NULL, l, a, ALPHA_REG_BITWIDTH, true);
drivers/clk/qcom/clk-alpha-pll.c
3181
return clk_alpha_pll_slew_update(pll);
drivers/clk/qcom/clk-alpha-pll.c
396
static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
drivers/clk/qcom/clk-alpha-pll.c
402
const char *name = clk_hw_get_name(&pll->clkr.hw);
drivers/clk/qcom/clk-alpha-pll.c
404
ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
drivers/clk/qcom/clk-alpha-pll.c
410
ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
drivers/clk/qcom/clk-alpha-pll.c
425
#define wait_for_pll_enable_active(pll) \
drivers/clk/qcom/clk-alpha-pll.c
426
wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable")
drivers/clk/qcom/clk-alpha-pll.c
428
#define wait_for_pll_enable_lock(pll) \
drivers/clk/qcom/clk-alpha-pll.c
429
wait_for_pll(pll, PLL_LOCK_DET, 0, "enable")
drivers/clk/qcom/clk-alpha-pll.c
431
#define wait_for_zonda_pll_freq_lock(pll) \
drivers/clk/qcom/clk-alpha-pll.c
432
wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable")
drivers/clk/qcom/clk-alpha-pll.c
434
#define wait_for_pll_disable(pll) \
drivers/clk/qcom/clk-alpha-pll.c
435
wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable")
drivers/clk/qcom/clk-alpha-pll.c
437
#define wait_for_pll_offline(pll) \
drivers/clk/qcom/clk-alpha-pll.c
438
wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline")
drivers/clk/qcom/clk-alpha-pll.c
440
#define wait_for_pll_update(pll) \
drivers/clk/qcom/clk-alpha-pll.c
441
wait_for_pll(pll, PLL_UPDATE, 1, "update")
drivers/clk/qcom/clk-alpha-pll.c
443
#define wait_for_pll_update_ack_set(pll) \
drivers/clk/qcom/clk-alpha-pll.c
444
wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set")
drivers/clk/qcom/clk-alpha-pll.c
446
#define wait_for_pll_update_ack_clear(pll) \
drivers/clk/qcom/clk-alpha-pll.c
447
wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear")
drivers/clk/qcom/clk-alpha-pll.c
456
void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
drivers/clk/qcom/clk-alpha-pll.c
461
regmap_write(regmap, PLL_L_VAL(pll), config->l);
drivers/clk/qcom/clk-alpha-pll.c
462
regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
drivers/clk/qcom/clk-alpha-pll.c
463
regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
drivers/clk/qcom/clk-alpha-pll.c
465
if (pll_has_64bit_config(pll))
drivers/clk/qcom/clk-alpha-pll.c
466
regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
drivers/clk/qcom/clk-alpha-pll.c
469
if (pll_alpha_width(pll) > 32)
drivers/clk/qcom/clk-alpha-pll.c
470
regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi);
drivers/clk/qcom/clk-alpha-pll.c
492
regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
drivers/clk/qcom/clk-alpha-pll.c
495
regmap_update_bits(regmap, PLL_TEST_CTL(pll),
drivers/clk/qcom/clk-alpha-pll.c
499
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
drivers/clk/qcom/clk-alpha-pll.c
503
regmap_update_bits(regmap, PLL_TEST_CTL_U(pll),
drivers/clk/qcom/clk-alpha-pll.c
507
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
drivers/clk/qcom/clk-alpha-pll.c
510
if (pll->flags & SUPPORTS_FSM_MODE)
drivers/clk/qcom/clk-alpha-pll.c
511
qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
drivers/clk/qcom/clk-alpha-pll.c
518
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
521
ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
drivers/clk/qcom/clk-alpha-pll.c
527
if (pll->flags & SUPPORTS_OFFLINE_REQ)
drivers/clk/qcom/clk-alpha-pll.c
530
ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val);
drivers/clk/qcom/clk-alpha-pll.c
537
return wait_for_pll_enable_active(pll);
drivers/clk/qcom/clk-alpha-pll.c
543
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
546
ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
drivers/clk/qcom/clk-alpha-pll.c
550
if (pll->flags & SUPPORTS_OFFLINE_REQ) {
drivers/clk/qcom/clk-alpha-pll.c
551
ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
drivers/clk/qcom/clk-alpha-pll.c
556
ret = wait_for_pll_offline(pll);
drivers/clk/qcom/clk-alpha-pll.c
562
ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
drivers/clk/qcom/clk-alpha-pll.c
567
wait_for_pll_disable(pll);
drivers/clk/qcom/clk-alpha-pll.c
573
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
576
ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
drivers/clk/qcom/clk-alpha-pll.c
596
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
600
ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
drivers/clk/qcom/clk-alpha-pll.c
609
return wait_for_pll_enable_active(pll);
drivers/clk/qcom/clk-alpha-pll.c
616
ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
drivers/clk/qcom/clk-alpha-pll.c
628
ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
drivers/clk/qcom/clk-alpha-pll.c
633
ret = wait_for_pll_enable_lock(pll);
drivers/clk/qcom/clk-alpha-pll.c
637
ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
drivers/clk/qcom/clk-alpha-pll.c
648
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
651
ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
drivers/clk/qcom/clk-alpha-pll.c
66
#define GET_PLL_TYPE(pll) (((pll)->regs - clk_alpha_pll_regs[0]) / PLL_OFF_MAX_REGS)
drivers/clk/qcom/clk-alpha-pll.c
662
regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
drivers/clk/qcom/clk-alpha-pll.c
669
regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
drivers/clk/qcom/clk-alpha-pll.c
707
alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate)
drivers/clk/qcom/clk-alpha-pll.c
709
const struct pll_vco *v = pll->vco_table;
drivers/clk/qcom/clk-alpha-pll.c
710
const struct pll_vco *end = v + pll->num_vco;
drivers/clk/qcom/clk-alpha-pll.c
724
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
725
u32 alpha_width = pll_alpha_width(pll);
drivers/clk/qcom/clk-alpha-pll.c
727
if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l))
drivers/clk/qcom/clk-alpha-pll.c
730
if (regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl))
drivers/clk/qcom/clk-alpha-pll.c
734
if (regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low))
drivers/clk/qcom/clk-alpha-pll.c
737
if (regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
drivers/clk/qcom/clk-alpha-pll.c
753
static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll)
drivers/clk/qcom/clk-alpha-pll.c
758
regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode);
drivers/clk/qcom/clk-alpha-pll.c
761
regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE,
drivers/clk/qcom/clk-alpha-pll.c
775
ret = wait_for_pll_update_ack_set(pll);
drivers/clk/qcom/clk-alpha-pll.c
779
regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0);
drivers/clk/qcom/clk-alpha-pll.c
781
ret = wait_for_pll_update(pll);
drivers/clk/qcom/clk-alpha-pll.c
786
ret = wait_for_pll_update_ack_clear(pll);
drivers/clk/qcom/clk-alpha-pll.c
796
static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll,
drivers/clk/qcom/clk-alpha-pll.c
799
if (!is_enabled(&pll->clkr.hw) ||
drivers/clk/qcom/clk-alpha-pll.c
800
!(pll->flags & SUPPORTS_DYNAMIC_UPDATE))
drivers/clk/qcom/clk-alpha-pll.c
803
return __clk_alpha_pll_update_latch(pll);
drivers/clk/qcom/clk-alpha-pll.c
806
static void clk_alpha_pll_update_configs(struct clk_alpha_pll *pll, const struct pll_vco *vco,
drivers/clk/qcom/clk-alpha-pll.c
809
regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
drivers/clk/qcom/clk-alpha-pll.c
815
regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), upper_32_bits(alpha));
drivers/clk/qcom/clk-alpha-pll.c
817
regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), lower_32_bits(alpha));
drivers/clk/qcom/clk-alpha-pll.c
820
regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
drivers/clk/qcom/clk-alpha-pll.c
826
regmap_set_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_ALPHA_EN);
drivers/clk/qcom/clk-alpha-pll.c
833
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
835
u32 l, alpha_width = pll_alpha_width(pll);
drivers/clk/qcom/clk-alpha-pll.c
839
vco = alpha_pll_find_vco(pll, rate);
drivers/clk/qcom/clk-alpha-pll.c
840
if (pll->vco_table && !vco) {
drivers/clk/qcom/clk-alpha-pll.c
846
clk_alpha_pll_update_configs(pll, vco, l, a, alpha_width, true);
drivers/clk/qcom/clk-alpha-pll.c
848
return clk_alpha_pll_update_latch(pll, is_enabled);
drivers/clk/qcom/clk-alpha-pll.c
868
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
869
u32 l, alpha_width = pll_alpha_width(pll);
drivers/clk/qcom/clk-alpha-pll.c
875
if (!pll->vco_table || alpha_pll_find_vco(pll, req->rate))
drivers/clk/qcom/clk-alpha-pll.c
878
min_freq = pll->vco_table[0].min_freq;
drivers/clk/qcom/clk-alpha-pll.c
879
max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
drivers/clk/qcom/clk-alpha-pll.c
886
void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
drivers/clk/qcom/clk-alpha-pll.c
891
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
drivers/clk/qcom/clk-alpha-pll.c
892
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
drivers/clk/qcom/clk-alpha-pll.c
893
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
drivers/clk/qcom/clk-alpha-pll.c
894
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
drivers/clk/qcom/clk-alpha-pll.c
895
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
drivers/clk/qcom/clk-alpha-pll.c
896
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
drivers/clk/qcom/clk-alpha-pll.c
897
clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
drivers/clk/qcom/clk-alpha-pll.c
898
clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
drivers/clk/qcom/clk-alpha-pll.c
899
clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
drivers/clk/qcom/clk-alpha-pll.c
902
regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL);
drivers/clk/qcom/clk-alpha-pll.c
903
regmap_read(regmap, PLL_MODE(pll), &val);
drivers/clk/qcom/clk-alpha-pll.c
909
regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
drivers/clk/qcom/clk-alpha-pll.c
910
regmap_read(regmap, PLL_MODE(pll), &val);
drivers/clk/qcom/clk-alpha-pll.c
916
regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
drivers/clk/qcom/clk-alpha-pll.c
971
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
drivers/clk/qcom/clk-alpha-pll.c
974
if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l))
drivers/clk/qcom/clk-alpha-pll.c
977
if (regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl))
drivers/clk/qcom/clk-alpha-pll.c
981
regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha);
drivers/clk/qcom/clk-alpha-pll.h
226
void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
drivers/clk/qcom/clk-alpha-pll.h
228
void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
drivers/clk/qcom/clk-alpha-pll.h
230
void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
drivers/clk/qcom/clk-alpha-pll.h
232
void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
drivers/clk/qcom/clk-alpha-pll.h
234
void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
drivers/clk/qcom/clk-alpha-pll.h
236
#define clk_lucid_pll_configure(pll, regmap, config) \
drivers/clk/qcom/clk-alpha-pll.h
237
clk_trion_pll_configure(pll, regmap, config)
drivers/clk/qcom/clk-alpha-pll.h
239
void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
drivers/clk/qcom/clk-alpha-pll.h
241
void clk_lucid_5lpe_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
drivers/clk/qcom/clk-alpha-pll.h
243
void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
drivers/clk/qcom/clk-alpha-pll.h
245
void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
drivers/clk/qcom/clk-alpha-pll.h
247
void clk_pongo_elu_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
drivers/clk/qcom/clk-alpha-pll.h
249
#define clk_taycan_elu_pll_configure(pll, regmap, config) \
drivers/clk/qcom/clk-alpha-pll.h
250
clk_lucid_evo_pll_configure(pll, regmap, config)
drivers/clk/qcom/clk-alpha-pll.h
251
#define clk_taycan_eko_t_pll_configure(pll, regmap, config) \
drivers/clk/qcom/clk-alpha-pll.h
252
clk_lucid_evo_pll_configure(pll, regmap, config)
drivers/clk/qcom/clk-alpha-pll.h
253
#define clk_taycan_eha_t_pll_configure(pll, regmap, config) \
drivers/clk/qcom/clk-alpha-pll.h
254
clk_lucid_evo_pll_configure(pll, regmap, config)
drivers/clk/qcom/clk-alpha-pll.h
256
void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
drivers/clk/qcom/clk-alpha-pll.h
258
void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
drivers/clk/qcom/clk-alpha-pll.h
260
void clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
drivers/clk/qcom/clk-alpha-pll.h
262
void qcom_clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap);
drivers/clk/qcom/clk-pll.c
102
if (pll->post_div_width) {
drivers/clk/qcom/clk-pll.c
103
regmap_read(pll->clkr.regmap, pll->config_reg, &config);
drivers/clk/qcom/clk-pll.c
104
config >>= pll->post_div_shift;
drivers/clk/qcom/clk-pll.c
105
config &= BIT(pll->post_div_width) - 1;
drivers/clk/qcom/clk-pll.c
128
struct clk_pll *pll = to_clk_pll(hw);
drivers/clk/qcom/clk-pll.c
131
f = find_freq(pll->freq_tbl, req->rate);
drivers/clk/qcom/clk-pll.c
143
struct clk_pll *pll = to_clk_pll(hw);
drivers/clk/qcom/clk-pll.c
149
f = find_freq(pll->freq_tbl, rate);
drivers/clk/qcom/clk-pll.c
153
regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);
drivers/clk/qcom/clk-pll.c
159
regmap_update_bits(pll->clkr.regmap, pll->l_reg, 0x3ff, f->l);
drivers/clk/qcom/clk-pll.c
160
regmap_update_bits(pll->clkr.regmap, pll->m_reg, 0x7ffff, f->m);
drivers/clk/qcom/clk-pll.c
161
regmap_update_bits(pll->clkr.regmap, pll->n_reg, 0x7ffff, f->n);
drivers/clk/qcom/clk-pll.c
162
regmap_write(pll->clkr.regmap, pll->config_reg, f->ibits);
drivers/clk/qcom/clk-pll.c
179
static int wait_for_pll(struct clk_pll *pll)
drivers/clk/qcom/clk-pll.c
184
const char *name = clk_hw_get_name(&pll->clkr.hw);
drivers/clk/qcom/clk-pll.c
188
ret = regmap_read(pll->clkr.regmap, pll->status_reg, &val);
drivers/clk/qcom/clk-pll.c
191
if (val & BIT(pll->status_bit))
drivers/clk/qcom/clk-pll.c
218
static void clk_pll_configure(struct clk_pll *pll, struct regmap *regmap,
drivers/clk/qcom/clk-pll.c
224
regmap_write(regmap, pll->l_reg, config->l);
drivers/clk/qcom/clk-pll.c
225
regmap_write(regmap, pll->m_reg, config->m);
drivers/clk/qcom/clk-pll.c
226
regmap_write(regmap, pll->n_reg, config->n);
drivers/clk/qcom/clk-pll.c
242
regmap_update_bits(regmap, pll->config_reg, mask, val);
drivers/clk/qcom/clk-pll.c
245
void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap,
drivers/clk/qcom/clk-pll.c
248
clk_pll_configure(pll, regmap, config);
drivers/clk/qcom/clk-pll.c
250
qcom_pll_set_fsm_mode(regmap, pll->mode_reg, 1, 8);
drivers/clk/qcom/clk-pll.c
254
void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,
drivers/clk/qcom/clk-pll.c
257
clk_pll_configure(pll, regmap, config);
drivers/clk/qcom/clk-pll.c
259
qcom_pll_set_fsm_mode(regmap, pll->mode_reg, 1, 0);
drivers/clk/qcom/clk-pll.c
26
struct clk_pll *pll = to_clk_pll(hw);
drivers/clk/qcom/clk-pll.c
265
struct clk_pll *pll = to_clk_pll(hw);
drivers/clk/qcom/clk-pll.c
269
ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);
drivers/clk/qcom/clk-pll.c
274
ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL,
drivers/clk/qcom/clk-pll.c
286
ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N,
drivers/clk/qcom/clk-pll.c
291
ret = wait_for_pll(pll);
drivers/clk/qcom/clk-pll.c
296
return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL,
drivers/clk/qcom/clk-pll.c
303
struct clk_pll *pll = to_clk_pll(hw);
drivers/clk/qcom/clk-pll.c
309
f = find_freq(pll->freq_tbl, rate);
drivers/clk/qcom/clk-pll.c
31
ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val);
drivers/clk/qcom/clk-pll.c
313
regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);
drivers/clk/qcom/clk-pll.c
319
regmap_update_bits(pll->clkr.regmap, pll->l_reg, 0x3ff, f->l);
drivers/clk/qcom/clk-pll.c
320
regmap_update_bits(pll->clkr.regmap, pll->m_reg, 0x7ffff, f->m);
drivers/clk/qcom/clk-pll.c
321
regmap_update_bits(pll->clkr.regmap, pll->n_reg, 0x7ffff, f->n);
drivers/clk/qcom/clk-pll.c
40
ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL,
drivers/clk/qcom/clk-pll.c
52
ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N,
drivers/clk/qcom/clk-pll.c
61
return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL,
drivers/clk/qcom/clk-pll.c
67
struct clk_pll *pll = to_clk_pll(hw);
drivers/clk/qcom/clk-pll.c
71
regmap_read(pll->clkr.regmap, pll->mode_reg, &val);
drivers/clk/qcom/clk-pll.c
76
regmap_update_bits(pll->clkr.regmap, pll->mode_reg, mask, 0);
drivers/clk/qcom/clk-pll.c
82
struct clk_pll *pll = to_clk_pll(hw);
drivers/clk/qcom/clk-pll.c
87
regmap_read(pll->clkr.regmap, pll->l_reg, &l);
drivers/clk/qcom/clk-pll.c
88
regmap_read(pll->clkr.regmap, pll->m_reg, &m);
drivers/clk/qcom/clk-pll.c
89
regmap_read(pll->clkr.regmap, pll->n_reg, &n);
drivers/clk/qcom/clk-pll.h
76
void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap,
drivers/clk/qcom/clk-pll.h
78
void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,
drivers/clk/qcom/common.c
294
struct clk_alpha_pll *pll;
drivers/clk/qcom/common.c
298
pll = data->alpha_plls[i];
drivers/clk/qcom/common.c
299
init = pll->clkr.hw.init;
drivers/clk/qcom/common.c
301
if (!pll->config || !pll->regs) {
drivers/clk/qcom/common.c
306
qcom_clk_alpha_pll_configure(pll, regmap);
drivers/clk/qcom/gcc-ipq4019.c
131
struct clk_fepll *pll = to_clk_fepll(hw);
drivers/clk/qcom/gcc-ipq4019.c
135
f = qcom_find_freq(pll->freq_tbl, req->rate);
drivers/clk/qcom/gcc-ipq4019.c
155
struct clk_fepll *pll = to_clk_fepll(hw);
drivers/clk/qcom/gcc-ipq4019.c
159
f = qcom_find_freq(pll->freq_tbl, rate);
drivers/clk/qcom/gcc-ipq4019.c
163
mask = (BIT(pll->cdiv.width) - 1) << pll->cdiv.shift;
drivers/clk/qcom/gcc-ipq4019.c
164
regmap_update_bits(pll->cdiv.clkr.regmap,
drivers/clk/qcom/gcc-ipq4019.c
165
pll->cdiv.reg, mask,
drivers/clk/qcom/gcc-ipq4019.c
166
f->pre_div << pll->cdiv.shift);
drivers/clk/qcom/gcc-ipq4019.c
186
struct clk_fepll *pll = to_clk_fepll(hw);
drivers/clk/qcom/gcc-ipq4019.c
190
regmap_read(pll->cdiv.clkr.regmap, pll->cdiv.reg, &cdiv);
drivers/clk/qcom/gcc-ipq4019.c
191
cdiv = (cdiv >> pll->cdiv.shift) & (BIT(pll->cdiv.width) - 1);
drivers/clk/qcom/gcc-ipq4019.c
203
rate = clk_fepll_vco_calc_rate(pll, parent_rate) * 2;
drivers/clk/qcom/gcc-ipq4019.c
263
struct clk_fepll *pll = to_clk_fepll(hw);
drivers/clk/qcom/gcc-ipq4019.c
268
if (pll->fixed_div) {
drivers/clk/qcom/gcc-ipq4019.c
269
pre_div = pll->fixed_div;
drivers/clk/qcom/gcc-ipq4019.c
271
regmap_read(pll->cdiv.clkr.regmap, pll->cdiv.reg, &cdiv);
drivers/clk/qcom/gcc-ipq4019.c
272
cdiv = (cdiv >> pll->cdiv.shift) & (BIT(pll->cdiv.width) - 1);
drivers/clk/qcom/gcc-ipq4019.c
274
for (clkt = pll->div_table; clkt->div; clkt++) {
drivers/clk/qcom/gcc-ipq4019.c
280
rate = clk_fepll_vco_calc_rate(pll, parent_rate);
drivers/clk/ralink/clk-mt7621.c
262
u32 pll, prediv, fbdiv;
drivers/clk/ralink/clk-mt7621.c
277
regmap_read(memc, MEMC_REG_CPU_PLL, &pll);
drivers/clk/ralink/clk-mt7621.c
278
fbdiv = FIELD_GET(CPU_PLL_FBDIV_MASK, pll);
drivers/clk/ralink/clk-mt7621.c
279
prediv = FIELD_GET(CPU_PLL_PREDIV_MASK, pll);
drivers/clk/renesas/rzv2h-cpg.c
139
struct pll pll;
drivers/clk/renesas/rzv2h-cpg.c
401
if (!rzv2h_get_pll_pars(limits, &p.pll, freq_millihz * table[i]))
drivers/clk/renesas/rzv2h-cpg.c
405
p.div.freq_millihz = DIV_U64_ROUND_CLOSEST(p.pll.freq_millihz, table[i]);
drivers/clk/renesas/rzv2h-cpg.c
468
dsi_info = &priv->pll_dsi_info[pll_clk->pll.instance];
drivers/clk/renesas/rzv2h-cpg.c
510
dsi_info = &priv->pll_dsi_info[pll_clk->pll.instance];
drivers/clk/renesas/rzv2h-cpg.c
587
dsi_info = &priv->pll_dsi_info[pll_clk->pll.instance];
drivers/clk/renesas/rzv2h-cpg.c
595
&dsi_info->pll_dsi_parameters.pll, rate_millihz)) {
drivers/clk/renesas/rzv2h-cpg.c
602
req->rate = DIV_ROUND_CLOSEST_ULL(dsi_info->pll_dsi_parameters.pll.freq_millihz, MILLI);
drivers/clk/renesas/rzv2h-cpg.c
613
u16 offset = pll_clk->pll.offset;
drivers/clk/renesas/rzv2h-cpg.c
665
dsi_info = &priv->pll_dsi_info[pll_clk->pll.instance];
drivers/clk/renesas/rzv2h-cpg.c
667
return rzv2h_cpg_pll_set_rate(pll_clk, &dsi_info->pll_dsi_parameters.pll, true);
drivers/clk/renesas/rzv2h-cpg.c
689
dsi_info = &priv->pll_dsi_info[pll_clk->pll.instance];
drivers/clk/renesas/rzv2h-cpg.c
833
u32 val = readl(priv->base + CPG_PLL_MON(pll_clk->pll.offset));
drivers/clk/renesas/rzv2h-cpg.c
844
struct pll pll = pll_clk->pll;
drivers/clk/renesas/rzv2h-cpg.c
853
stby_offset = CPG_PLL_STBY(pll.offset);
drivers/clk/renesas/rzv2h-cpg.c
854
mon_offset = CPG_PLL_MON(pll.offset);
drivers/clk/renesas/rzv2h-cpg.c
882
struct pll pll = pll_clk->pll;
drivers/clk/renesas/rzv2h-cpg.c
886
if (!pll.has_clkn)
drivers/clk/renesas/rzv2h-cpg.c
889
clk1 = readl(priv->base + CPG_PLL_CLK1(pll.offset));
drivers/clk/renesas/rzv2h-cpg.c
890
clk2 = readl(priv->base + CPG_PLL_CLK2(pll.offset));
drivers/clk/renesas/rzv2h-cpg.c
932
priv->pll_dsi_info[core->cfg.pll.instance].pll_dsi_limits =
drivers/clk/renesas/rzv2h-cpg.c
933
core->cfg.pll.limits;
drivers/clk/renesas/rzv2h-cpg.c
943
pll_clk->pll = core->cfg.pll;
drivers/clk/renesas/rzv2h-cpg.h
189
struct pll pll;
drivers/clk/renesas/rzv2h-cpg.h
218
DEF_TYPE(_name, _id, CLK_TYPE_PLL, .parent = _parent, .cfg.pll = _pll_packed)
drivers/clk/renesas/rzv2h-cpg.h
242
DEF_TYPE(_name, _id, CLK_TYPE_PLLDSI, .parent = _parent, .cfg.pll = _pll_packed)
drivers/clk/renesas/rzv2h-cpg.h
29
((struct pll){ \
drivers/clk/rockchip/clk-pll.c
1005
return rockchip_rk3588_pll_set_params(pll, rate);
drivers/clk/rockchip/clk-pll.c
1010
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
drivers/clk/rockchip/clk-pll.c
1013
pll->reg_base + RK3588_PLLCON(1));
drivers/clk/rockchip/clk-pll.c
1014
rockchip_rk3588_pll_wait_lock(pll);
drivers/clk/rockchip/clk-pll.c
1021
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
drivers/clk/rockchip/clk-pll.c
1024
pll->reg_base + RK3588_PLLCON(1));
drivers/clk/rockchip/clk-pll.c
1029
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
drivers/clk/rockchip/clk-pll.c
1030
u32 pllcon = readl(pll->reg_base + RK3588_PLLCON(1));
drivers/clk/rockchip/clk-pll.c
1065
struct rockchip_clk_pll *pll;
drivers/clk/rockchip/clk-pll.c
1079
pll = kzalloc_obj(*pll);
drivers/clk/rockchip/clk-pll.c
1080
if (!pll)
drivers/clk/rockchip/clk-pll.c
1084
pll->pll_mux_ops = &clk_mux_ops;
drivers/clk/rockchip/clk-pll.c
1085
pll_mux = &pll->pll_mux;
drivers/clk/rockchip/clk-pll.c
1110
init.ops = pll->pll_mux_ops;
drivers/clk/rockchip/clk-pll.c
1137
pll->rate_count = len;
drivers/clk/rockchip/clk-pll.c
1138
pll->rate_table = kmemdup_array(rate_table,
drivers/clk/rockchip/clk-pll.c
1139
pll->rate_count,
drivers/clk/rockchip/clk-pll.c
1140
sizeof(*pll->rate_table),
drivers/clk/rockchip/clk-pll.c
1142
WARN(!pll->rate_table,
drivers/clk/rockchip/clk-pll.c
1150
if (!pll->rate_table)
drivers/clk/rockchip/clk-pll.c
1156
if (!pll->rate_table || IS_ERR(ctx->grf))
drivers/clk/rockchip/clk-pll.c
1162
if (!pll->rate_table)
drivers/clk/rockchip/clk-pll.c
1170
if (!pll->rate_table)
drivers/clk/rockchip/clk-pll.c
1181
pll->hw.init = &init;
drivers/clk/rockchip/clk-pll.c
1182
pll->type = pll_type;
drivers/clk/rockchip/clk-pll.c
1183
pll->reg_base = ctx->reg_base + con_offset;
drivers/clk/rockchip/clk-pll.c
1184
pll->lock_offset = grf_lock_offset;
drivers/clk/rockchip/clk-pll.c
1185
pll->lock_shift = lock_shift;
drivers/clk/rockchip/clk-pll.c
1186
pll->flags = clk_pll_flags;
drivers/clk/rockchip/clk-pll.c
1187
pll->lock = &ctx->lock;
drivers/clk/rockchip/clk-pll.c
1188
pll->ctx = ctx;
drivers/clk/rockchip/clk-pll.c
1190
pll_clk = clk_register(NULL, &pll->hw);
drivers/clk/rockchip/clk-pll.c
1200
kfree(pll->rate_table);
drivers/clk/rockchip/clk-pll.c
1204
kfree(pll);
drivers/clk/rockchip/clk-pll.c
125
static int rockchip_rk3036_pll_wait_lock(struct rockchip_clk_pll *pll)
drivers/clk/rockchip/clk-pll.c
134
ret = readl_relaxed_poll_timeout(pll->reg_base + RK3036_PLLCON(1),
drivers/clk/rockchip/clk-pll.c
144
static void rockchip_rk3036_pll_get_params(struct rockchip_clk_pll *pll,
drivers/clk/rockchip/clk-pll.c
149
pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(0));
drivers/clk/rockchip/clk-pll.c
155
pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(1));
drivers/clk/rockchip/clk-pll.c
163
pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));
drivers/clk/rockchip/clk-pll.c
171
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
drivers/clk/rockchip/clk-pll.c
175
rockchip_rk3036_pll_get_params(pll, &cur);
drivers/clk/rockchip/clk-pll.c
194
static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll,
drivers/clk/rockchip/clk-pll.c
197
const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
drivers/clk/rockchip/clk-pll.c
198
struct clk_mux *pll_mux = &pll->pll_mux;
drivers/clk/rockchip/clk-pll.c
209
rockchip_rk3036_pll_get_params(pll, &cur);
drivers/clk/rockchip/clk-pll.c
212
if (!(pll->flags & ROCKCHIP_PLL_FIXED_MODE)) {
drivers/clk/rockchip/clk-pll.c
225
pll->reg_base + RK3036_PLLCON(0));
drivers/clk/rockchip/clk-pll.c
233
pll->reg_base + RK3036_PLLCON(1));
drivers/clk/rockchip/clk-pll.c
236
pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));
drivers/clk/rockchip/clk-pll.c
239
writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2));
drivers/clk/rockchip/clk-pll.c
242
ret = rockchip_rk3036_pll_wait_lock(pll);
drivers/clk/rockchip/clk-pll.c
246
rockchip_rk3036_pll_set_params(pll, &cur);
drivers/clk/rockchip/clk-pll.c
258
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
drivers/clk/rockchip/clk-pll.c
265
rate = rockchip_get_pll_settings(pll, drate);
drivers/clk/rockchip/clk-pll.c
272
return rockchip_rk3036_pll_set_params(pll, rate);
drivers/clk/rockchip/clk-pll.c
277
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
drivers/clk/rockchip/clk-pll.c
280
pll->reg_base + RK3036_PLLCON(1));
drivers/clk/rockchip/clk-pll.c
281
rockchip_rk3036_pll_wait_lock(pll);
drivers/clk/rockchip/clk-pll.c
288
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
drivers/clk/rockchip/clk-pll.c
292
pll->reg_base + RK3036_PLLCON(1));
drivers/clk/rockchip/clk-pll.c
297
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
drivers/clk/rockchip/clk-pll.c
298
u32 pllcon = readl(pll->reg_base + RK3036_PLLCON(1));
drivers/clk/rockchip/clk-pll.c
305
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
drivers/clk/rockchip/clk-pll.c
310
if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
drivers/clk/rockchip/clk-pll.c
314
rate = rockchip_get_pll_settings(pll, drate);
drivers/clk/rockchip/clk-pll.c
320
rockchip_rk3036_pll_get_params(pll, &cur);
drivers/clk/rockchip/clk-pll.c
345
rockchip_rk3036_pll_set_params(pll, rate);
drivers/clk/rockchip/clk-pll.c
387
static void rockchip_rk3066_pll_get_params(struct rockchip_clk_pll *pll,
drivers/clk/rockchip/clk-pll.c
392
pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0));
drivers/clk/rockchip/clk-pll.c
398
pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1));
drivers/clk/rockchip/clk-pll.c
402
pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2));
drivers/clk/rockchip/clk-pll.c
410
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
drivers/clk/rockchip/clk-pll.c
415
pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3));
drivers/clk/rockchip/clk-pll.c
422
rockchip_rk3066_pll_get_params(pll, &cur);
drivers/clk/rockchip/clk-pll.c
431
static int rockchip_rk3066_pll_set_params(struct rockchip_clk_pll *pll,
drivers/clk/rockchip/clk-pll.c
434
const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
drivers/clk/rockchip/clk-pll.c
435
struct clk_mux *pll_mux = &pll->pll_mux;
drivers/clk/rockchip/clk-pll.c
444
rockchip_rk3066_pll_get_params(pll, &cur);
drivers/clk/rockchip/clk-pll.c
455
pll->reg_base + RK3066_PLLCON(3));
drivers/clk/rockchip/clk-pll.c
462
pll->reg_base + RK3066_PLLCON(0));
drivers/clk/rockchip/clk-pll.c
466
pll->reg_base + RK3066_PLLCON(1));
drivers/clk/rockchip/clk-pll.c
469
pll->reg_base + RK3066_PLLCON(2));
drivers/clk/rockchip/clk-pll.c
473
pll->reg_base + RK3066_PLLCON(3));
drivers/clk/rockchip/clk-pll.c
477
ret = rockchip_pll_wait_lock(pll);
drivers/clk/rockchip/clk-pll.c
481
rockchip_rk3066_pll_set_params(pll, &cur);
drivers/clk/rockchip/clk-pll.c
493
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
drivers/clk/rockchip/clk-pll.c
500
rate = rockchip_get_pll_settings(pll, drate);
drivers/clk/rockchip/clk-pll.c
507
return rockchip_rk3066_pll_set_params(pll, rate);
drivers/clk/rockchip/clk-pll.c
51
struct rockchip_clk_pll *pll, unsigned long rate)
drivers/clk/rockchip/clk-pll.c
512
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
drivers/clk/rockchip/clk-pll.c
515
pll->reg_base + RK3066_PLLCON(3));
drivers/clk/rockchip/clk-pll.c
516
rockchip_pll_wait_lock(pll);
drivers/clk/rockchip/clk-pll.c
523
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
drivers/clk/rockchip/clk-pll.c
527
pll->reg_base + RK3066_PLLCON(3));
drivers/clk/rockchip/clk-pll.c
53
const struct rockchip_pll_rate_table *rate_table = pll->rate_table;
drivers/clk/rockchip/clk-pll.c
532
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
drivers/clk/rockchip/clk-pll.c
533
u32 pllcon = readl(pll->reg_base + RK3066_PLLCON(3));
drivers/clk/rockchip/clk-pll.c
540
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
drivers/clk/rockchip/clk-pll.c
545
if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
drivers/clk/rockchip/clk-pll.c
549
rate = rockchip_get_pll_settings(pll, drate);
drivers/clk/rockchip/clk-pll.c
555
rockchip_rk3066_pll_get_params(pll, &cur);
drivers/clk/rockchip/clk-pll.c
56
for (i = 0; i < pll->rate_count; i++) {
drivers/clk/rockchip/clk-pll.c
564
rockchip_rk3066_pll_set_params(pll, rate);
drivers/clk/rockchip/clk-pll.c
607
static int rockchip_rk3399_pll_wait_lock(struct rockchip_clk_pll *pll)
drivers/clk/rockchip/clk-pll.c
616
ret = readl_relaxed_poll_timeout(pll->reg_base + RK3399_PLLCON(2),
drivers/clk/rockchip/clk-pll.c
626
static void rockchip_rk3399_pll_get_params(struct rockchip_clk_pll *pll,
drivers/clk/rockchip/clk-pll.c
631
pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(0));
drivers/clk/rockchip/clk-pll.c
635
pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(1));
drivers/clk/rockchip/clk-pll.c
643
pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));
drivers/clk/rockchip/clk-pll.c
647
pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(3));
drivers/clk/rockchip/clk-pll.c
655
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
drivers/clk/rockchip/clk-pll.c
659
rockchip_rk3399_pll_get_params(pll, &cur);
drivers/clk/rockchip/clk-pll.c
67
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
drivers/clk/rockchip/clk-pll.c
678
static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *pll,
drivers/clk/rockchip/clk-pll.c
68
const struct rockchip_pll_rate_table *rate_table = pll->rate_table;
drivers/clk/rockchip/clk-pll.c
681
const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
drivers/clk/rockchip/clk-pll.c
682
struct clk_mux *pll_mux = &pll->pll_mux;
drivers/clk/rockchip/clk-pll.c
693
rockchip_rk3399_pll_get_params(pll, &cur);
drivers/clk/rockchip/clk-pll.c
705
pll->reg_base + RK3399_PLLCON(0));
drivers/clk/rockchip/clk-pll.c
713
pll->reg_base + RK3399_PLLCON(1));
drivers/clk/rockchip/clk-pll.c
716
pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));
drivers/clk/rockchip/clk-pll.c
719
writel_relaxed(pllcon, pll->reg_base + RK3399_PLLCON(2));
drivers/clk/rockchip/clk-pll.c
72
for (i = 0; i < pll->rate_count; i++) {
drivers/clk/rockchip/clk-pll.c
723
pll->reg_base + RK3399_PLLCON(3));
drivers/clk/rockchip/clk-pll.c
726
ret = rockchip_rk3399_pll_wait_lock(pll);
drivers/clk/rockchip/clk-pll.c
730
rockchip_rk3399_pll_set_params(pll, &cur);
drivers/clk/rockchip/clk-pll.c
742
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
drivers/clk/rockchip/clk-pll.c
749
rate = rockchip_get_pll_settings(pll, drate);
drivers/clk/rockchip/clk-pll.c
756
return rockchip_rk3399_pll_set_params(pll, rate);
drivers/clk/rockchip/clk-pll.c
761
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
drivers/clk/rockchip/clk-pll.c
764
pll->reg_base + RK3399_PLLCON(3));
drivers/clk/rockchip/clk-pll.c
765
rockchip_rk3399_pll_wait_lock(pll);
drivers/clk/rockchip/clk-pll.c
772
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
drivers/clk/rockchip/clk-pll.c
776
pll->reg_base + RK3399_PLLCON(3));
drivers/clk/rockchip/clk-pll.c
781
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
drivers/clk/rockchip/clk-pll.c
782
u32 pllcon = readl(pll->reg_base + RK3399_PLLCON(3));
drivers/clk/rockchip/clk-pll.c
789
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
drivers/clk/rockchip/clk-pll.c
794
if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
drivers/clk/rockchip/clk-pll.c
798
rate = rockchip_get_pll_settings(pll, drate);
drivers/clk/rockchip/clk-pll.c
804
rockchip_rk3399_pll_get_params(pll, &cur);
drivers/clk/rockchip/clk-pll.c
829
rockchip_rk3399_pll_set_params(pll, rate);
drivers/clk/rockchip/clk-pll.c
868
static int rockchip_rk3588_pll_wait_lock(struct rockchip_clk_pll *pll)
drivers/clk/rockchip/clk-pll.c
877
ret = readl_relaxed_poll_timeout(pll->reg_base + RK3588_PLLCON(6),
drivers/clk/rockchip/clk-pll.c
887
static void rockchip_rk3588_pll_get_params(struct rockchip_clk_pll *pll,
drivers/clk/rockchip/clk-pll.c
892
pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(0));
drivers/clk/rockchip/clk-pll.c
895
pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(1));
drivers/clk/rockchip/clk-pll.c
899
pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(2));
drivers/clk/rockchip/clk-pll.c
905
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
drivers/clk/rockchip/clk-pll.c
909
rockchip_rk3588_pll_get_params(pll, &cur);
drivers/clk/rockchip/clk-pll.c
91
static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll)
drivers/clk/rockchip/clk-pll.c
924
if (pll->type == pll_rk3588_ddr)
drivers/clk/rockchip/clk-pll.c
93
struct regmap *grf = pll->ctx->grf;
drivers/clk/rockchip/clk-pll.c
930
static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll,
drivers/clk/rockchip/clk-pll.c
933
const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
drivers/clk/rockchip/clk-pll.c
934
struct clk_mux *pll_mux = &pll->pll_mux;
drivers/clk/rockchip/clk-pll.c
943
rockchip_rk3588_pll_get_params(pll, &cur);
drivers/clk/rockchip/clk-pll.c
946
if (pll->type == pll_rk3588) {
drivers/clk/rockchip/clk-pll.c
957
pll->reg_base + RK3399_PLLCON(1));
drivers/clk/rockchip/clk-pll.c
961
pll->reg_base + RK3399_PLLCON(0));
drivers/clk/rockchip/clk-pll.c
965
pll->reg_base + RK3399_PLLCON(1));
drivers/clk/rockchip/clk-pll.c
968
pll->reg_base + RK3399_PLLCON(2));
drivers/clk/rockchip/clk-pll.c
97
ret = regmap_read_poll_timeout(grf, pll->lock_offset, val,
drivers/clk/rockchip/clk-pll.c
972
pll->reg_base + RK3588_PLLCON(1));
drivers/clk/rockchip/clk-pll.c
975
ret = rockchip_rk3588_pll_wait_lock(pll);
drivers/clk/rockchip/clk-pll.c
979
rockchip_rk3588_pll_set_params(pll, &cur);
drivers/clk/rockchip/clk-pll.c
98
val & BIT(pll->lock_shift), 0, 1000);
drivers/clk/rockchip/clk-pll.c
982
if ((pll->type == pll_rk3588) && rate_change_remuxed)
drivers/clk/rockchip/clk-pll.c
991
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
drivers/clk/rockchip/clk-pll.c
998
rate = rockchip_get_pll_settings(pll, drate);
drivers/clk/rockchip/clk-rk3188.c
871
struct rockchip_pll_clock *pll = &rk3188_pll_clks[i];
drivers/clk/rockchip/clk-rk3188.c
874
if (!pll->rate_table)
drivers/clk/rockchip/clk-rk3188.c
877
rate = pll->rate_table;
drivers/clk/samsung/clk-pll.c
102
struct samsung_clk_pll *pll = to_clk_pll(hw);
drivers/clk/samsung/clk-pll.c
1027
struct samsung_clk_pll *pll = to_clk_pll(hw);
drivers/clk/samsung/clk-pll.c
1031
pll_con = readl_relaxed(pll->con_reg);
drivers/clk/samsung/clk-pll.c
105
tmp = readl_relaxed(pll->con_reg);
drivers/clk/samsung/clk-pll.c
1055
struct samsung_clk_pll *pll = to_clk_pll(hw);
drivers/clk/samsung/clk-pll.c
106
tmp |= BIT(pll->enable_offs);
drivers/clk/samsung/clk-pll.c
1060
rate = samsung_get_pll_settings(pll, drate);
drivers/clk/samsung/clk-pll.c
1067
tmp = readl_relaxed(pll->con_reg);
drivers/clk/samsung/clk-pll.c
107
writel_relaxed(tmp, pll->con_reg);
drivers/clk/samsung/clk-pll.c
1073
writel_relaxed(tmp, pll->con_reg);
drivers/clk/samsung/clk-pll.c
1079
writel_relaxed(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg);
drivers/clk/samsung/clk-pll.c
1088
writel_relaxed(tmp, pll->con_reg);
drivers/clk/samsung/clk-pll.c
109
return samsung_pll_lock_wait(pll, BIT(pll->lock_offs));
drivers/clk/samsung/clk-pll.c
1091
return samsung_pll_lock_wait(pll,
drivers/clk/samsung/clk-pll.c
1127
struct samsung_clk_pll *pll = to_clk_pll(hw);
drivers/clk/samsung/clk-pll.c
1132
pll_con0 = readl_relaxed(pll->con_reg);
drivers/clk/samsung/clk-pll.c
1137
pll_con1 = readl_relaxed(pll->con_reg + 4);
drivers/clk/samsung/clk-pll.c
114
struct samsung_clk_pll *pll = to_clk_pll(hw);
drivers/clk/samsung/clk-pll.c
1150
struct samsung_clk_pll *pll = to_clk_pll(hw);
drivers/clk/samsung/clk-pll.c
1155
rate = samsung_get_pll_settings(pll, drate);
drivers/clk/samsung/clk-pll.c
1162
con0 = readl_relaxed(pll->con_reg);
drivers/clk/samsung/clk-pll.c
1163
con1 = readl_relaxed(pll->con_reg + 4);
drivers/clk/samsung/clk-pll.c
1166
writel_relaxed(rate->pdiv * PLL2650X_LOCK_FACTOR, pll->lock_reg);
drivers/clk/samsung/clk-pll.c
117
tmp = readl_relaxed(pll->con_reg);
drivers/clk/samsung/clk-pll.c
1176
writel_relaxed(con0, pll->con_reg);
drivers/clk/samsung/clk-pll.c
118
tmp &= ~BIT(pll->enable_offs);
drivers/clk/samsung/clk-pll.c
1180
writel_relaxed(con1, pll->con_reg + 4);
drivers/clk/samsung/clk-pll.c
1183
return samsung_pll_lock_wait(pll,
drivers/clk/samsung/clk-pll.c
119
writel_relaxed(tmp, pll->con_reg);
drivers/clk/samsung/clk-pll.c
1219
struct samsung_clk_pll *pll = to_clk_pll(hw);
drivers/clk/samsung/clk-pll.c
1224
pll_con0 = readl_relaxed(pll->con_reg);
drivers/clk/samsung/clk-pll.c
1225
pll_con2 = readl_relaxed(pll->con_reg + 8);
drivers/clk/samsung/clk-pll.c
1241
struct samsung_clk_pll *pll = to_clk_pll(hw);
drivers/clk/samsung/clk-pll.c
1245
rate = samsung_get_pll_settings(pll, drate);
drivers/clk/samsung/clk-pll.c
1252
pll_con0 = readl_relaxed(pll->con_reg);
drivers/clk/samsung/clk-pll.c
1253
pll_con2 = readl_relaxed(pll->con_reg + 8);
drivers/clk/samsung/clk-pll.c
1270
writel_relaxed(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg);
drivers/clk/samsung/clk-pll.c
1272
writel_relaxed(pll_con0, pll->con_reg);
drivers/clk/samsung/clk-pll.c
1273
writel_relaxed(pll_con2, pll->con_reg + 8);
drivers/clk/samsung/clk-pll.c
1275
return samsung_pll_lock_wait(pll, 0x1 << PLL2650XX_PLL_LOCKTIME_SHIFT);
drivers/clk/samsung/clk-pll.c
1304
struct samsung_clk_pll *pll = to_clk_pll(hw);
drivers/clk/samsung/clk-pll.c
1308
pll_con0 = readl_relaxed(pll->con_reg);
drivers/clk/samsung/clk-pll.c
1309
pll_con8 = readl_relaxed(pll->con_reg + 20);
drivers/clk/samsung/clk-pll.c
1351
struct samsung_clk_pll *pll = to_clk_pll(hw);
drivers/clk/samsung/clk-pll.c
1355
pll_con0 = readl_relaxed(pll->con_reg);
drivers/clk/samsung/clk-pll.c
1356
pll_con3 = readl_relaxed(pll->con_reg + 0xc);
drivers/clk/samsung/clk-pll.c
136
struct samsung_clk_pll *pll = to_clk_pll(hw);
drivers/clk/samsung/clk-pll.c
1385
struct samsung_clk_pll *pll = to_clk_pll(hw);
drivers/clk/samsung/clk-pll.c
1390
rate = samsung_get_pll_settings(pll, drate);
drivers/clk/samsung/clk-pll.c
1397
con0 = readl_relaxed(pll->con_reg);
drivers/clk/samsung/clk-pll.c
1398
con3 = readl_relaxed(pll->con_reg + 0xc);
drivers/clk/samsung/clk-pll.c
140
pll_con = readl_relaxed(pll->con_reg);
drivers/clk/samsung/clk-pll.c
1404
writel_relaxed(con0, pll->con_reg);
drivers/clk/samsung/clk-pll.c
1410
writel_relaxed(rate->pdiv * PLL1031X_LOCK_FACTOR, pll->lock_reg);
drivers/clk/samsung/clk-pll.c
1422
con3 = readl_relaxed(pll->con_reg + 0xc);
drivers/clk/samsung/clk-pll.c
1431
writel_relaxed(con0, pll->con_reg);
drivers/clk/samsung/clk-pll.c
1432
writel_relaxed(con3, pll->con_reg + 0xc);
drivers/clk/samsung/clk-pll.c
1435
return samsung_pll_lock_wait(pll, BIT(pll->lock_offs));
drivers/clk/samsung/clk-pll.c
1473
struct samsung_clk_pll *pll = to_clk_pll(hw);
drivers/clk/samsung/clk-pll.c
1478
pll_con0 = readl_relaxed(pll->con_reg);
drivers/clk/samsung/clk-pll.c
1479
pll_con5 = readl_relaxed(pll->con_reg + PLLA9FRACO_PLL_CON5_DIV_FRAC);
drivers/clk/samsung/clk-pll.c
1507
struct samsung_clk_pll *pll = to_clk_pll(hw);
drivers/clk/samsung/clk-pll.c
1513
rate = samsung_get_pll_settings(pll, drate);
drivers/clk/samsung/clk-pll.c
1520
con0 = readl_relaxed(pll->con_reg);
drivers/clk/samsung/clk-pll.c
1521
con5 = readl_relaxed(pll->con_reg + PLLA9FRACO_PLL_CON5_DIV_FRAC);
drivers/clk/samsung/clk-pll.c
1527
writel_relaxed(con0, pll->con_reg);
drivers/clk/samsung/clk-pll.c
1533
con0 = readl_relaxed(pll->con_reg);
drivers/clk/samsung/clk-pll.c
1535
writel_relaxed(con0, pll->con_reg);
drivers/clk/samsung/clk-pll.c
1539
writel_relaxed(con0, pll->con_reg);
drivers/clk/samsung/clk-pll.c
1542
writel_relaxed(rate->pdiv * PLLA9FRACO_LOCK_FACTOR, pll->lock_reg);
drivers/clk/samsung/clk-pll.c
1555
con5 = readl_relaxed(pll->con_reg + PLLA9FRACO_PLL_CON5_DIV_FRAC);
drivers/clk/samsung/clk-pll.c
1561
writel_relaxed(con0, pll->con_reg);
drivers/clk/samsung/clk-pll.c
1562
writel_relaxed(con5, pll->con_reg + PLLA9FRACO_PLL_CON5_DIV_FRAC);
drivers/clk/samsung/clk-pll.c
1565
con0 = readl_relaxed(pll->con_reg);
drivers/clk/samsung/clk-pll.c
1567
writel_relaxed(con0, pll->con_reg);
drivers/clk/samsung/clk-pll.c
1570
ret = samsung_pll_lock_wait(pll, BIT(pll->lock_offs));
drivers/clk/samsung/clk-pll.c
1576
writel_relaxed(con0, pll->con_reg);
drivers/clk/samsung/clk-pll.c
1594
struct samsung_clk_pll *pll;
drivers/clk/samsung/clk-pll.c
1598
pll = kzalloc_obj(*pll);
drivers/clk/samsung/clk-pll.c
1599
if (!pll) {
drivers/clk/samsung/clk-pll.c
1615
pll->rate_count = len;
drivers/clk/samsung/clk-pll.c
1616
pll->rate_table = kmemdup_array(pll_clk->rate_table,
drivers/clk/samsung/clk-pll.c
1617
pll->rate_count,
drivers/clk/samsung/clk-pll.c
1618
sizeof(*pll->rate_table),
drivers/clk/samsung/clk-pll.c
1620
WARN(!pll->rate_table,
drivers/clk/samsung/clk-pll.c
1641
pll->enable_offs = PLL35XX_ENABLE_SHIFT;
drivers/clk/samsung/clk-pll.c
1642
pll->lock_offs = PLL35XX_LOCK_STAT_SHIFT;
drivers/clk/samsung/clk-pll.c
1643
if (!pll->rate_table)
drivers/clk/samsung/clk-pll.c
1660
pll->enable_offs = PLL0822X_ENABLE_SHIFT;
drivers/clk/samsung/clk-pll.c
1661
pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT;
drivers/clk/samsung/clk-pll.c
1662
if (!pll->rate_table)
drivers/clk/samsung/clk-pll.c
1672
if (!pll->rate_table)
drivers/clk/samsung/clk-pll.c
1680
pll->enable_offs = PLL36XX_ENABLE_SHIFT;
drivers/clk/samsung/clk-pll.c
1681
pll->lock_offs = PLL36XX_LOCK_STAT_SHIFT;
drivers/clk/samsung/clk-pll.c
1682
if (!pll->rate_table)
drivers/clk/samsung/clk-pll.c
1688
pll->enable_offs = PLL0831X_ENABLE_SHIFT;
drivers/clk/samsung/clk-pll.c
1689
pll->lock_offs = PLL0831X_LOCK_STAT_SHIFT;
drivers/clk/samsung/clk-pll.c
169
struct samsung_clk_pll *pll = to_clk_pll(hw);
drivers/clk/samsung/clk-pll.c
1690
if (!pll->rate_table)
drivers/clk/samsung/clk-pll.c
1706
if (!pll->rate_table)
drivers/clk/samsung/clk-pll.c
1715
if (!pll->rate_table)
drivers/clk/samsung/clk-pll.c
1721
if (!pll->rate_table)
drivers/clk/samsung/clk-pll.c
1727
if (!pll->rate_table)
drivers/clk/samsung/clk-pll.c
173
pll_con = readl_relaxed(pll->con_reg);
drivers/clk/samsung/clk-pll.c
1737
if (!pll->rate_table)
drivers/clk/samsung/clk-pll.c
1743
pll->enable_offs = PLLA9FRACO_ENABLE_SHIFT;
drivers/clk/samsung/clk-pll.c
1744
pll->lock_offs = PLLA9FRACO_LOCK_STAT_SHIFT;
drivers/clk/samsung/clk-pll.c
1745
if (!pll->rate_table)
drivers/clk/samsung/clk-pll.c
1755
pll->hw.init = &init;
drivers/clk/samsung/clk-pll.c
1756
pll->type = pll_clk->type;
drivers/clk/samsung/clk-pll.c
1757
pll->lock_reg = ctx->reg_base + pll_clk->lock_offset;
drivers/clk/samsung/clk-pll.c
1758
pll->con_reg = ctx->reg_base + pll_clk->con_offset;
drivers/clk/samsung/clk-pll.c
1760
ret = clk_hw_register(ctx->dev, &pll->hw);
drivers/clk/samsung/clk-pll.c
1764
kfree(pll->rate_table);
drivers/clk/samsung/clk-pll.c
1765
kfree(pll);
drivers/clk/samsung/clk-pll.c
1769
samsung_clk_add_lookup(ctx, &pll->hw, pll_clk->id);
drivers/clk/samsung/clk-pll.c
210
struct samsung_clk_pll *pll = to_clk_pll(hw);
drivers/clk/samsung/clk-pll.c
214
pll_con = readl_relaxed(pll->con_reg);
drivers/clk/samsung/clk-pll.c
216
if (pll->type == pll_a9fracm)
drivers/clk/samsung/clk-pll.c
247
struct samsung_clk_pll *pll = to_clk_pll(hw);
drivers/clk/samsung/clk-pll.c
252
if (pll->type == pll_a9fracm)
drivers/clk/samsung/clk-pll.c
258
rate = samsung_get_pll_settings(pll, drate);
drivers/clk/samsung/clk-pll.c
265
tmp = readl_relaxed(pll->con_reg);
drivers/clk/samsung/clk-pll.c
267
if (!(samsung_pll35xx_mp_change(pll->type, rate, tmp))) {
drivers/clk/samsung/clk-pll.c
271
writel_relaxed(tmp, pll->con_reg);
drivers/clk/samsung/clk-pll.c
277
if (pll->type == pll_142xx || pll->type == pll_1017x || pll->type == pll_a9fracm)
drivers/clk/samsung/clk-pll.c
279
pll->lock_reg);
drivers/clk/samsung/clk-pll.c
282
pll->lock_reg);
drivers/clk/samsung/clk-pll.c
291
writel_relaxed(tmp, pll->con_reg);
drivers/clk/samsung/clk-pll.c
294
if (tmp & BIT(pll->enable_offs))
drivers/clk/samsung/clk-pll.c
295
return samsung_pll_lock_wait(pll, BIT(pll->lock_offs));
drivers/clk/samsung/clk-pll.c
332
struct samsung_clk_pll *pll = to_clk_pll(hw);
drivers/clk/samsung/clk-pll.c
337
pll_con0 = readl_relaxed(pll->con_reg);
drivers/clk/samsung/clk-pll.c
338
pll_con1 = readl_relaxed(pll->con_reg + 4);
drivers/clk/samsung/clk-pll.c
367
struct samsung_clk_pll *pll = to_clk_pll(hw);
drivers/clk/samsung/clk-pll.c
37
struct samsung_clk_pll *pll, unsigned long rate)
drivers/clk/samsung/clk-pll.c
371
rate = samsung_get_pll_settings(pll, drate);
drivers/clk/samsung/clk-pll.c
378
pll_con0 = readl_relaxed(pll->con_reg);
drivers/clk/samsung/clk-pll.c
379
pll_con1 = readl_relaxed(pll->con_reg + 4);
drivers/clk/samsung/clk-pll.c
385
writel_relaxed(pll_con0, pll->con_reg);
drivers/clk/samsung/clk-pll.c
39
const struct samsung_pll_rate_table *rate_table = pll->rate_table;
drivers/clk/samsung/clk-pll.c
391
writel_relaxed(rate->pdiv * PLL36XX_LOCK_FACTOR, pll->lock_reg);
drivers/clk/samsung/clk-pll.c
400
writel_relaxed(pll_con0, pll->con_reg);
drivers/clk/samsung/clk-pll.c
404
writel_relaxed(pll_con1, pll->con_reg + 4);
drivers/clk/samsung/clk-pll.c
406
if (pll_con0 & BIT(pll->enable_offs))
drivers/clk/samsung/clk-pll.c
407
return samsung_pll_lock_wait(pll, BIT(pll->lock_offs));
drivers/clk/samsung/clk-pll.c
42
for (i = 0; i < pll->rate_count; i++) {
drivers/clk/samsung/clk-pll.c
448
struct samsung_clk_pll *pll = to_clk_pll(hw);
drivers/clk/samsung/clk-pll.c
452
pll_con3 = readl_relaxed(pll->con_reg);
drivers/clk/samsung/clk-pll.c
454
if (pll->type != pll_1418x &&
drivers/clk/samsung/clk-pll.c
455
pll->type != pll_0717x &&
drivers/clk/samsung/clk-pll.c
456
pll->type != pll_0718x)
drivers/clk/samsung/clk-pll.c
465
if (pll->type == pll_0516x)
drivers/clk/samsung/clk-pll.c
477
struct samsung_clk_pll *pll = to_clk_pll(hw);
drivers/clk/samsung/clk-pll.c
480
if (pll->type != pll_1418x)
drivers/clk/samsung/clk-pll.c
486
rate = samsung_get_pll_settings(pll, drate);
drivers/clk/samsung/clk-pll.c
494
pll_con3 = readl_relaxed(pll->con_reg);
drivers/clk/samsung/clk-pll.c
504
pll->lock_reg);
drivers/clk/samsung/clk-pll.c
507
writel_relaxed(pll_con3, pll->con_reg);
drivers/clk/samsung/clk-pll.c
510
if (pll_con3 & BIT(pll->enable_offs))
drivers/clk/samsung/clk-pll.c
511
return samsung_pll_lock_wait(pll, BIT(pll->lock_offs));
drivers/clk/samsung/clk-pll.c
53
struct samsung_clk_pll *pll = to_clk_pll(hw);
drivers/clk/samsung/clk-pll.c
54
const struct samsung_pll_rate_table *rate_table = pll->rate_table;
drivers/clk/samsung/clk-pll.c
548
struct samsung_clk_pll *pll = to_clk_pll(hw);
drivers/clk/samsung/clk-pll.c
553
pll_con3 = readl_relaxed(pll->con_reg);
drivers/clk/samsung/clk-pll.c
554
pll_con5 = readl_relaxed(pll->con_reg + 8);
drivers/clk/samsung/clk-pll.c
571
struct samsung_clk_pll *pll = to_clk_pll(hw);
drivers/clk/samsung/clk-pll.c
575
rate = samsung_get_pll_settings(pll, drate);
drivers/clk/samsung/clk-pll.c
58
for (i = 0; i < pll->rate_count; i++) {
drivers/clk/samsung/clk-pll.c
582
pll_con3 = readl_relaxed(pll->con_reg);
drivers/clk/samsung/clk-pll.c
583
pll_con5 = readl_relaxed(pll->con_reg + 8);
drivers/clk/samsung/clk-pll.c
600
writel_relaxed(rate->pdiv * PLL0831X_LOCK_FACTOR, pll->lock_reg);
drivers/clk/samsung/clk-pll.c
603
writel_relaxed(pll_con3, pll->con_reg);
drivers/clk/samsung/clk-pll.c
604
writel_relaxed(pll_con5, pll->con_reg + 8);
drivers/clk/samsung/clk-pll.c
607
if (pll_con3 & BIT(pll->enable_offs))
drivers/clk/samsung/clk-pll.c
608
return samsung_pll_lock_wait(pll, BIT(pll->lock_offs));
drivers/clk/samsung/clk-pll.c
646
struct samsung_clk_pll *pll = to_clk_pll(hw);
drivers/clk/samsung/clk-pll.c
650
pll_con = readl_relaxed(pll->con_reg);
drivers/clk/samsung/clk-pll.c
655
if (pll->type == pll_4508)
drivers/clk/samsung/clk-pll.c
680
struct samsung_clk_pll *pll = to_clk_pll(hw);
drivers/clk/samsung/clk-pll.c
685
rate = samsung_get_pll_settings(pll, drate);
drivers/clk/samsung/clk-pll.c
692
con0 = readl_relaxed(pll->con_reg);
drivers/clk/samsung/clk-pll.c
693
con1 = readl_relaxed(pll->con_reg + 0x4);
drivers/clk/samsung/clk-pll.c
699
writel_relaxed(con0, pll->con_reg);
drivers/clk/samsung/clk-pll.c
713
con1 = readl_relaxed(pll->con_reg + 0x4);
drivers/clk/samsung/clk-pll.c
718
switch (pll->type) {
drivers/clk/samsung/clk-pll.c
720
writel_relaxed(rate->pdiv * PLL4502_LOCK_FACTOR, pll->lock_reg);
drivers/clk/samsung/clk-pll.c
723
writel_relaxed(rate->pdiv * PLL4508_LOCK_FACTOR, pll->lock_reg);
drivers/clk/samsung/clk-pll.c
73
static int samsung_pll_lock_wait(struct samsung_clk_pll *pll,
drivers/clk/samsung/clk-pll.c
730
writel_relaxed(con1, pll->con_reg + 0x4);
drivers/clk/samsung/clk-pll.c
731
writel_relaxed(con0, pll->con_reg);
drivers/clk/samsung/clk-pll.c
734
return samsung_pll_lock_wait(pll, PLL45XX_LOCKED);
drivers/clk/samsung/clk-pll.c
779
struct samsung_clk_pll *pll = to_clk_pll(hw);
drivers/clk/samsung/clk-pll.c
783
pll_con0 = readl_relaxed(pll->con_reg);
drivers/clk/samsung/clk-pll.c
784
pll_con1 = readl_relaxed(pll->con_reg + 4);
drivers/clk/samsung/clk-pll.c
785
mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ?
drivers/clk/samsung/clk-pll.c
789
kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK :
drivers/clk/samsung/clk-pll.c
792
shift = ((pll->type == pll_4600) || (pll->type == pll_1460x)) ? 16 : 10;
drivers/clk/samsung/clk-pll.c
817
struct samsung_clk_pll *pll = to_clk_pll(hw);
drivers/clk/samsung/clk-pll.c
822
rate = samsung_get_pll_settings(pll, drate);
drivers/clk/samsung/clk-pll.c
829
con0 = readl_relaxed(pll->con_reg);
drivers/clk/samsung/clk-pll.c
830
con1 = readl_relaxed(pll->con_reg + 0x4);
drivers/clk/samsung/clk-pll.c
836
writel_relaxed(con0, pll->con_reg);
drivers/clk/samsung/clk-pll.c
848
if (pll->type == pll_1460x) {
drivers/clk/samsung/clk-pll.c
865
con1 = readl_relaxed(pll->con_reg + 0x4);
drivers/clk/samsung/clk-pll.c
874
writel_relaxed(lock, pll->lock_reg);
drivers/clk/samsung/clk-pll.c
875
writel_relaxed(con0, pll->con_reg);
drivers/clk/samsung/clk-pll.c
876
writel_relaxed(con1, pll->con_reg + 0x4);
drivers/clk/samsung/clk-pll.c
879
return samsung_pll_lock_wait(pll, PLL46XX_LOCKED);
drivers/clk/samsung/clk-pll.c
908
struct samsung_clk_pll *pll = to_clk_pll(hw);
drivers/clk/samsung/clk-pll.c
91
ret = readl_relaxed_poll_timeout_atomic(pll->con_reg, val,
drivers/clk/samsung/clk-pll.c
912
pll_con = readl_relaxed(pll->con_reg);
drivers/clk/samsung/clk-pll.c
913
if (pll->type == pll_6552_s3c2416) {
drivers/clk/samsung/clk-pll.c
948
struct samsung_clk_pll *pll = to_clk_pll(hw);
drivers/clk/samsung/clk-pll.c
95
pr_err("Could not lock PLL %s\n", clk_hw_get_name(&pll->hw));
drivers/clk/samsung/clk-pll.c
952
pll_con0 = readl_relaxed(pll->con_reg);
drivers/clk/samsung/clk-pll.c
953
pll_con1 = readl_relaxed(pll->con_reg + 0x4);
drivers/clk/samsung/clk-pll.c
986
struct samsung_clk_pll *pll = to_clk_pll(hw);
drivers/clk/samsung/clk-pll.c
990
pll_stat = readl_relaxed(pll->con_reg);
drivers/clk/sophgo/clk-cv18xx-pll.c
135
struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw);
drivers/clk/sophgo/clk-cv18xx-pll.c
137
ipll_find_rate(pll->pll_limit, parent_rate, &rate, &detected);
drivers/clk/sophgo/clk-cv18xx-pll.c
140
pll->pll_limit, &detected);
drivers/clk/sophgo/clk-cv18xx-pll.c
142
spin_lock_irqsave(pll->common.lock, flags);
drivers/clk/sophgo/clk-cv18xx-pll.c
144
regval = readl(pll->common.base + pll->pll_reg);
drivers/clk/sophgo/clk-cv18xx-pll.c
147
writel(regval, pll->common.base + pll->pll_reg);
drivers/clk/sophgo/clk-cv18xx-pll.c
149
spin_unlock_irqrestore(pll->common.lock, flags);
drivers/clk/sophgo/clk-cv18xx-pll.c
151
cv1800_clk_wait_for_lock(&pll->common, pll->pll_status.reg,
drivers/clk/sophgo/clk-cv18xx-pll.c
152
BIT(pll->pll_status.shift));
drivers/clk/sophgo/clk-cv18xx-pll.c
159
struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw);
drivers/clk/sophgo/clk-cv18xx-pll.c
161
return cv1800_clk_clearbit(&pll->common, &pll->pll_pwd);
drivers/clk/sophgo/clk-cv18xx-pll.c
166
struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw);
drivers/clk/sophgo/clk-cv18xx-pll.c
168
cv1800_clk_setbit(&pll->common, &pll->pll_pwd);
drivers/clk/sophgo/clk-cv18xx-pll.c
173
struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw);
drivers/clk/sophgo/clk-cv18xx-pll.c
175
return cv1800_clk_checkbit(&pll->common, &pll->pll_pwd) == 0;
drivers/clk/sophgo/clk-cv18xx-pll.c
191
static bool fpll_is_factional_mode(struct cv1800_clk_pll *pll)
drivers/clk/sophgo/clk-cv18xx-pll.c
193
return cv1800_clk_checkbit(&pll->common, &pll->pll_syn->en);
drivers/clk/sophgo/clk-cv18xx-pll.c
223
struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw);
drivers/clk/sophgo/clk-cv18xx-pll.c
228
if (!fpll_is_factional_mode(pll))
drivers/clk/sophgo/clk-cv18xx-pll.c
231
syn_set = readl(pll->common.base + pll->pll_syn->set);
drivers/clk/sophgo/clk-cv18xx-pll.c
236
clk_full = cv1800_clk_checkbit(&pll->common,
drivers/clk/sophgo/clk-cv18xx-pll.c
237
&pll->pll_syn->clk_half);
drivers/clk/sophgo/clk-cv18xx-pll.c
239
value = readl(pll->common.base + pll->pll_reg);
drivers/clk/sophgo/clk-cv18xx-pll.c
282
static int fpll_find_rate(struct cv1800_clk_pll *pll,
drivers/clk/sophgo/clk-cv18xx-pll.c
294
bool clk_full = cv1800_clk_checkbit(&pll->common,
drivers/clk/sophgo/clk-cv18xx-pll.c
295
&pll->pll_syn->clk_half);
drivers/clk/sophgo/clk-cv18xx-pll.c
329
struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw);
drivers/clk/sophgo/clk-cv18xx-pll.c
332
if (!fpll_is_factional_mode(pll))
drivers/clk/sophgo/clk-cv18xx-pll.c
335
fpll_find_rate(pll, &pll->pll_limit[2], req->best_parent_rate,
drivers/clk/sophgo/clk-cv18xx-pll.c
358
struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw);
drivers/clk/sophgo/clk-cv18xx-pll.c
36
struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw);
drivers/clk/sophgo/clk-cv18xx-pll.c
360
if (!fpll_is_factional_mode(pll))
drivers/clk/sophgo/clk-cv18xx-pll.c
363
fpll_find_rate(pll, &pll->pll_limit[2], parent_rate,
drivers/clk/sophgo/clk-cv18xx-pll.c
367
pll->pll_limit, &detected);
drivers/clk/sophgo/clk-cv18xx-pll.c
369
spin_lock_irqsave(pll->common.lock, flags);
drivers/clk/sophgo/clk-cv18xx-pll.c
371
writel(detected_ssc, pll->common.base + pll->pll_syn->set);
drivers/clk/sophgo/clk-cv18xx-pll.c
373
regval = readl(pll->common.base + pll->pll_reg);
drivers/clk/sophgo/clk-cv18xx-pll.c
376
writel(regval, pll->common.base + pll->pll_reg);
drivers/clk/sophgo/clk-cv18xx-pll.c
378
spin_unlock_irqrestore(pll->common.lock, flags);
drivers/clk/sophgo/clk-cv18xx-pll.c
380
cv1800_clk_wait_for_lock(&pll->common, pll->pll_status.reg,
drivers/clk/sophgo/clk-cv18xx-pll.c
381
BIT(pll->pll_status.shift));
drivers/clk/sophgo/clk-cv18xx-pll.c
388
struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw);
drivers/clk/sophgo/clk-cv18xx-pll.c
39
value = readl(pll->common.base + pll->pll_reg);
drivers/clk/sophgo/clk-cv18xx-pll.c
390
if (fpll_is_factional_mode(pll))
drivers/clk/sophgo/clk-cv18xx-pll.c
398
struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw);
drivers/clk/sophgo/clk-cv18xx-pll.c
401
cv1800_clk_setbit(&pll->common, &pll->pll_syn->en);
drivers/clk/sophgo/clk-cv18xx-pll.c
403
cv1800_clk_clearbit(&pll->common, &pll->pll_syn->en);
drivers/clk/sophgo/clk-cv18xx-pll.c
91
struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw);
drivers/clk/sophgo/clk-cv18xx-pll.c
93
return ipll_find_rate(pll->pll_limit, req->best_parent_rate,
drivers/clk/sophgo/clk-sg2042-pll.c
106
static inline void sg2042_pll_enable(struct sg2042_pll_clock *pll, bool en)
drivers/clk/sophgo/clk-sg2042-pll.c
112
if (readl_poll_timeout_atomic(pll->base + R_PLL_STAT,
drivers/clk/sophgo/clk-sg2042-pll.c
114
((value >> pll->shift_status_lock) & 0x1),
drivers/clk/sophgo/clk-sg2042-pll.c
117
pr_warn("%s not locked\n", pll->hw.init->name);
drivers/clk/sophgo/clk-sg2042-pll.c
120
if (readl_poll_timeout_atomic(pll->base + R_PLL_STAT,
drivers/clk/sophgo/clk-sg2042-pll.c
122
!((value >> pll->shift_status_updating) & 0x1),
drivers/clk/sophgo/clk-sg2042-pll.c
125
pr_warn("%s still updating\n", pll->hw.init->name);
drivers/clk/sophgo/clk-sg2042-pll.c
128
value = readl(pll->base + R_PLL_CLKEN_CONTROL);
drivers/clk/sophgo/clk-sg2042-pll.c
129
writel(value | (1 << pll->shift_enable), pll->base + R_PLL_CLKEN_CONTROL);
drivers/clk/sophgo/clk-sg2042-pll.c
132
value = readl(pll->base + R_PLL_CLKEN_CONTROL);
drivers/clk/sophgo/clk-sg2042-pll.c
133
writel(value & (~(1 << pll->shift_enable)), pll->base + R_PLL_CLKEN_CONTROL);
drivers/clk/sophgo/clk-sg2042-pll.c
337
struct sg2042_pll_clock *pll = to_sg2042_pll_clk(hw);
drivers/clk/sophgo/clk-sg2042-pll.c
341
value = readl(pll->base + pll->offset_ctrl);
drivers/clk/sophgo/clk-sg2042-pll.c
380
struct sg2042_pll_clock *pll = to_sg2042_pll_clk(hw);
drivers/clk/sophgo/clk-sg2042-pll.c
386
spin_lock_irqsave(pll->lock, flags);
drivers/clk/sophgo/clk-sg2042-pll.c
388
sg2042_pll_enable(pll, 0);
drivers/clk/sophgo/clk-sg2042-pll.c
392
pr_warn("%s: Can't find a proper pll setting\n", pll->hw.init->name);
drivers/clk/sophgo/clk-sg2042-pll.c
399
writel(value, pll->base + pll->offset_ctrl);
drivers/clk/sophgo/clk-sg2042-pll.c
402
sg2042_pll_enable(pll, 1);
drivers/clk/sophgo/clk-sg2042-pll.c
404
spin_unlock_irqrestore(pll->lock, flags);
drivers/clk/sophgo/clk-sg2042-pll.c
469
struct sg2042_pll_clock *pll;
drivers/clk/sophgo/clk-sg2042-pll.c
474
pll = &pll_clks[i];
drivers/clk/sophgo/clk-sg2042-pll.c
476
pll->base = clk_data->iobase;
drivers/clk/sophgo/clk-sg2042-pll.c
477
pll->lock = &sg2042_clk_lock;
drivers/clk/sophgo/clk-sg2042-pll.c
479
hw = &pll->hw;
drivers/clk/sophgo/clk-sg2042-pll.c
482
pr_err("failed to register clock %s\n", pll->hw.init->name);
drivers/clk/sophgo/clk-sg2042-pll.c
486
clk_data->onecell_data.hws[pll->id] = hw;
drivers/clk/sophgo/clk-sg2044-pll.c
142
struct sg2044_pll *pll = hw_to_sg2044_pll(hw);
drivers/clk/sophgo/clk-sg2044-pll.c
146
ret = regmap_read(pll->common.regmap,
drivers/clk/sophgo/clk-sg2044-pll.c
147
pll->syscon_offset + pll->pll.ctrl_offset + PLL_HIGH_CTRL_OFFSET,
drivers/clk/sophgo/clk-sg2044-pll.c
263
struct sg2044_pll *pll = hw_to_sg2044_pll(hw);
drivers/clk/sophgo/clk-sg2044-pll.c
268
target = clamp(req->rate, pll->pll.limits[PLL_LIMIT_FOUT].min,
drivers/clk/sophgo/clk-sg2044-pll.c
269
pll->pll.limits[PLL_LIMIT_FOUT].max);
drivers/clk/sophgo/clk-sg2044-pll.c
271
ret = sg2044_compute_pll_setting(pll->pll.limits, target,
drivers/clk/sophgo/clk-sg2044-pll.c
285
static int sg2044_pll_poll_update(struct sg2044_pll *pll)
drivers/clk/sophgo/clk-sg2044-pll.c
290
ret = regmap_read_poll_timeout_atomic(pll->common.regmap,
drivers/clk/sophgo/clk-sg2044-pll.c
291
pll->syscon_offset + pll->pll.status_offset,
drivers/clk/sophgo/clk-sg2044-pll.c
293
(value & BIT(pll->pll.status_lock_bit)),
drivers/clk/sophgo/clk-sg2044-pll.c
298
return regmap_read_poll_timeout_atomic(pll->common.regmap,
drivers/clk/sophgo/clk-sg2044-pll.c
299
pll->syscon_offset + pll->pll.status_offset,
drivers/clk/sophgo/clk-sg2044-pll.c
301
(!(value & BIT(pll->pll.status_updating_bit))),
drivers/clk/sophgo/clk-sg2044-pll.c
305
static int sg2044_pll_enable(struct sg2044_pll *pll, bool en)
drivers/clk/sophgo/clk-sg2044-pll.c
308
if (sg2044_pll_poll_update(pll) < 0)
drivers/clk/sophgo/clk-sg2044-pll.c
309
pr_warn("%s: fail to lock pll\n", clk_hw_get_name(&pll->common.hw));
drivers/clk/sophgo/clk-sg2044-pll.c
311
return regmap_set_bits(pll->common.regmap,
drivers/clk/sophgo/clk-sg2044-pll.c
312
pll->syscon_offset + pll->pll.enable_offset,
drivers/clk/sophgo/clk-sg2044-pll.c
313
BIT(pll->pll.enable_bit));
drivers/clk/sophgo/clk-sg2044-pll.c
316
return regmap_clear_bits(pll->common.regmap,
drivers/clk/sophgo/clk-sg2044-pll.c
317
pll->syscon_offset + pll->pll.enable_offset,
drivers/clk/sophgo/clk-sg2044-pll.c
318
BIT(pll->pll.enable_bit));
drivers/clk/sophgo/clk-sg2044-pll.c
321
static int sg2044_pll_update_vcosel(struct sg2044_pll *pll, u64 rate)
drivers/clk/sophgo/clk-sg2044-pll.c
330
return regmap_write_bits(pll->common.regmap,
drivers/clk/sophgo/clk-sg2044-pll.c
331
pll->syscon_offset + pll->pll.ctrl_offset,
drivers/clk/sophgo/clk-sg2044-pll.c
339
struct sg2044_pll *pll = hw_to_sg2044_pll(hw);
drivers/clk/sophgo/clk-sg2044-pll.c
344
ret = sg2044_compute_pll_setting(pll->pll.limits, rate,
drivers/clk/sophgo/clk-sg2044-pll.c
357
guard(spinlock_irqsave)(pll->common.lock);
drivers/clk/sophgo/clk-sg2044-pll.c
359
ret = sg2044_pll_enable(pll, false);
drivers/clk/sophgo/clk-sg2044-pll.c
363
sg2044_pll_update_vcosel(pll, vco);
drivers/clk/sophgo/clk-sg2044-pll.c
365
regmap_write_bits(pll->common.regmap,
drivers/clk/sophgo/clk-sg2044-pll.c
366
pll->syscon_offset + pll->pll.ctrl_offset +
drivers/clk/sophgo/clk-sg2044-pll.c
370
sg2044_pll_enable(pll, true);
drivers/clk/sophgo/clk-sg2044-pll.c
402
.pll = { \
drivers/clk/sophgo/clk-sg2044-pll.c
423
.pll = { \
drivers/clk/sophgo/clk-sg2044-pll.c
562
struct sg2044_clk_common *common = desc->pll[i];
drivers/clk/sophgo/clk-sg2044-pll.c
563
struct sg2044_pll *pll = hw_to_sg2044_pll(&common->hw);
drivers/clk/sophgo/clk-sg2044-pll.c
567
pll->syscon_offset = SG2044_SYSCON_PLL_OFFSET;
drivers/clk/sophgo/clk-sg2044-pll.c
606
.pll = sg2044_pll_commons,
drivers/clk/sophgo/clk-sg2044-pll.c
85
struct sg2044_pll_internal pll;
drivers/clk/sophgo/clk-sg2044-pll.c
90
struct sg2044_clk_common * const *pll;
drivers/clk/sophgo/clk-sg2044.c
81
struct sg2044_clk_common * const *pll;
drivers/clk/spacemit/ccu_pll.c
109
struct ccu_pll *pll = hw_to_ccu_pll(hw);
drivers/clk/spacemit/ccu_pll.c
112
entry = ccu_pll_lookup_best_rate(pll, rate);
drivers/clk/spacemit/ccu_pll.c
113
ccu_pll_update_param(pll, entry);
drivers/clk/spacemit/ccu_pll.c
121
struct ccu_pll *pll = hw_to_ccu_pll(hw);
drivers/clk/spacemit/ccu_pll.c
124
entry = ccu_pll_lookup_matched_entry(pll);
drivers/clk/spacemit/ccu_pll.c
134
struct ccu_pll *pll = hw_to_ccu_pll(hw);
drivers/clk/spacemit/ccu_pll.c
136
req->rate = ccu_pll_lookup_best_rate(pll, req->rate)->rate;
drivers/clk/spacemit/ccu_pll.c
143
struct ccu_pll *pll = hw_to_ccu_pll(hw);
drivers/clk/spacemit/ccu_pll.c
145
if (ccu_pll_lookup_matched_entry(pll))
drivers/clk/spacemit/ccu_pll.c
149
ccu_pll_update_param(pll, &pll->config.rate_tbl[0]);
drivers/clk/spacemit/ccu_pll.c
154
static const struct ccu_pll_rate_tbl *ccu_plla_lookup_matched_entry(struct ccu_pll *pll)
drivers/clk/spacemit/ccu_pll.c
156
struct ccu_pll_config *config = &pll->config;
drivers/clk/spacemit/ccu_pll.c
160
swcr1 = ccu_read(&pll->common, swcr1);
drivers/clk/spacemit/ccu_pll.c
161
swcr2 = ccu_read(&pll->common, swcr2);
drivers/clk/spacemit/ccu_pll.c
163
swcr3 = ccu_read(&pll->common, swcr3);
drivers/clk/spacemit/ccu_pll.c
177
static void ccu_plla_update_param(struct ccu_pll *pll, const struct ccu_pll_rate_tbl *entry)
drivers/clk/spacemit/ccu_pll.c
179
struct ccu_common *common = &pll->common;
drivers/clk/spacemit/ccu_pll.c
195
struct ccu_pll *pll = hw_to_ccu_pll(hw);
drivers/clk/spacemit/ccu_pll.c
196
struct ccu_common *common = &pll->common;
drivers/clk/spacemit/ccu_pll.c
203
pll->config.reg_lock,
drivers/clk/spacemit/ccu_pll.c
205
tmp & pll->config.mask_lock,
drivers/clk/spacemit/ccu_pll.c
223
struct ccu_pll *pll = hw_to_ccu_pll(hw);
drivers/clk/spacemit/ccu_pll.c
226
entry = ccu_pll_lookup_best_rate(pll, rate);
drivers/clk/spacemit/ccu_pll.c
227
ccu_plla_update_param(pll, entry);
drivers/clk/spacemit/ccu_pll.c
23
static const struct ccu_pll_rate_tbl *ccu_pll_lookup_best_rate(struct ccu_pll *pll,
drivers/clk/spacemit/ccu_pll.c
235
struct ccu_pll *pll = hw_to_ccu_pll(hw);
drivers/clk/spacemit/ccu_pll.c
238
entry = ccu_plla_lookup_matched_entry(pll);
drivers/clk/spacemit/ccu_pll.c
247
struct ccu_pll *pll = hw_to_ccu_pll(hw);
drivers/clk/spacemit/ccu_pll.c
249
if (ccu_plla_lookup_matched_entry(pll))
drivers/clk/spacemit/ccu_pll.c
253
ccu_plla_update_param(pll, &pll->config.rate_tbl[0]);
drivers/clk/spacemit/ccu_pll.c
26
struct ccu_pll_config *config = &pll->config;
drivers/clk/spacemit/ccu_pll.c
44
static const struct ccu_pll_rate_tbl *ccu_pll_lookup_matched_entry(struct ccu_pll *pll)
drivers/clk/spacemit/ccu_pll.c
46
struct ccu_pll_config *config = &pll->config;
drivers/clk/spacemit/ccu_pll.c
50
swcr1 = ccu_read(&pll->common, swcr1);
drivers/clk/spacemit/ccu_pll.c
51
swcr3 = ccu_read(&pll->common, swcr3);
drivers/clk/spacemit/ccu_pll.c
64
static void ccu_pll_update_param(struct ccu_pll *pll, const struct ccu_pll_rate_tbl *entry)
drivers/clk/spacemit/ccu_pll.c
66
struct ccu_common *common = &pll->common;
drivers/clk/spacemit/ccu_pll.c
81
struct ccu_pll *pll = hw_to_ccu_pll(hw);
drivers/clk/spacemit/ccu_pll.c
82
struct ccu_common *common = &pll->common;
drivers/clk/spacemit/ccu_pll.c
89
pll->config.reg_lock,
drivers/clk/spacemit/ccu_pll.c
91
tmp & pll->config.mask_lock,
drivers/clk/spear/clk-vco-pll.c
127
struct clk_pll *pll = to_clk_pll(hw);
drivers/clk/spear/clk-vco-pll.c
131
if (pll->vco->lock)
drivers/clk/spear/clk-vco-pll.c
132
spin_lock_irqsave(pll->vco->lock, flags);
drivers/clk/spear/clk-vco-pll.c
134
p = readl_relaxed(pll->vco->cfg_reg);
drivers/clk/spear/clk-vco-pll.c
136
if (pll->vco->lock)
drivers/clk/spear/clk-vco-pll.c
137
spin_unlock_irqrestore(pll->vco->lock, flags);
drivers/clk/spear/clk-vco-pll.c
147
struct clk_pll *pll = to_clk_pll(hw);
drivers/clk/spear/clk-vco-pll.c
148
struct pll_rate_tbl *rtbl = pll->vco->rtbl;
drivers/clk/spear/clk-vco-pll.c
154
if (pll->vco->lock)
drivers/clk/spear/clk-vco-pll.c
155
spin_lock_irqsave(pll->vco->lock, flags);
drivers/clk/spear/clk-vco-pll.c
157
val = readl_relaxed(pll->vco->cfg_reg);
drivers/clk/spear/clk-vco-pll.c
160
writel_relaxed(val, pll->vco->cfg_reg);
drivers/clk/spear/clk-vco-pll.c
162
if (pll->vco->lock)
drivers/clk/spear/clk-vco-pll.c
163
spin_unlock_irqrestore(pll->vco->lock, flags);
drivers/clk/spear/clk-vco-pll.c
285
struct clk_pll *pll;
drivers/clk/spear/clk-vco-pll.c
300
pll = kzalloc_obj(*pll);
drivers/clk/spear/clk-vco-pll.c
301
if (!pll)
drivers/clk/spear/clk-vco-pll.c
312
pll->vco = vco;
drivers/clk/spear/clk-vco-pll.c
313
pll->hw.init = &pll_init;
drivers/clk/spear/clk-vco-pll.c
344
tpll_clk = clk_register(NULL, &pll->hw);
drivers/clk/spear/clk-vco-pll.c
356
kfree(pll);
drivers/clk/spear/clk-vco-pll.c
84
struct clk_pll *pll = to_clk_pll(hw);
drivers/clk/spear/clk-vco-pll.c
94
for (*index = 0; *index < pll->vco->rtbl_cnt; (*index)++) {
drivers/clk/spear/clk-vco-pll.c
97
*prate = pll_calc_rate(pll->vco->rtbl, vco_parent_rate, *index,
drivers/clk/sprd/pll.c
102
u32 i, mask, regs_num = pll->regs_num;
drivers/clk/sprd/pll.c
112
cfg[i] = sprd_pll_read(pll, i);
drivers/clk/sprd/pll.c
114
refin = pll_get_refin(pll);
drivers/clk/sprd/pll.c
116
if (pinternal(pll, cfg, PLL_PREDIV))
drivers/clk/sprd/pll.c
119
if (pwidth(pll, PLL_POSTDIV) &&
drivers/clk/sprd/pll.c
120
((pll->fflag == 1 && pinternal(pll, cfg, PLL_POSTDIV)) ||
drivers/clk/sprd/pll.c
121
(!pll->fflag && !pinternal(pll, cfg, PLL_POSTDIV))))
drivers/clk/sprd/pll.c
124
if (!pinternal(pll, cfg, PLL_DIV_S)) {
drivers/clk/sprd/pll.c
125
rate = refin * pinternal_val(pll, cfg, PLL_N) * CLK_PLL_10M;
drivers/clk/sprd/pll.c
127
nint = pinternal_val(pll, cfg, PLL_NINT);
drivers/clk/sprd/pll.c
128
if (pinternal(pll, cfg, PLL_SDM_EN))
drivers/clk/sprd/pll.c
129
kint = pinternal_val(pll, cfg, PLL_KINT);
drivers/clk/sprd/pll.c
131
mask = pmask(pll, PLL_KINT);
drivers/clk/sprd/pll.c
133
k1 = pll->k1;
drivers/clk/sprd/pll.c
134
k2 = pll->k2;
drivers/clk/sprd/pll.c
144
#define SPRD_PLL_WRITE_CHECK(pll, i, mask, val) \
drivers/clk/sprd/pll.c
145
(((sprd_pll_read(pll, i) & mask) == val) ? 0 : (-EFAULT))
drivers/clk/sprd/pll.c
147
static int _sprd_pll_set_rate(const struct sprd_pll *pll,
drivers/clk/sprd/pll.c
154
u32 regs_num = pll->regs_num, i = 0;
drivers/clk/sprd/pll.c
162
refin = pll_get_refin(pll);
drivers/clk/sprd/pll.c
164
mask = pmask(pll, PLL_PREDIV);
drivers/clk/sprd/pll.c
165
index = pindex(pll, PLL_PREDIV);
drivers/clk/sprd/pll.c
166
width = pwidth(pll, PLL_PREDIV);
drivers/clk/sprd/pll.c
167
if (width && (sprd_pll_read(pll, index) & mask))
drivers/clk/sprd/pll.c
170
mask = pmask(pll, PLL_POSTDIV);
drivers/clk/sprd/pll.c
171
index = pindex(pll, PLL_POSTDIV);
drivers/clk/sprd/pll.c
172
width = pwidth(pll, PLL_POSTDIV);
drivers/clk/sprd/pll.c
174
if (width && ((pll->fflag == 1 && fvco <= pll->fvco) ||
drivers/clk/sprd/pll.c
175
(pll->fflag == 0 && fvco > pll->fvco)))
drivers/clk/sprd/pll.c
178
if (width && fvco <= pll->fvco)
drivers/clk/sprd/pll.c
18
#define pindex(pll, member) \
drivers/clk/sprd/pll.c
181
mask = pmask(pll, PLL_DIV_S);
drivers/clk/sprd/pll.c
182
index = pindex(pll, PLL_DIV_S);
drivers/clk/sprd/pll.c
186
mask = pmask(pll, PLL_SDM_EN);
drivers/clk/sprd/pll.c
187
index = pindex(pll, PLL_SDM_EN);
drivers/clk/sprd/pll.c
19
(pll->factors[member].shift / (8 * sizeof(pll->regs_num)))
drivers/clk/sprd/pll.c
192
mask = pmask(pll, PLL_NINT);
drivers/clk/sprd/pll.c
193
index = pindex(pll, PLL_NINT);
drivers/clk/sprd/pll.c
194
shift = pshift(pll, PLL_NINT);
drivers/clk/sprd/pll.c
198
mask = pmask(pll, PLL_KINT);
drivers/clk/sprd/pll.c
199
index = pindex(pll, PLL_KINT);
drivers/clk/sprd/pll.c
200
width = pwidth(pll, PLL_KINT);
drivers/clk/sprd/pll.c
201
shift = pshift(pll, PLL_KINT);
drivers/clk/sprd/pll.c
208
ibias_val = pll_get_ibias(fvco, pll->itable);
drivers/clk/sprd/pll.c
21
#define pshift(pll, member) \
drivers/clk/sprd/pll.c
210
mask = pmask(pll, PLL_IBIAS);
drivers/clk/sprd/pll.c
211
index = pindex(pll, PLL_IBIAS);
drivers/clk/sprd/pll.c
212
shift = pshift(pll, PLL_IBIAS);
drivers/clk/sprd/pll.c
218
sprd_pll_write(pll, i, cfg[i].msk, cfg[i].val);
drivers/clk/sprd/pll.c
219
ret |= SPRD_PLL_WRITE_CHECK(pll, i, cfg[i].msk,
drivers/clk/sprd/pll.c
22
(pll->factors[member].shift % (8 * sizeof(pll->regs_num)))
drivers/clk/sprd/pll.c
225
udelay(pll->udelay);
drivers/clk/sprd/pll.c
234
struct sprd_pll *pll = hw_to_sprd_pll(hw);
drivers/clk/sprd/pll.c
236
return _sprd_pll_recalc_rate(pll, parent_rate);
drivers/clk/sprd/pll.c
24
#define pwidth(pll, member) \
drivers/clk/sprd/pll.c
243
struct sprd_pll *pll = hw_to_sprd_pll(hw);
drivers/clk/sprd/pll.c
245
return _sprd_pll_set_rate(pll, rate, parent_rate);
drivers/clk/sprd/pll.c
25
pll->factors[member].width
drivers/clk/sprd/pll.c
250
struct sprd_pll *pll = hw_to_sprd_pll(hw);
drivers/clk/sprd/pll.c
252
udelay(pll->udelay);
drivers/clk/sprd/pll.c
27
#define pmask(pll, member) \
drivers/clk/sprd/pll.c
28
((pwidth(pll, member)) ? \
drivers/clk/sprd/pll.c
29
GENMASK(pwidth(pll, member) + pshift(pll, member) - 1, \
drivers/clk/sprd/pll.c
30
pshift(pll, member)) : 0)
drivers/clk/sprd/pll.c
32
#define pinternal(pll, cfg, member) \
drivers/clk/sprd/pll.c
33
(cfg[pindex(pll, member)] & pmask(pll, member))
drivers/clk/sprd/pll.c
35
#define pinternal_val(pll, cfg, member) \
drivers/clk/sprd/pll.c
36
(pinternal(pll, cfg, member) >> pshift(pll, member))
drivers/clk/sprd/pll.c
39
sprd_pll_read(const struct sprd_pll *pll, u8 index)
drivers/clk/sprd/pll.c
41
const struct sprd_clk_common *common = &pll->common;
drivers/clk/sprd/pll.c
44
if (WARN_ON(index >= pll->regs_num))
drivers/clk/sprd/pll.c
53
sprd_pll_write(const struct sprd_pll *pll, u8 index,
drivers/clk/sprd/pll.c
56
const struct sprd_clk_common *common = &pll->common;
drivers/clk/sprd/pll.c
60
if (WARN_ON(index >= pll->regs_num))
drivers/clk/sprd/pll.c
69
static unsigned long pll_get_refin(const struct sprd_pll *pll)
drivers/clk/sprd/pll.c
74
if (pwidth(pll, PLL_REFIN)) {
drivers/clk/sprd/pll.c
75
index = pindex(pll, PLL_REFIN);
drivers/clk/sprd/pll.c
76
shift = pshift(pll, PLL_REFIN);
drivers/clk/sprd/pll.c
77
mask = pmask(pll, PLL_REFIN);
drivers/clk/sprd/pll.c
78
refin_id = (sprd_pll_read(pll, index) & mask) >> shift;
drivers/clk/sprd/pll.c
98
static unsigned long _sprd_pll_recalc_rate(const struct sprd_pll *pll,
drivers/clk/st/clkgen-fsyn.c
254
struct st_clk_quadfs_pll *pll = to_quadfs_pll(hw);
drivers/clk/st/clkgen-fsyn.c
257
if (pll->lock)
drivers/clk/st/clkgen-fsyn.c
258
spin_lock_irqsave(pll->lock, flags);
drivers/clk/st/clkgen-fsyn.c
263
if (pll->data->reset_present)
drivers/clk/st/clkgen-fsyn.c
264
CLKGEN_WRITE(pll, nreset, 1);
drivers/clk/st/clkgen-fsyn.c
269
if (pll->data->bwfilter_present)
drivers/clk/st/clkgen-fsyn.c
270
CLKGEN_WRITE(pll, ref_bw, PLL_BW_GOODREF);
drivers/clk/st/clkgen-fsyn.c
273
CLKGEN_WRITE(pll, ndiv, pll->ndiv);
drivers/clk/st/clkgen-fsyn.c
278
CLKGEN_WRITE(pll, npda, !pll->data->powerup_polarity);
drivers/clk/st/clkgen-fsyn.c
280
if (pll->lock)
drivers/clk/st/clkgen-fsyn.c
281
spin_unlock_irqrestore(pll->lock, flags);
drivers/clk/st/clkgen-fsyn.c
283
if (pll->data->lockstatus_present)
drivers/clk/st/clkgen-fsyn.c
284
while (!CLKGEN_READ(pll, lock_status)) {
drivers/clk/st/clkgen-fsyn.c
295
struct st_clk_quadfs_pll *pll = to_quadfs_pll(hw);
drivers/clk/st/clkgen-fsyn.c
298
if (pll->lock)
drivers/clk/st/clkgen-fsyn.c
299
spin_lock_irqsave(pll->lock, flags);
drivers/clk/st/clkgen-fsyn.c
305
CLKGEN_WRITE(pll, npda, pll->data->powerup_polarity);
drivers/clk/st/clkgen-fsyn.c
307
if (pll->data->reset_present)
drivers/clk/st/clkgen-fsyn.c
308
CLKGEN_WRITE(pll, nreset, 0);
drivers/clk/st/clkgen-fsyn.c
310
if (pll->lock)
drivers/clk/st/clkgen-fsyn.c
311
spin_unlock_irqrestore(pll->lock, flags);
drivers/clk/st/clkgen-fsyn.c
316
struct st_clk_quadfs_pll *pll = to_quadfs_pll(hw);
drivers/clk/st/clkgen-fsyn.c
317
u32 npda = CLKGEN_READ(pll, npda);
drivers/clk/st/clkgen-fsyn.c
319
return pll->data->powerup_polarity ? !npda : !!npda;
drivers/clk/st/clkgen-fsyn.c
335
struct st_clk_quadfs_pll *pll = to_quadfs_pll(hw);
drivers/clk/st/clkgen-fsyn.c
339
params.ndiv = CLKGEN_READ(pll, ndiv);
drivers/clk/st/clkgen-fsyn.c
344
pll->ndiv = params.ndiv;
drivers/clk/st/clkgen-fsyn.c
398
struct st_clk_quadfs_pll *pll = to_quadfs_pll(hw);
drivers/clk/st/clkgen-fsyn.c
420
pll->ndiv = params.ndiv;
drivers/clk/st/clkgen-fsyn.c
422
if (pll->lock)
drivers/clk/st/clkgen-fsyn.c
423
spin_lock_irqsave(pll->lock, flags);
drivers/clk/st/clkgen-fsyn.c
425
CLKGEN_WRITE(pll, ndiv, pll->ndiv);
drivers/clk/st/clkgen-fsyn.c
427
if (pll->lock)
drivers/clk/st/clkgen-fsyn.c
428
spin_unlock_irqrestore(pll->lock, flags);
drivers/clk/st/clkgen-fsyn.c
447
struct st_clk_quadfs_pll *pll;
drivers/clk/st/clkgen-fsyn.c
457
pll = kzalloc_obj(*pll);
drivers/clk/st/clkgen-fsyn.c
458
if (!pll)
drivers/clk/st/clkgen-fsyn.c
467
pll->data = quadfs;
drivers/clk/st/clkgen-fsyn.c
468
pll->regs_base = reg;
drivers/clk/st/clkgen-fsyn.c
469
pll->lock = lock;
drivers/clk/st/clkgen-fsyn.c
470
pll->hw.init = &init;
drivers/clk/st/clkgen-fsyn.c
472
clk = clk_register(NULL, &pll->hw);
drivers/clk/st/clkgen-fsyn.c
475
kfree(pll);
drivers/clk/st/clkgen-pll.c
230
struct clkgen_pll *pll = to_clkgen_pll(hw);
drivers/clk/st/clkgen-pll.c
231
u32 locked = CLKGEN_READ(pll, locked_status);
drivers/clk/st/clkgen-pll.c
238
struct clkgen_pll *pll = to_clkgen_pll(hw);
drivers/clk/st/clkgen-pll.c
239
u32 poweroff = CLKGEN_READ(pll, pdn_status);
drivers/clk/st/clkgen-pll.c
245
struct clkgen_pll *pll = to_clkgen_pll(hw);
drivers/clk/st/clkgen-pll.c
246
void __iomem *base = pll->regs_base;
drivers/clk/st/clkgen-pll.c
247
struct clkgen_field *field = &pll->data->locked_status;
drivers/clk/st/clkgen-pll.c
254
CLKGEN_WRITE(pll, pdn_ctrl, 0);
drivers/clk/st/clkgen-pll.c
260
if (pll->data->switch2pll_en)
drivers/clk/st/clkgen-pll.c
261
CLKGEN_WRITE(pll, switch2pll, 0);
drivers/clk/st/clkgen-pll.c
271
struct clkgen_pll *pll = to_clkgen_pll(hw);
drivers/clk/st/clkgen-pll.c
275
if (pll->lock)
drivers/clk/st/clkgen-pll.c
276
spin_lock_irqsave(pll->lock, flags);
drivers/clk/st/clkgen-pll.c
280
if (pll->lock)
drivers/clk/st/clkgen-pll.c
281
spin_unlock_irqrestore(pll->lock, flags);
drivers/clk/st/clkgen-pll.c
288
struct clkgen_pll *pll = to_clkgen_pll(hw);
drivers/clk/st/clkgen-pll.c
293
if (pll->data->switch2pll_en)
drivers/clk/st/clkgen-pll.c
294
CLKGEN_WRITE(pll, switch2pll, 1);
drivers/clk/st/clkgen-pll.c
296
CLKGEN_WRITE(pll, pdn_ctrl, 1);
drivers/clk/st/clkgen-pll.c
303
struct clkgen_pll *pll = to_clkgen_pll(hw);
drivers/clk/st/clkgen-pll.c
306
if (pll->lock)
drivers/clk/st/clkgen-pll.c
307
spin_lock_irqsave(pll->lock, flags);
drivers/clk/st/clkgen-pll.c
311
if (pll->lock)
drivers/clk/st/clkgen-pll.c
312
spin_unlock_irqrestore(pll->lock, flags);
drivers/clk/st/clkgen-pll.c
316
struct stm_pll *pll)
drivers/clk/st/clkgen-pll.c
349
pll->idf = i;
drivers/clk/st/clkgen-pll.c
350
pll->ndiv = n;
drivers/clk/st/clkgen-pll.c
359
for (pll->cp = 6; pll->ndiv > cp_table[pll->cp-6]; (pll->cp)++)
drivers/clk/st/clkgen-pll.c
365
static int clk_pll3200c32_get_rate(unsigned long input, struct stm_pll *pll,
drivers/clk/st/clkgen-pll.c
368
if (!pll->idf)
drivers/clk/st/clkgen-pll.c
369
pll->idf = 1;
drivers/clk/st/clkgen-pll.c
371
*rate = ((2 * (input / 1000) * pll->ndiv) / pll->idf) * 1000;
drivers/clk/st/clkgen-pll.c
379
struct clkgen_pll *pll = to_clkgen_pll(hw);
drivers/clk/st/clkgen-pll.c
386
ndiv = CLKGEN_READ(pll, ndiv);
drivers/clk/st/clkgen-pll.c
387
idf = CLKGEN_READ(pll, idf);
drivers/clk/st/clkgen-pll.c
425
struct clkgen_pll *pll = to_clkgen_pll(hw);
drivers/clk/st/clkgen-pll.c
444
pll->ndiv = params.ndiv;
drivers/clk/st/clkgen-pll.c
445
pll->idf = params.idf;
drivers/clk/st/clkgen-pll.c
446
pll->cp = params.cp;
drivers/clk/st/clkgen-pll.c
450
if (pll->lock)
drivers/clk/st/clkgen-pll.c
451
spin_lock_irqsave(pll->lock, flags);
drivers/clk/st/clkgen-pll.c
453
CLKGEN_WRITE(pll, ndiv, pll->ndiv);
drivers/clk/st/clkgen-pll.c
454
CLKGEN_WRITE(pll, idf, pll->idf);
drivers/clk/st/clkgen-pll.c
455
CLKGEN_WRITE(pll, cp, pll->cp);
drivers/clk/st/clkgen-pll.c
457
if (pll->lock)
drivers/clk/st/clkgen-pll.c
458
spin_unlock_irqrestore(pll->lock, flags);
drivers/clk/st/clkgen-pll.c
480
struct stm_pll *pll)
drivers/clk/st/clkgen-pll.c
511
pll->idf = i;
drivers/clk/st/clkgen-pll.c
512
pll->ndiv = n;
drivers/clk/st/clkgen-pll.c
524
static int clk_pll4600c28_get_rate(unsigned long input, struct stm_pll *pll,
drivers/clk/st/clkgen-pll.c
527
if (!pll->idf)
drivers/clk/st/clkgen-pll.c
528
pll->idf = 1;
drivers/clk/st/clkgen-pll.c
530
*rate = (input / pll->idf) * 2 * pll->ndiv;
drivers/clk/st/clkgen-pll.c
538
struct clkgen_pll *pll = to_clkgen_pll(hw);
drivers/clk/st/clkgen-pll.c
545
params.ndiv = CLKGEN_READ(pll, ndiv);
drivers/clk/st/clkgen-pll.c
546
params.idf = CLKGEN_READ(pll, idf);
drivers/clk/st/clkgen-pll.c
582
struct clkgen_pll *pll = to_clkgen_pll(hw);
drivers/clk/st/clkgen-pll.c
606
pll->ndiv = params.ndiv;
drivers/clk/st/clkgen-pll.c
607
pll->idf = params.idf;
drivers/clk/st/clkgen-pll.c
611
if (pll->lock)
drivers/clk/st/clkgen-pll.c
612
spin_lock_irqsave(pll->lock, flags);
drivers/clk/st/clkgen-pll.c
614
CLKGEN_WRITE(pll, ndiv, pll->ndiv);
drivers/clk/st/clkgen-pll.c
615
CLKGEN_WRITE(pll, idf, pll->idf);
drivers/clk/st/clkgen-pll.c
617
if (pll->lock)
drivers/clk/st/clkgen-pll.c
618
spin_unlock_irqrestore(pll->lock, flags);
drivers/clk/st/clkgen-pll.c
655
struct clkgen_pll *pll;
drivers/clk/st/clkgen-pll.c
659
pll = kzalloc_obj(*pll);
drivers/clk/st/clkgen-pll.c
660
if (!pll)
drivers/clk/st/clkgen-pll.c
670
pll->data = pll_data;
drivers/clk/st/clkgen-pll.c
671
pll->regs_base = reg;
drivers/clk/st/clkgen-pll.c
672
pll->hw.init = &init;
drivers/clk/st/clkgen-pll.c
673
pll->lock = lock;
drivers/clk/st/clkgen-pll.c
675
clk = clk_register(NULL, &pll->hw);
drivers/clk/st/clkgen-pll.c
677
kfree(pll);
drivers/clk/st/clkgen.h
44
#define CLKGEN_READ(pll, field) clkgen_read(pll->regs_base, \
drivers/clk/st/clkgen.h
45
&pll->data->field)
drivers/clk/st/clkgen.h
47
#define CLKGEN_WRITE(pll, field, val) clkgen_write(pll->regs_base, \
drivers/clk/st/clkgen.h
48
&pll->data->field, val)
drivers/clk/starfive/clk-starfive-jh7100.c
278
return priv->pll[idx - JH7100_CLK_PLL0_OUT];
drivers/clk/starfive/clk-starfive-jh7100.c
299
priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out",
drivers/clk/starfive/clk-starfive-jh7100.c
301
if (IS_ERR(priv->pll[0]))
drivers/clk/starfive/clk-starfive-jh7100.c
302
return PTR_ERR(priv->pll[0]);
drivers/clk/starfive/clk-starfive-jh7100.c
304
priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out",
drivers/clk/starfive/clk-starfive-jh7100.c
306
if (IS_ERR(priv->pll[1]))
drivers/clk/starfive/clk-starfive-jh7100.c
307
return PTR_ERR(priv->pll[1]);
drivers/clk/starfive/clk-starfive-jh7100.c
309
priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out",
drivers/clk/starfive/clk-starfive-jh7100.c
311
if (IS_ERR(priv->pll[2]))
drivers/clk/starfive/clk-starfive-jh7100.c
312
return PTR_ERR(priv->pll[2]);
drivers/clk/starfive/clk-starfive-jh7100.c
333
parents[i].hw = priv->pll[pidx - JH7100_CLK_PLL0_OUT];
drivers/clk/starfive/clk-starfive-jh7110-pll.c
143
struct jh7110_pll_data pll[JH7110_PLLCLK_END];
drivers/clk/starfive/clk-starfive-jh7110-pll.c
273
static struct jh7110_pll_priv *jh7110_pll_priv_from(struct jh7110_pll_data *pll)
drivers/clk/starfive/clk-starfive-jh7110-pll.c
275
return container_of(pll, struct jh7110_pll_priv, pll[pll->idx]);
drivers/clk/starfive/clk-starfive-jh7110-pll.c
301
struct jh7110_pll_data *pll = jh7110_pll_data_from(hw);
drivers/clk/starfive/clk-starfive-jh7110-pll.c
302
struct jh7110_pll_priv *priv = jh7110_pll_priv_from(pll);
drivers/clk/starfive/clk-starfive-jh7110-pll.c
306
jh7110_pll_regvals_get(priv->regmap, &jh7110_plls[pll->idx], &val);
drivers/clk/starfive/clk-starfive-jh7110-pll.c
330
struct jh7110_pll_data *pll = jh7110_pll_data_from(hw);
drivers/clk/starfive/clk-starfive-jh7110-pll.c
331
const struct jh7110_pll_info *info = &jh7110_plls[pll->idx];
drivers/clk/starfive/clk-starfive-jh7110-pll.c
358
struct jh7110_pll_data *pll = jh7110_pll_data_from(hw);
drivers/clk/starfive/clk-starfive-jh7110-pll.c
359
struct jh7110_pll_priv *priv = jh7110_pll_priv_from(pll);
drivers/clk/starfive/clk-starfive-jh7110-pll.c
360
const struct jh7110_pll_info *info = &jh7110_plls[pll->idx];
drivers/clk/starfive/clk-starfive-jh7110-pll.c
396
struct jh7110_pll_data *pll = s->private;
drivers/clk/starfive/clk-starfive-jh7110-pll.c
397
struct jh7110_pll_priv *priv = jh7110_pll_priv_from(pll);
drivers/clk/starfive/clk-starfive-jh7110-pll.c
400
jh7110_pll_regvals_get(priv->regmap, &jh7110_plls[pll->idx], &val);
drivers/clk/starfive/clk-starfive-jh7110-pll.c
429
struct jh7110_pll_data *pll = jh7110_pll_data_from(hw);
drivers/clk/starfive/clk-starfive-jh7110-pll.c
431
debugfs_create_file("registers", 0400, dentry, pll,
drivers/clk/starfive/clk-starfive-jh7110-pll.c
451
return &priv->pll[idx].hw;
drivers/clk/starfive/clk-starfive-jh7110-pll.c
482
struct jh7110_pll_data *pll = &priv->pll[idx];
drivers/clk/starfive/clk-starfive-jh7110-pll.c
484
pll->hw.init = &init;
drivers/clk/starfive/clk-starfive-jh7110-pll.c
485
pll->idx = idx;
drivers/clk/starfive/clk-starfive-jh7110-pll.c
487
ret = devm_clk_hw_register(&pdev->dev, &pll->hw);
drivers/clk/starfive/clk-starfive-jh7110-sys.c
427
priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out",
drivers/clk/starfive/clk-starfive-jh7110-sys.c
429
if (IS_ERR(priv->pll[0]))
drivers/clk/starfive/clk-starfive-jh7110-sys.c
430
return PTR_ERR(priv->pll[0]);
drivers/clk/starfive/clk-starfive-jh7110-sys.c
436
priv->pll[0] = NULL;
drivers/clk/starfive/clk-starfive-jh7110-sys.c
442
priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out",
drivers/clk/starfive/clk-starfive-jh7110-sys.c
444
if (IS_ERR(priv->pll[1]))
drivers/clk/starfive/clk-starfive-jh7110-sys.c
445
return PTR_ERR(priv->pll[1]);
drivers/clk/starfive/clk-starfive-jh7110-sys.c
448
priv->pll[1] = NULL;
drivers/clk/starfive/clk-starfive-jh7110-sys.c
454
priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out",
drivers/clk/starfive/clk-starfive-jh7110-sys.c
456
if (IS_ERR(priv->pll[2]))
drivers/clk/starfive/clk-starfive-jh7110-sys.c
457
return PTR_ERR(priv->pll[2]);
drivers/clk/starfive/clk-starfive-jh7110-sys.c
460
priv->pll[2] = NULL;
drivers/clk/starfive/clk-starfive-jh7110-sys.c
500
else if (pidx == JH7110_SYSCLK_PLL0_OUT && !priv->pll[0])
drivers/clk/starfive/clk-starfive-jh7110-sys.c
502
else if (pidx == JH7110_SYSCLK_PLL1_OUT && !priv->pll[1])
drivers/clk/starfive/clk-starfive-jh7110-sys.c
504
else if (pidx == JH7110_SYSCLK_PLL2_OUT && !priv->pll[2])
drivers/clk/starfive/clk-starfive-jh7110-sys.c
507
parents[i].hw = priv->pll[pidx - JH7110_SYSCLK_PLL0_OUT];
drivers/clk/starfive/clk-starfive-jh71x0.h
119
struct clk_hw *pll[3];
drivers/clk/sunxi-ng/ccu_common.c
85
struct ccu_pll_nb *pll = to_ccu_pll_nb(nb);
drivers/clk/sunxi-ng/ccu_common.c
91
ccu_gate_helper_disable(pll->common, pll->enable);
drivers/clk/sunxi-ng/ccu_common.c
93
ret = ccu_gate_helper_enable(pll->common, pll->enable);
drivers/clk/sunxi-ng/ccu_common.c
97
ccu_helper_wait_for_lock(pll->common, pll->lock);
drivers/clk/tegra/clk-pll.c
1002
val = pll_readl_misc(pll);
drivers/clk/tegra/clk-pll.c
1005
pll_writel_misc(val, pll);
drivers/clk/tegra/clk-pll.c
1007
val = readl(pll->clk_base + PLLE_SS_CTRL);
drivers/clk/tegra/clk-pll.c
1010
writel(val, pll->clk_base + PLLE_SS_CTRL);
drivers/clk/tegra/clk-pll.c
1012
val = pll_readl_base(pll);
drivers/clk/tegra/clk-pll.c
1014
pll_writel_base(val, pll);
drivers/clk/tegra/clk-pll.c
1016
clk_pll_wait_for_lock(pll);
drivers/clk/tegra/clk-pll.c
1024
struct tegra_clk_pll *pll = to_clk_pll(hw);
drivers/clk/tegra/clk-pll.c
1025
u32 val = pll_readl_base(pll);
drivers/clk/tegra/clk-pll.c
1029
divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll));
drivers/clk/tegra/clk-pll.c
1030
divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll));
drivers/clk/tegra/clk-pll.c
1031
divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll));
drivers/clk/tegra/clk-pll.c
1041
struct tegra_clk_pll *pll = to_clk_pll(hw);
drivers/clk/tegra/clk-pll.c
1049
if (pll->params->set_defaults)
drivers/clk/tegra/clk-pll.c
1050
pll->params->set_defaults(pll);
drivers/clk/tegra/clk-pll.c
1123
struct tegra_clk_pll *pll = to_clk_pll(hw);
drivers/clk/tegra/clk-pll.c
1139
if (pll->lock)
drivers/clk/tegra/clk-pll.c
1140
spin_lock_irqsave(pll->lock, flags);
drivers/clk/tegra/clk-pll.c
1145
ret = clk_pll_wait_for_lock(pll);
drivers/clk/tegra/clk-pll.c
1163
value = pll_readl_base(pll);
drivers/clk/tegra/clk-pll.c
1165
pll_writel_base(value, pll);
drivers/clk/tegra/clk-pll.c
1167
value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
drivers/clk/tegra/clk-pll.c
1177
writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
drivers/clk/tegra/clk-pll.c
1179
value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
drivers/clk/tegra/clk-pll.c
1189
writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
drivers/clk/tegra/clk-pll.c
1192
if (pll->lock)
drivers/clk/tegra/clk-pll.c
1193
spin_unlock_irqrestore(pll->lock, flags);
drivers/clk/tegra/clk-pll.c
1229
struct tegra_clk_pll *pll = to_clk_pll(hw);
drivers/clk/tegra/clk-pll.c
1236
p = DIV_ROUND_UP(pll->params->vco_min, rate);
drivers/clk/tegra/clk-pll.c
1237
cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);
drivers/clk/tegra/clk-pll.c
1248
if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)
drivers/clk/tegra/clk-pll.c
1261
struct tegra_clk_pll *pll = to_clk_pll(hw);
drivers/clk/tegra/clk-pll.c
1263
return (u16)_pll_fixed_mdiv(pll->params, input_rate);
drivers/clk/tegra/clk-pll.c
1312
struct tegra_clk_pll *pll = to_clk_pll(hw);
drivers/clk/tegra/clk-pll.c
1319
if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {
drivers/clk/tegra/clk-pll.c
1326
if (cfg->p > pll->params->max_p)
drivers/clk/tegra/clk-pll.c
1336
struct tegra_clk_pll *pll = to_clk_pll(hw);
drivers/clk/tegra/clk-pll.c
1345
if (pll->lock)
drivers/clk/tegra/clk-pll.c
1346
spin_lock_irqsave(pll->lock, flags);
drivers/clk/tegra/clk-pll.c
1348
_get_pll_mnp(pll, &old_cfg);
drivers/clk/tegra/clk-pll.c
1349
if (pll->params->flags & TEGRA_PLL_VCO_OUT)
drivers/clk/tegra/clk-pll.c
1355
if (pll->lock)
drivers/clk/tegra/clk-pll.c
1356
spin_unlock_irqrestore(pll->lock, flags);
drivers/clk/tegra/clk-pll.c
1364
struct tegra_clk_pll *pll = to_clk_pll(hw);
drivers/clk/tegra/clk-pll.c
1377
if (pll->params->set_gain)
drivers/clk/tegra/clk-pll.c
1378
pll->params->set_gain(&cfg);
drivers/clk/tegra/clk-pll.c
1388
static void _pllcx_strobe(struct tegra_clk_pll *pll)
drivers/clk/tegra/clk-pll.c
1392
val = pll_readl_misc(pll);
drivers/clk/tegra/clk-pll.c
1394
pll_writel_misc(val, pll);
drivers/clk/tegra/clk-pll.c
1398
pll_writel_misc(val, pll);
drivers/clk/tegra/clk-pll.c
1403
struct tegra_clk_pll *pll = to_clk_pll(hw);
drivers/clk/tegra/clk-pll.c
1411
if (pll->lock)
drivers/clk/tegra/clk-pll.c
1412
spin_lock_irqsave(pll->lock, flags);
drivers/clk/tegra/clk-pll.c
1417
val = pll_readl_misc(pll);
drivers/clk/tegra/clk-pll.c
1419
pll_writel_misc(val, pll);
drivers/clk/tegra/clk-pll.c
1422
_pllcx_strobe(pll);
drivers/clk/tegra/clk-pll.c
1424
ret = clk_pll_wait_for_lock(pll);
drivers/clk/tegra/clk-pll.c
1426
if (pll->lock)
drivers/clk/tegra/clk-pll.c
1427
spin_unlock_irqrestore(pll->lock, flags);
drivers/clk/tegra/clk-pll.c
1434
struct tegra_clk_pll *pll = to_clk_pll(hw);
drivers/clk/tegra/clk-pll.c
1439
val = pll_readl_misc(pll);
drivers/clk/tegra/clk-pll.c
1441
pll_writel_misc(val, pll);
drivers/clk/tegra/clk-pll.c
1447
struct tegra_clk_pll *pll = to_clk_pll(hw);
drivers/clk/tegra/clk-pll.c
1450
if (pll->lock)
drivers/clk/tegra/clk-pll.c
1451
spin_lock_irqsave(pll->lock, flags);
drivers/clk/tegra/clk-pll.c
1455
if (pll->lock)
drivers/clk/tegra/clk-pll.c
1456
spin_unlock_irqrestore(pll->lock, flags);
drivers/clk/tegra/clk-pll.c
1459
static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll,
drivers/clk/tegra/clk-pll.c
1484
val = pll_readl_misc(pll);
drivers/clk/tegra/clk-pll.c
1488
pll_writel_misc(val, pll);
drivers/clk/tegra/clk-pll.c
1497
struct tegra_clk_pll *pll = to_clk_pll(hw);
drivers/clk/tegra/clk-pll.c
1501
if (pll->lock)
drivers/clk/tegra/clk-pll.c
1502
spin_lock_irqsave(pll->lock, flags);
drivers/clk/tegra/clk-pll.c
1508
_get_pll_mnp(pll, &old_cfg);
drivers/clk/tegra/clk-pll.c
1522
ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
drivers/clk/tegra/clk-pll.c
1526
_update_pll_mnp(pll, &cfg);
drivers/clk/tegra/clk-pll.c
1532
if (pll->lock)
drivers/clk/tegra/clk-pll.c
1533
spin_unlock_irqrestore(pll->lock, flags);
drivers/clk/tegra/clk-pll.c
1538
static long _pllre_calc_rate(struct tegra_clk_pll *pll,
drivers/clk/tegra/clk-pll.c
1545
m = _pll_fixed_mdiv(pll->params, parent_rate);
drivers/clk/tegra/clk-pll.c
1563
struct tegra_clk_pll *pll = to_clk_pll(hw);
drivers/clk/tegra/clk-pll.c
1567
if (pll->lock)
drivers/clk/tegra/clk-pll.c
1568
spin_lock_irqsave(pll->lock, flags);
drivers/clk/tegra/clk-pll.c
1570
_pllre_calc_rate(pll, &cfg, rate, parent_rate);
drivers/clk/tegra/clk-pll.c
1571
_get_pll_mnp(pll, &old_cfg);
drivers/clk/tegra/clk-pll.c
1579
_update_pll_mnp(pll, &cfg);
drivers/clk/tegra/clk-pll.c
1583
ret = clk_pll_wait_for_lock(pll);
drivers/clk/tegra/clk-pll.c
1587
if (pll->lock)
drivers/clk/tegra/clk-pll.c
1588
spin_unlock_irqrestore(pll->lock, flags);
drivers/clk/tegra/clk-pll.c
1597
struct tegra_clk_pll *pll = to_clk_pll(hw);
drivers/clk/tegra/clk-pll.c
1600
_get_pll_mnp(pll, &cfg);
drivers/clk/tegra/clk-pll.c
1611
struct tegra_clk_pll *pll = to_clk_pll(hw);
drivers/clk/tegra/clk-pll.c
1613
req->rate = _pllre_calc_rate(pll, NULL, req->rate,
drivers/clk/tegra/clk-pll.c
1621
struct tegra_clk_pll *pll = to_clk_pll(hw);
drivers/clk/tegra/clk-pll.c
1630
if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
drivers/clk/tegra/clk-pll.c
1633
if (pll->lock)
drivers/clk/tegra/clk-pll.c
1634
spin_lock_irqsave(pll->lock, flags);
drivers/clk/tegra/clk-pll.c
1636
val = pll_readl_base(pll);
drivers/clk/tegra/clk-pll.c
1638
pll_writel_base(val, pll);
drivers/clk/tegra/clk-pll.c
1640
val = pll_readl(pll->params->aux_reg, pll);
drivers/clk/tegra/clk-pll.c
1643
pll_writel(val, pll->params->aux_reg, pll);
drivers/clk/tegra/clk-pll.c
1646
val = pll_readl_misc(pll);
drivers/clk/tegra/clk-pll.c
1652
pll_writel_misc(val, pll);
drivers/clk/tegra/clk-pll.c
1655
val = pll_readl(PLLE_SS_CTRL, pll);
drivers/clk/tegra/clk-pll.c
1657
pll_writel(val, PLLE_SS_CTRL, pll);
drivers/clk/tegra/clk-pll.c
1659
val = pll_readl_base(pll);
drivers/clk/tegra/clk-pll.c
1660
val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
drivers/clk/tegra/clk-pll.c
1661
divm_mask_shifted(pll));
drivers/clk/tegra/clk-pll.c
1663
val |= sel.m << divm_shift(pll);
drivers/clk/tegra/clk-pll.c
1664
val |= sel.n << divn_shift(pll);
drivers/clk/tegra/clk-pll.c
1666
pll_writel_base(val, pll);
drivers/clk/tegra/clk-pll.c
1670
ret = clk_pll_wait_for_lock(pll);
drivers/clk/tegra/clk-pll.c
1675
val = pll_readl(PLLE_SS_CTRL, pll);
drivers/clk/tegra/clk-pll.c
1679
pll_writel(val, PLLE_SS_CTRL, pll);
drivers/clk/tegra/clk-pll.c
1681
pll_writel(val, PLLE_SS_CTRL, pll);
drivers/clk/tegra/clk-pll.c
1684
pll_writel(val, PLLE_SS_CTRL, pll);
drivers/clk/tegra/clk-pll.c
1688
val = pll_readl_misc(pll);
drivers/clk/tegra/clk-pll.c
1690
pll_writel_misc(val, pll);
drivers/clk/tegra/clk-pll.c
1692
val = pll_readl(pll->params->aux_reg, pll);
drivers/clk/tegra/clk-pll.c
1695
pll_writel(val, pll->params->aux_reg, pll);
drivers/clk/tegra/clk-pll.c
1698
pll_writel(val, pll->params->aux_reg, pll);
drivers/clk/tegra/clk-pll.c
1700
val = pll_readl(XUSBIO_PLL_CFG0, pll);
drivers/clk/tegra/clk-pll.c
1705
pll_writel(val, XUSBIO_PLL_CFG0, pll);
drivers/clk/tegra/clk-pll.c
1708
pll_writel(val, XUSBIO_PLL_CFG0, pll);
drivers/clk/tegra/clk-pll.c
1711
val = pll_readl(SATA_PLL_CFG0, pll);
drivers/clk/tegra/clk-pll.c
1715
pll_writel(val, SATA_PLL_CFG0, pll);
drivers/clk/tegra/clk-pll.c
1719
val = pll_readl(SATA_PLL_CFG0, pll);
drivers/clk/tegra/clk-pll.c
1721
pll_writel(val, SATA_PLL_CFG0, pll);
drivers/clk/tegra/clk-pll.c
1724
if (pll->lock)
drivers/clk/tegra/clk-pll.c
1725
spin_unlock_irqrestore(pll->lock, flags);
drivers/clk/tegra/clk-pll.c
1732
struct tegra_clk_pll *pll = to_clk_pll(hw);
drivers/clk/tegra/clk-pll.c
1736
if (pll->lock)
drivers/clk/tegra/clk-pll.c
1737
spin_lock_irqsave(pll->lock, flags);
drivers/clk/tegra/clk-pll.c
1741
val = pll_readl_misc(pll);
drivers/clk/tegra/clk-pll.c
1743
pll_writel_misc(val, pll);
drivers/clk/tegra/clk-pll.c
1746
if (pll->lock)
drivers/clk/tegra/clk-pll.c
1747
spin_unlock_irqrestore(pll->lock, flags);
drivers/clk/tegra/clk-pll.c
1752
struct tegra_clk_pll *pll = to_clk_pll(hw);
drivers/clk/tegra/clk-pll.c
1767
if (pll->lock)
drivers/clk/tegra/clk-pll.c
1768
spin_lock_irqsave(pll->lock, flags);
drivers/clk/tegra/clk-pll.c
1773
ret = clk_pll_wait_for_lock(pll);
drivers/clk/tegra/clk-pll.c
1791
value = pll_readl_base(pll);
drivers/clk/tegra/clk-pll.c
1793
pll_writel_base(value, pll);
drivers/clk/tegra/clk-pll.c
1795
value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
drivers/clk/tegra/clk-pll.c
1805
writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
drivers/clk/tegra/clk-pll.c
1807
value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
drivers/clk/tegra/clk-pll.c
1818
writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
drivers/clk/tegra/clk-pll.c
1821
value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
drivers/clk/tegra/clk-pll.c
1825
writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
drivers/clk/tegra/clk-pll.c
1827
value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
drivers/clk/tegra/clk-pll.c
1830
writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
drivers/clk/tegra/clk-pll.c
1838
value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
drivers/clk/tegra/clk-pll.c
1841
writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
drivers/clk/tegra/clk-pll.c
1846
value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
drivers/clk/tegra/clk-pll.c
1848
writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
drivers/clk/tegra/clk-pll.c
1851
if (pll->lock)
drivers/clk/tegra/clk-pll.c
1852
spin_unlock_irqrestore(pll->lock, flags);
drivers/clk/tegra/clk-pll.c
1857
static void _clk_plle_tegra_init_parent(struct tegra_clk_pll *pll)
drivers/clk/tegra/clk-pll.c
1862
val = pll_readl_base(pll);
drivers/clk/tegra/clk-pll.c
1863
val_aux = pll_readl(pll->params->aux_reg, pll);
drivers/clk/tegra/clk-pll.c
1873
pll_writel(val_aux, pll->params->aux_reg, pll);
drivers/clk/tegra/clk-pll.c
1874
fence_udelay(1, pll->clk_base);
drivers/clk/tegra/clk-pll.c
1883
struct tegra_clk_pll *pll;
drivers/clk/tegra/clk-pll.c
1885
pll = kzalloc_obj(*pll);
drivers/clk/tegra/clk-pll.c
1886
if (!pll)
drivers/clk/tegra/clk-pll.c
1889
pll->clk_base = clk_base;
drivers/clk/tegra/clk-pll.c
1890
pll->pmc = pmc;
drivers/clk/tegra/clk-pll.c
1892
pll->params = pll_params;
drivers/clk/tegra/clk-pll.c
1893
pll->lock = lock;
drivers/clk/tegra/clk-pll.c
1898
return pll;
drivers/clk/tegra/clk-pll.c
1901
static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll,
drivers/clk/tegra/clk-pll.c
1914
if (!pll->params->calc_rate) {
drivers/clk/tegra/clk-pll.c
1915
if (pll->params->flags & TEGRA_PLLM)
drivers/clk/tegra/clk-pll.c
1916
pll->params->calc_rate = _calc_dynamic_ramp_rate;
drivers/clk/tegra/clk-pll.c
1918
pll->params->calc_rate = _calc_rate;
drivers/clk/tegra/clk-pll.c
1921
if (pll->params->set_defaults)
drivers/clk/tegra/clk-pll.c
1922
pll->params->set_defaults(pll);
drivers/clk/tegra/clk-pll.c
1925
pll->hw.init = &init;
drivers/clk/tegra/clk-pll.c
1927
return tegra_clk_dev_register(&pll->hw);
drivers/clk/tegra/clk-pll.c
1935
struct tegra_clk_pll *pll;
drivers/clk/tegra/clk-pll.c
1940
pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
drivers/clk/tegra/clk-pll.c
1941
if (IS_ERR(pll))
drivers/clk/tegra/clk-pll.c
1942
return ERR_CAST(pll);
drivers/clk/tegra/clk-pll.c
1944
clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
drivers/clk/tegra/clk-pll.c
1947
kfree(pll);
drivers/clk/tegra/clk-pll.c
1966
struct tegra_clk_pll *pll;
drivers/clk/tegra/clk-pll.c
1974
pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
drivers/clk/tegra/clk-pll.c
1975
if (IS_ERR(pll))
drivers/clk/tegra/clk-pll.c
1976
return ERR_CAST(pll);
drivers/clk/tegra/clk-pll.c
1978
clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
drivers/clk/tegra/clk-pll.c
1981
kfree(pll);
drivers/clk/tegra/clk-pll.c
1990
struct tegra_clk_pll *pll;
drivers/clk/tegra/clk-pll.c
1995
pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
drivers/clk/tegra/clk-pll.c
1996
if (IS_ERR(pll))
drivers/clk/tegra/clk-pll.c
1997
return ERR_CAST(pll);
drivers/clk/tegra/clk-pll.c
1999
clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
drivers/clk/tegra/clk-pll.c
2002
kfree(pll);
drivers/clk/tegra/clk-pll.c
2058
struct tegra_clk_pll *pll;
drivers/clk/tegra/clk-pll.c
2104
pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
drivers/clk/tegra/clk-pll.c
2105
if (IS_ERR(pll))
drivers/clk/tegra/clk-pll.c
2106
return ERR_CAST(pll);
drivers/clk/tegra/clk-pll.c
2108
clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
drivers/clk/tegra/clk-pll.c
2111
kfree(pll);
drivers/clk/tegra/clk-pll.c
2123
struct tegra_clk_pll *pll;
drivers/clk/tegra/clk-pll.c
2132
pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
drivers/clk/tegra/clk-pll.c
2133
if (IS_ERR(pll))
drivers/clk/tegra/clk-pll.c
2134
return ERR_CAST(pll);
drivers/clk/tegra/clk-pll.c
2138
val = pll_readl_base(pll);
drivers/clk/tegra/clk-pll.c
2146
val = m << divm_shift(pll);
drivers/clk/tegra/clk-pll.c
2147
val |= (pll_params->vco_min / parent_rate) << divn_shift(pll);
drivers/clk/tegra/clk-pll.c
2148
pll_writel_base(val, pll);
drivers/clk/tegra/clk-pll.c
2153
val = pll_readl_misc(pll);
drivers/clk/tegra/clk-pll.c
2155
pll_writel_misc(val, pll);
drivers/clk/tegra/clk-pll.c
2157
clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
drivers/clk/tegra/clk-pll.c
2160
kfree(pll);
drivers/clk/tegra/clk-pll.c
2171
struct tegra_clk_pll *pll;
drivers/clk/tegra/clk-pll.c
2195
pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
drivers/clk/tegra/clk-pll.c
2196
if (IS_ERR(pll))
drivers/clk/tegra/clk-pll.c
2197
return ERR_CAST(pll);
drivers/clk/tegra/clk-pll.c
2199
clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
drivers/clk/tegra/clk-pll.c
2202
kfree(pll);
drivers/clk/tegra/clk-pll.c
2215
struct tegra_clk_pll *pll;
drivers/clk/tegra/clk-pll.c
2234
pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
drivers/clk/tegra/clk-pll.c
2235
if (IS_ERR(pll))
drivers/clk/tegra/clk-pll.c
2236
return ERR_CAST(pll);
drivers/clk/tegra/clk-pll.c
2263
pll_writel_base(0, pll);
drivers/clk/tegra/clk-pll.c
2264
_update_pll_mnp(pll, &cfg);
drivers/clk/tegra/clk-pll.c
2266
pll_writel_misc(PLLCX_MISC_DEFAULT, pll);
drivers/clk/tegra/clk-pll.c
2267
pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);
drivers/clk/tegra/clk-pll.c
2268
pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);
drivers/clk/tegra/clk-pll.c
2269
pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);
drivers/clk/tegra/clk-pll.c
2271
_pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
drivers/clk/tegra/clk-pll.c
2273
clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
drivers/clk/tegra/clk-pll.c
2276
kfree(pll);
drivers/clk/tegra/clk-pll.c
2287
struct tegra_clk_pll *pll;
drivers/clk/tegra/clk-pll.c
2290
pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
drivers/clk/tegra/clk-pll.c
2291
if (IS_ERR(pll))
drivers/clk/tegra/clk-pll.c
2292
return ERR_CAST(pll);
drivers/clk/tegra/clk-pll.c
2294
_clk_plle_tegra_init_parent(pll);
drivers/clk/tegra/clk-pll.c
2296
clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
drivers/clk/tegra/clk-pll.c
2299
kfree(pll);
drivers/clk/tegra/clk-pll.c
2310
struct tegra_clk_pll *pll;
drivers/clk/tegra/clk-pll.c
2315
pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
drivers/clk/tegra/clk-pll.c
2316
if (IS_ERR(pll))
drivers/clk/tegra/clk-pll.c
2317
return ERR_CAST(pll);
drivers/clk/tegra/clk-pll.c
2319
clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
drivers/clk/tegra/clk-pll.c
2322
kfree(pll);
drivers/clk/tegra/clk-pll.c
2344
struct tegra_clk_pll *pll;
drivers/clk/tegra/clk-pll.c
2361
pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
drivers/clk/tegra/clk-pll.c
2362
if (IS_ERR(pll))
drivers/clk/tegra/clk-pll.c
2363
return ERR_CAST(pll);
drivers/clk/tegra/clk-pll.c
2365
val = pll_readl_base(pll);
drivers/clk/tegra/clk-pll.c
2367
pll_writel_base(val, pll);
drivers/clk/tegra/clk-pll.c
2381
kfree(pll);
drivers/clk/tegra/clk-pll.c
2387
_update_pll_mnp(pll, &cfg);
drivers/clk/tegra/clk-pll.c
2389
pll_writel_misc(PLLSS_MISC_DEFAULT, pll);
drivers/clk/tegra/clk-pll.c
2390
pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll);
drivers/clk/tegra/clk-pll.c
2391
pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll);
drivers/clk/tegra/clk-pll.c
2392
pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);
drivers/clk/tegra/clk-pll.c
2394
val = pll_readl_base(pll);
drivers/clk/tegra/clk-pll.c
2399
kfree(pll);
drivers/clk/tegra/clk-pll.c
2408
pll_writel_base(val, pll);
drivers/clk/tegra/clk-pll.c
2410
clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
drivers/clk/tegra/clk-pll.c
2414
kfree(pll);
drivers/clk/tegra/clk-pll.c
2427
struct tegra_clk_pll *pll;
drivers/clk/tegra/clk-pll.c
2436
pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
drivers/clk/tegra/clk-pll.c
2437
if (IS_ERR(pll))
drivers/clk/tegra/clk-pll.c
2438
return ERR_CAST(pll);
drivers/clk/tegra/clk-pll.c
2440
clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
drivers/clk/tegra/clk-pll.c
2443
kfree(pll);
drivers/clk/tegra/clk-pll.c
2450
struct tegra_clk_pll *pll = to_clk_pll(hw);
drivers/clk/tegra/clk-pll.c
2453
val = pll_readl_base(pll);
drivers/clk/tegra/clk-pll.c
2460
struct tegra_clk_pll *pll = to_clk_pll(hw);
drivers/clk/tegra/clk-pll.c
2472
if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
drivers/clk/tegra/clk-pll.c
2475
if (pll->lock)
drivers/clk/tegra/clk-pll.c
2476
spin_lock_irqsave(pll->lock, flags);
drivers/clk/tegra/clk-pll.c
2478
val = pll_readl(pll->params->aux_reg, pll);
drivers/clk/tegra/clk-pll.c
2482
val = pll_readl_base(pll);
drivers/clk/tegra/clk-pll.c
2484
pll_writel_base(val, pll);
drivers/clk/tegra/clk-pll.c
2486
val = pll_readl_misc(pll);
drivers/clk/tegra/clk-pll.c
2492
pll_writel_misc(val, pll);
drivers/clk/tegra/clk-pll.c
2495
val = pll_readl(PLLE_SS_CTRL, pll);
drivers/clk/tegra/clk-pll.c
2497
pll_writel(val, PLLE_SS_CTRL, pll);
drivers/clk/tegra/clk-pll.c
2499
val = pll_readl_base(pll);
drivers/clk/tegra/clk-pll.c
2500
val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
drivers/clk/tegra/clk-pll.c
2501
divm_mask_shifted(pll));
drivers/clk/tegra/clk-pll.c
2503
val |= sel.m << divm_shift(pll);
drivers/clk/tegra/clk-pll.c
2504
val |= sel.n << divn_shift(pll);
drivers/clk/tegra/clk-pll.c
2506
pll_writel_base(val, pll);
drivers/clk/tegra/clk-pll.c
2509
val = pll_readl_base(pll);
drivers/clk/tegra/clk-pll.c
2511
pll_writel_base(val, pll);
drivers/clk/tegra/clk-pll.c
2513
ret = clk_pll_wait_for_lock(pll);
drivers/clk/tegra/clk-pll.c
2518
val = pll_readl(PLLE_SS_CTRL, pll);
drivers/clk/tegra/clk-pll.c
2522
pll_writel(val, PLLE_SS_CTRL, pll);
drivers/clk/tegra/clk-pll.c
2524
pll_writel(val, PLLE_SS_CTRL, pll);
drivers/clk/tegra/clk-pll.c
2527
pll_writel(val, PLLE_SS_CTRL, pll);
drivers/clk/tegra/clk-pll.c
2531
if (pll->lock)
drivers/clk/tegra/clk-pll.c
2532
spin_unlock_irqrestore(pll->lock, flags);
drivers/clk/tegra/clk-pll.c
2539
struct tegra_clk_pll *pll = to_clk_pll(hw);
drivers/clk/tegra/clk-pll.c
2543
if (pll->lock)
drivers/clk/tegra/clk-pll.c
2544
spin_lock_irqsave(pll->lock, flags);
drivers/clk/tegra/clk-pll.c
2547
val = pll_readl(pll->params->aux_reg, pll);
drivers/clk/tegra/clk-pll.c
2551
val = pll_readl_base(pll);
drivers/clk/tegra/clk-pll.c
2553
pll_writel_base(val, pll);
drivers/clk/tegra/clk-pll.c
2555
val = pll_readl(pll->params->aux_reg, pll);
drivers/clk/tegra/clk-pll.c
2557
pll_writel(val, pll->params->aux_reg, pll);
drivers/clk/tegra/clk-pll.c
2559
val = pll_readl_misc(pll);
drivers/clk/tegra/clk-pll.c
2561
pll_writel_misc(val, pll);
drivers/clk/tegra/clk-pll.c
2565
if (pll->lock)
drivers/clk/tegra/clk-pll.c
2566
spin_unlock_irqrestore(pll->lock, flags);
drivers/clk/tegra/clk-pll.c
2571
struct tegra_clk_pll *pll = to_clk_pll(hw);
drivers/clk/tegra/clk-pll.c
2573
_clk_plle_tegra_init_parent(pll);
drivers/clk/tegra/clk-pll.c
2590
struct tegra_clk_pll *pll;
drivers/clk/tegra/clk-pll.c
2593
pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
drivers/clk/tegra/clk-pll.c
2594
if (IS_ERR(pll))
drivers/clk/tegra/clk-pll.c
2595
return ERR_CAST(pll);
drivers/clk/tegra/clk-pll.c
2597
_clk_plle_tegra_init_parent(pll);
drivers/clk/tegra/clk-pll.c
2599
clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
drivers/clk/tegra/clk-pll.c
2602
kfree(pll);
drivers/clk/tegra/clk-pll.c
2615
struct tegra_clk_pll *pll;
drivers/clk/tegra/clk-pll.c
2637
pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
drivers/clk/tegra/clk-pll.c
2638
if (IS_ERR(pll))
drivers/clk/tegra/clk-pll.c
2639
return ERR_CAST(pll);
drivers/clk/tegra/clk-pll.c
2641
clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
drivers/clk/tegra/clk-pll.c
2644
kfree(pll);
drivers/clk/tegra/clk-pll.c
2655
struct tegra_clk_pll *pll;
drivers/clk/tegra/clk-pll.c
2685
pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
drivers/clk/tegra/clk-pll.c
2686
if (IS_ERR(pll))
drivers/clk/tegra/clk-pll.c
2687
return ERR_CAST(pll);
drivers/clk/tegra/clk-pll.c
2689
clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
drivers/clk/tegra/clk-pll.c
2693
kfree(pll);
drivers/clk/tegra/clk-pll.c
2704
struct tegra_clk_pll *pll;
drivers/clk/tegra/clk-pll.c
2728
pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
drivers/clk/tegra/clk-pll.c
2729
if (IS_ERR(pll))
drivers/clk/tegra/clk-pll.c
2730
return ERR_CAST(pll);
drivers/clk/tegra/clk-pll.c
2732
clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
drivers/clk/tegra/clk-pll.c
2735
kfree(pll);
drivers/clk/tegra/clk-pll.c
276
static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
drivers/clk/tegra/clk-pll.c
280
if (!(pll->params->flags & TEGRA_PLL_USE_LOCK))
drivers/clk/tegra/clk-pll.c
283
if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE))
drivers/clk/tegra/clk-pll.c
286
val = pll_readl_misc(pll);
drivers/clk/tegra/clk-pll.c
287
val |= BIT(pll->params->lock_enable_bit_idx);
drivers/clk/tegra/clk-pll.c
288
pll_writel_misc(val, pll);
drivers/clk/tegra/clk-pll.c
291
static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
drivers/clk/tegra/clk-pll.c
297
if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) {
drivers/clk/tegra/clk-pll.c
298
udelay(pll->params->lock_delay);
drivers/clk/tegra/clk-pll.c
302
lock_addr = pll->clk_base;
drivers/clk/tegra/clk-pll.c
303
if (pll->params->flags & TEGRA_PLL_LOCK_MISC)
drivers/clk/tegra/clk-pll.c
304
lock_addr += pll->params->misc_reg;
drivers/clk/tegra/clk-pll.c
306
lock_addr += pll->params->base_reg;
drivers/clk/tegra/clk-pll.c
308
lock_mask = pll->params->lock_mask;
drivers/clk/tegra/clk-pll.c
310
for (i = 0; i < pll->params->lock_delay; i++) {
drivers/clk/tegra/clk-pll.c
320
clk_hw_get_name(&pll->hw));
drivers/clk/tegra/clk-pll.c
325
int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll)
drivers/clk/tegra/clk-pll.c
327
return clk_pll_wait_for_lock(pll);
drivers/clk/tegra/clk-pll.c
330
static bool pllm_clk_is_gated_by_pmc(struct tegra_clk_pll *pll)
drivers/clk/tegra/clk-pll.c
332
u32 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
drivers/clk/tegra/clk-pll.c
340
struct tegra_clk_pll *pll = to_clk_pll(hw);
drivers/clk/tegra/clk-pll.c
348
if ((pll->params->flags & TEGRA_PLLM) && pllm_clk_is_gated_by_pmc(pll))
drivers/clk/tegra/clk-pll.c
351
val = pll_readl_base(pll);
drivers/clk/tegra/clk-pll.c
358
struct tegra_clk_pll *pll = to_clk_pll(hw);
drivers/clk/tegra/clk-pll.c
361
if (pll->params->iddq_reg) {
drivers/clk/tegra/clk-pll.c
362
val = pll_readl(pll->params->iddq_reg, pll);
drivers/clk/tegra/clk-pll.c
363
val &= ~BIT(pll->params->iddq_bit_idx);
drivers/clk/tegra/clk-pll.c
364
pll_writel(val, pll->params->iddq_reg, pll);
drivers/clk/tegra/clk-pll.c
368
if (pll->params->reset_reg) {
drivers/clk/tegra/clk-pll.c
369
val = pll_readl(pll->params->reset_reg, pll);
drivers/clk/tegra/clk-pll.c
370
val &= ~BIT(pll->params->reset_bit_idx);
drivers/clk/tegra/clk-pll.c
371
pll_writel(val, pll->params->reset_reg, pll);
drivers/clk/tegra/clk-pll.c
374
clk_pll_enable_lock(pll);
drivers/clk/tegra/clk-pll.c
376
val = pll_readl_base(pll);
drivers/clk/tegra/clk-pll.c
377
if (pll->params->flags & TEGRA_PLL_BYPASS)
drivers/clk/tegra/clk-pll.c
380
pll_writel_base(val, pll);
drivers/clk/tegra/clk-pll.c
382
if (pll->params->flags & TEGRA_PLLM) {
drivers/clk/tegra/clk-pll.c
383
val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
drivers/clk/tegra/clk-pll.c
385
writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
drivers/clk/tegra/clk-pll.c
391
struct tegra_clk_pll *pll = to_clk_pll(hw);
drivers/clk/tegra/clk-pll.c
394
val = pll_readl_base(pll);
drivers/clk/tegra/clk-pll.c
395
if (pll->params->flags & TEGRA_PLL_BYPASS)
drivers/clk/tegra/clk-pll.c
398
pll_writel_base(val, pll);
drivers/clk/tegra/clk-pll.c
400
if (pll->params->flags & TEGRA_PLLM) {
drivers/clk/tegra/clk-pll.c
401
val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
drivers/clk/tegra/clk-pll.c
403
writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
drivers/clk/tegra/clk-pll.c
406
if (pll->params->reset_reg) {
drivers/clk/tegra/clk-pll.c
407
val = pll_readl(pll->params->reset_reg, pll);
drivers/clk/tegra/clk-pll.c
408
val |= BIT(pll->params->reset_bit_idx);
drivers/clk/tegra/clk-pll.c
409
pll_writel(val, pll->params->reset_reg, pll);
drivers/clk/tegra/clk-pll.c
412
if (pll->params->iddq_reg) {
drivers/clk/tegra/clk-pll.c
413
val = pll_readl(pll->params->iddq_reg, pll);
drivers/clk/tegra/clk-pll.c
414
val |= BIT(pll->params->iddq_bit_idx);
drivers/clk/tegra/clk-pll.c
415
pll_writel(val, pll->params->iddq_reg, pll);
drivers/clk/tegra/clk-pll.c
420
static void pll_clk_start_ss(struct tegra_clk_pll *pll)
drivers/clk/tegra/clk-pll.c
422
if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
drivers/clk/tegra/clk-pll.c
423
u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
drivers/clk/tegra/clk-pll.c
425
val |= pll->params->ssc_ctrl_en_mask;
drivers/clk/tegra/clk-pll.c
426
pll_writel(val, pll->params->ssc_ctrl_reg, pll);
drivers/clk/tegra/clk-pll.c
430
static void pll_clk_stop_ss(struct tegra_clk_pll *pll)
drivers/clk/tegra/clk-pll.c
432
if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
drivers/clk/tegra/clk-pll.c
433
u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
drivers/clk/tegra/clk-pll.c
435
val &= ~pll->params->ssc_ctrl_en_mask;
drivers/clk/tegra/clk-pll.c
436
pll_writel(val, pll->params->ssc_ctrl_reg, pll);
drivers/clk/tegra/clk-pll.c
442
struct tegra_clk_pll *pll = to_clk_pll(hw);
drivers/clk/tegra/clk-pll.c
449
if (pll->lock)
drivers/clk/tegra/clk-pll.c
450
spin_lock_irqsave(pll->lock, flags);
drivers/clk/tegra/clk-pll.c
454
ret = clk_pll_wait_for_lock(pll);
drivers/clk/tegra/clk-pll.c
456
pll_clk_start_ss(pll);
drivers/clk/tegra/clk-pll.c
458
if (pll->lock)
drivers/clk/tegra/clk-pll.c
459
spin_unlock_irqrestore(pll->lock, flags);
drivers/clk/tegra/clk-pll.c
466
struct tegra_clk_pll *pll = to_clk_pll(hw);
drivers/clk/tegra/clk-pll.c
469
if (pll->lock)
drivers/clk/tegra/clk-pll.c
470
spin_lock_irqsave(pll->lock, flags);
drivers/clk/tegra/clk-pll.c
472
pll_clk_stop_ss(pll);
drivers/clk/tegra/clk-pll.c
476
if (pll->lock)
drivers/clk/tegra/clk-pll.c
477
spin_unlock_irqrestore(pll->lock, flags);
drivers/clk/tegra/clk-pll.c
482
struct tegra_clk_pll *pll = to_clk_pll(hw);
drivers/clk/tegra/clk-pll.c
483
const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
drivers/clk/tegra/clk-pll.c
496
int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div)
drivers/clk/tegra/clk-pll.c
498
return _p_div_to_hw(&pll->hw, p_div);
drivers/clk/tegra/clk-pll.c
503
struct tegra_clk_pll *pll = to_clk_pll(hw);
drivers/clk/tegra/clk-pll.c
504
const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
drivers/clk/tegra/clk-pll.c
522
struct tegra_clk_pll *pll = to_clk_pll(hw);
drivers/clk/tegra/clk-pll.c
526
for (sel = pll->params->freq_table; sel->input_rate != 0; sel++)
drivers/clk/tegra/clk-pll.c
534
if (pll->params->pdiv_tohw) {
drivers/clk/tegra/clk-pll.c
556
struct tegra_clk_pll *pll = to_clk_pll(hw);
drivers/clk/tegra/clk-pll.c
598
if (cfg->m == 0 || cfg->m > divm_max(pll) ||
drivers/clk/tegra/clk-pll.c
599
cfg->n > divn_max(pll) || (1 << p_div) > divp_max(pll) ||
drivers/clk/tegra/clk-pll.c
600
cfg->output_rate > pll->params->vco_max) {
drivers/clk/tegra/clk-pll.c
607
if (pll->params->pdiv_tohw) {
drivers/clk/tegra/clk-pll.c
630
struct tegra_clk_pll *pll = to_clk_pll(hw);
drivers/clk/tegra/clk-pll.c
634
if (!pll->params->sdm_din_reg)
drivers/clk/tegra/clk-pll.c
638
val = pll_readl_sdm_din(pll) & (~sdm_din_mask(pll));
drivers/clk/tegra/clk-pll.c
639
val |= sdin_data_to_din(cfg->sdm_data) & sdm_din_mask(pll);
drivers/clk/tegra/clk-pll.c
640
pll_writel_sdm_din(val, pll);
drivers/clk/tegra/clk-pll.c
643
val = pll_readl_sdm_ctrl(pll);
drivers/clk/tegra/clk-pll.c
644
enabled = (val & sdm_en_mask(pll));
drivers/clk/tegra/clk-pll.c
647
val &= ~pll->params->sdm_ctrl_en_mask;
drivers/clk/tegra/clk-pll.c
650
val |= pll->params->sdm_ctrl_en_mask;
drivers/clk/tegra/clk-pll.c
652
pll_writel_sdm_ctrl(val, pll);
drivers/clk/tegra/clk-pll.c
655
static void _update_pll_mnp(struct tegra_clk_pll *pll,
drivers/clk/tegra/clk-pll.c
659
struct tegra_clk_pll_params *params = pll->params;
drivers/clk/tegra/clk-pll.c
663
(pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
drivers/clk/tegra/clk-pll.c
665
val = pll_override_readl(params->pmc_divp_reg, pll);
drivers/clk/tegra/clk-pll.c
666
val &= ~(divp_mask(pll) << div_nmp->override_divp_shift);
drivers/clk/tegra/clk-pll.c
668
pll_override_writel(val, params->pmc_divp_reg, pll);
drivers/clk/tegra/clk-pll.c
670
val = pll_override_readl(params->pmc_divnm_reg, pll);
drivers/clk/tegra/clk-pll.c
671
val &= ~((divm_mask(pll) << div_nmp->override_divm_shift) |
drivers/clk/tegra/clk-pll.c
672
(divn_mask(pll) << div_nmp->override_divn_shift));
drivers/clk/tegra/clk-pll.c
675
pll_override_writel(val, params->pmc_divnm_reg, pll);
drivers/clk/tegra/clk-pll.c
677
val = pll_readl_base(pll);
drivers/clk/tegra/clk-pll.c
679
val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) |
drivers/clk/tegra/clk-pll.c
680
divp_mask_shifted(pll));
drivers/clk/tegra/clk-pll.c
682
val |= (cfg->m << divm_shift(pll)) |
drivers/clk/tegra/clk-pll.c
683
(cfg->n << divn_shift(pll)) |
drivers/clk/tegra/clk-pll.c
684
(cfg->p << divp_shift(pll));
drivers/clk/tegra/clk-pll.c
686
pll_writel_base(val, pll);
drivers/clk/tegra/clk-pll.c
688
clk_pll_set_sdm_data(&pll->hw, cfg);
drivers/clk/tegra/clk-pll.c
692
static void _get_pll_mnp(struct tegra_clk_pll *pll,
drivers/clk/tegra/clk-pll.c
696
struct tegra_clk_pll_params *params = pll->params;
drivers/clk/tegra/clk-pll.c
702
(pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
drivers/clk/tegra/clk-pll.c
704
val = pll_override_readl(params->pmc_divp_reg, pll);
drivers/clk/tegra/clk-pll.c
705
cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll);
drivers/clk/tegra/clk-pll.c
707
val = pll_override_readl(params->pmc_divnm_reg, pll);
drivers/clk/tegra/clk-pll.c
708
cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll);
drivers/clk/tegra/clk-pll.c
709
cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll);
drivers/clk/tegra/clk-pll.c
711
val = pll_readl_base(pll);
drivers/clk/tegra/clk-pll.c
713
cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll);
drivers/clk/tegra/clk-pll.c
714
cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll);
drivers/clk/tegra/clk-pll.c
715
cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll);
drivers/clk/tegra/clk-pll.c
717
if (pll->params->sdm_din_reg) {
drivers/clk/tegra/clk-pll.c
718
if (sdm_en_mask(pll) & pll_readl_sdm_ctrl(pll)) {
drivers/clk/tegra/clk-pll.c
719
val = pll_readl_sdm_din(pll);
drivers/clk/tegra/clk-pll.c
720
val &= sdm_din_mask(pll);
drivers/clk/tegra/clk-pll.c
727
static void _update_pll_cpcon(struct tegra_clk_pll *pll,
drivers/clk/tegra/clk-pll.c
733
val = pll_readl_misc(pll);
drivers/clk/tegra/clk-pll.c
738
if (pll->params->flags & TEGRA_PLL_SET_LFCON) {
drivers/clk/tegra/clk-pll.c
742
} else if (pll->params->flags & TEGRA_PLL_SET_DCCON) {
drivers/clk/tegra/clk-pll.c
744
if (rate >= (pll->params->vco_max >> 1))
drivers/clk/tegra/clk-pll.c
748
pll_writel_misc(val, pll);
drivers/clk/tegra/clk-pll.c
754
struct tegra_clk_pll *pll = to_clk_pll(hw);
drivers/clk/tegra/clk-pll.c
760
if (state && pll->params->pre_rate_change) {
drivers/clk/tegra/clk-pll.c
761
ret = pll->params->pre_rate_change();
drivers/clk/tegra/clk-pll.c
766
_get_pll_mnp(pll, &old_cfg);
drivers/clk/tegra/clk-pll.c
768
if (state && pll->params->defaults_set && pll->params->dyn_ramp &&
drivers/clk/tegra/clk-pll.c
770
ret = pll->params->dyn_ramp(pll, cfg);
drivers/clk/tegra/clk-pll.c
776
pll_clk_stop_ss(pll);
drivers/clk/tegra/clk-pll.c
780
if (!pll->params->defaults_set && pll->params->set_defaults)
drivers/clk/tegra/clk-pll.c
781
pll->params->set_defaults(pll);
drivers/clk/tegra/clk-pll.c
783
_update_pll_mnp(pll, cfg);
drivers/clk/tegra/clk-pll.c
785
if (pll->params->flags & TEGRA_PLL_HAS_CPCON)
drivers/clk/tegra/clk-pll.c
786
_update_pll_cpcon(pll, cfg, rate);
drivers/clk/tegra/clk-pll.c
790
ret = clk_pll_wait_for_lock(pll);
drivers/clk/tegra/clk-pll.c
791
pll_clk_start_ss(pll);
drivers/clk/tegra/clk-pll.c
795
if (state && pll->params->post_rate_change)
drivers/clk/tegra/clk-pll.c
796
pll->params->post_rate_change();
drivers/clk/tegra/clk-pll.c
804
struct tegra_clk_pll *pll = to_clk_pll(hw);
drivers/clk/tegra/clk-pll.c
809
if (pll->params->flags & TEGRA_PLL_FIXED) {
drivers/clk/tegra/clk-pll.c
810
if (rate != pll->params->fixed_rate) {
drivers/clk/tegra/clk-pll.c
813
pll->params->fixed_rate, rate);
drivers/clk/tegra/clk-pll.c
820
pll->params->calc_rate(hw, &cfg, rate, parent_rate)) {
drivers/clk/tegra/clk-pll.c
826
if (pll->lock)
drivers/clk/tegra/clk-pll.c
827
spin_lock_irqsave(pll->lock, flags);
drivers/clk/tegra/clk-pll.c
829
_get_pll_mnp(pll, &old_cfg);
drivers/clk/tegra/clk-pll.c
830
if (pll->params->flags & TEGRA_PLL_VCO_OUT)
drivers/clk/tegra/clk-pll.c
837
if (pll->lock)
drivers/clk/tegra/clk-pll.c
838
spin_unlock_irqrestore(pll->lock, flags);
drivers/clk/tegra/clk-pll.c
846
struct tegra_clk_pll *pll = to_clk_pll(hw);
drivers/clk/tegra/clk-pll.c
849
if (pll->params->flags & TEGRA_PLL_FIXED) {
drivers/clk/tegra/clk-pll.c
851
if (pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB))
drivers/clk/tegra/clk-pll.c
854
req->rate = pll->params->fixed_rate;
drivers/clk/tegra/clk-pll.c
860
pll->params->calc_rate(hw, &cfg, req->rate, req->best_parent_rate))
drivers/clk/tegra/clk-pll.c
871
struct tegra_clk_pll *pll = to_clk_pll(hw);
drivers/clk/tegra/clk-pll.c
877
val = pll_readl_base(pll);
drivers/clk/tegra/clk-pll.c
879
if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
drivers/clk/tegra/clk-pll.c
882
if ((pll->params->flags & TEGRA_PLL_FIXED) &&
drivers/clk/tegra/clk-pll.c
883
!(pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
drivers/clk/tegra/clk-pll.c
886
if (_get_table_rate(hw, &sel, pll->params->fixed_rate,
drivers/clk/tegra/clk-pll.c
892
return pll->params->fixed_rate;
drivers/clk/tegra/clk-pll.c
895
_get_pll_mnp(pll, &cfg);
drivers/clk/tegra/clk-pll.c
897
if (pll->params->flags & TEGRA_PLL_VCO_OUT) {
drivers/clk/tegra/clk-pll.c
908
if (pll->params->set_gain)
drivers/clk/tegra/clk-pll.c
909
pll->params->set_gain(&cfg);
drivers/clk/tegra/clk-pll.c
919
static int clk_plle_training(struct tegra_clk_pll *pll)
drivers/clk/tegra/clk-pll.c
924
if (!pll->pmc)
drivers/clk/tegra/clk-pll.c
931
val = readl(pll->pmc + PMC_SATA_PWRGT);
drivers/clk/tegra/clk-pll.c
933
writel(val, pll->pmc + PMC_SATA_PWRGT);
drivers/clk/tegra/clk-pll.c
935
val = readl(pll->pmc + PMC_SATA_PWRGT);
drivers/clk/tegra/clk-pll.c
937
writel(val, pll->pmc + PMC_SATA_PWRGT);
drivers/clk/tegra/clk-pll.c
939
val = readl(pll->pmc + PMC_SATA_PWRGT);
drivers/clk/tegra/clk-pll.c
941
writel(val, pll->pmc + PMC_SATA_PWRGT);
drivers/clk/tegra/clk-pll.c
943
val = pll_readl_misc(pll);
drivers/clk/tegra/clk-pll.c
947
val = pll_readl_misc(pll);
drivers/clk/tegra/clk-pll.c
962
struct tegra_clk_pll *pll = to_clk_pll(hw);
drivers/clk/tegra/clk-pll.c
973
if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
drivers/clk/tegra/clk-pll.c
978
val = pll_readl_misc(pll);
drivers/clk/tegra/clk-pll.c
980
pll_writel_misc(val, pll);
drivers/clk/tegra/clk-pll.c
982
val = pll_readl_misc(pll);
drivers/clk/tegra/clk-pll.c
984
err = clk_plle_training(pll);
drivers/clk/tegra/clk-pll.c
989
if (pll->params->flags & TEGRA_PLLE_CONFIGURE) {
drivers/clk/tegra/clk-pll.c
991
val = pll_readl_base(pll);
drivers/clk/tegra/clk-pll.c
992
val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
drivers/clk/tegra/clk-pll.c
993
divm_mask_shifted(pll));
drivers/clk/tegra/clk-pll.c
995
val |= sel.m << divm_shift(pll);
drivers/clk/tegra/clk-pll.c
996
val |= sel.n << divn_shift(pll);
drivers/clk/tegra/clk-pll.c
997
val |= sel.p << divp_shift(pll);
drivers/clk/tegra/clk-pll.c
999
pll_writel_base(val, pll);
drivers/clk/tegra/clk-tegra210.c
1143
static void pllx_check_defaults(struct tegra_clk_pll *pll)
drivers/clk/tegra/clk-tegra210.c
1149
_pll_misc_chk_default(clk_base, pll->params, 0, default_val,
drivers/clk/tegra/clk-tegra210.c
1153
_pll_misc_chk_default(clk_base, pll->params, 1, default_val,
drivers/clk/tegra/clk-tegra210.c
1158
_pll_misc_chk_default(clk_base, pll->params, 2,
drivers/clk/tegra/clk-tegra210.c
1162
_pll_misc_chk_default(clk_base, pll->params, 3, default_val,
drivers/clk/tegra/clk-tegra210.c
1166
_pll_misc_chk_default(clk_base, pll->params, 4, default_val,
drivers/clk/tegra/clk-tegra210.c
1170
_pll_misc_chk_default(clk_base, pll->params, 5, default_val,
drivers/clk/tegra/clk-tegra210.c
1276
static void pllp_check_defaults(struct tegra_clk_pll *pll, bool enabled)
drivers/clk/tegra/clk-tegra210.c
1285
_pll_misc_chk_default(clk_base, pll->params, 0, val,
drivers/clk/tegra/clk-tegra210.c
1291
_pll_misc_chk_default(clk_base, pll->params, 1, val,
drivers/clk/tegra/clk-tegra210.c
1413
static int tegra210_wait_for_mask(struct tegra_clk_pll *pll,
drivers/clk/tegra/clk-tegra210.c
1419
for (i = 0; i < pll->params->lock_delay / PLL_LOCKDET_DELAY + 1; i++) {
drivers/clk/tegra/clk-tegra210.c
1482
struct tegra_clk_pll *pll = to_clk_pll(hw);
drivers/clk/tegra/clk-tegra210.c
1483
struct tegra_clk_pll_params *params = pll->params;
drivers/clk/tegra/clk-tegra210.c
1505
cfg->p = tegra_pll_p_div_to_hw(pll, cfg->p);
drivers/clk/tegra/clk.h
346
void (*set_defaults)(struct tegra_clk_pll *pll);
drivers/clk/tegra/clk.h
347
int (*dyn_ramp)(struct tegra_clk_pll *pll,
drivers/clk/tegra/clk.h
903
int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll);
drivers/clk/tegra/clk.h
905
int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div);
drivers/clk/tenstorrent/atlantis-prcm.c
279
struct atlantis_clk_pll *pll = hw_to_atlantis_pll(hw);
drivers/clk/tenstorrent/atlantis-prcm.c
282
regmap_read(pll->common.regmap, pll->config.reg_offset, &val);
drivers/clk/tenstorrent/atlantis-prcm.c
283
regmap_read(pll->common.regmap, pll->config.en_reg_offset, &en_val);
drivers/clk/tenstorrent/atlantis-prcm.c
284
regmap_read(pll->common.regmap, pll->config.cg_reg_offset, &cg_val);
drivers/clk/tenstorrent/atlantis-prcm.c
288
(!pll->config.cg_reg_enable || (cg_val & pll->config.cg_reg_enable)) &&
drivers/clk/tenstorrent/atlantis-prcm.c
294
struct atlantis_clk_pll *pll = hw_to_atlantis_pll(hw);
drivers/clk/tenstorrent/atlantis-prcm.c
298
regmap_read(pll->common.regmap, pll->config.reg_offset, &val);
drivers/clk/tenstorrent/atlantis-prcm.c
299
regmap_read(pll->common.regmap, pll->config.en_reg_offset, &en_val);
drivers/clk/tenstorrent/atlantis-prcm.c
300
regmap_read(pll->common.regmap, pll->config.cg_reg_offset, &cg_val);
drivers/clk/tenstorrent/atlantis-prcm.c
304
(!pll->config.cg_reg_enable || (cg_val & pll->config.cg_reg_enable)) &&
drivers/clk/tenstorrent/atlantis-prcm.c
310
regmap_update_bits(pll->common.regmap, pll->config.reg_offset,
drivers/clk/tenstorrent/atlantis-prcm.c
314
regmap_update_bits(pll->common.regmap, pll->config.en_reg_offset,
drivers/clk/tenstorrent/atlantis-prcm.c
317
regmap_update_bits(pll->common.regmap, pll->config.en_reg_offset,
drivers/clk/tenstorrent/atlantis-prcm.c
321
ret = regmap_read_poll_timeout(pll->common.regmap,
drivers/clk/tenstorrent/atlantis-prcm.c
322
pll->config.reg_offset, val,
drivers/clk/tenstorrent/atlantis-prcm.c
331
regmap_update_bits(pll->common.regmap, pll->config.reg_offset,
drivers/clk/tenstorrent/atlantis-prcm.c
335
return regmap_update_bits(pll->common.regmap, pll->config.cg_reg_offset,
drivers/clk/tenstorrent/atlantis-prcm.c
336
pll->config.cg_reg_enable,
drivers/clk/tenstorrent/atlantis-prcm.c
337
pll->config.cg_reg_enable);
drivers/clk/tenstorrent/atlantis-prcm.c
342
struct atlantis_clk_pll *pll = hw_to_atlantis_pll(hw);
drivers/clk/tenstorrent/atlantis-prcm.c
345
regmap_update_bits(pll->common.regmap, pll->config.reg_offset,
drivers/clk/tenstorrent/atlantis-prcm.c
348
regmap_update_bits(pll->common.regmap, pll->config.en_reg_offset,
drivers/clk/tenstorrent/atlantis-prcm.c
355
struct atlantis_clk_pll *pll = hw_to_atlantis_pll(hw);
drivers/clk/tenstorrent/atlantis-prcm.c
360
regmap_read(pll->common.regmap, pll->config.reg_offset, &val);
drivers/clk/thead/clk-th1520-ap.c
325
struct ccu_pll *pll = hw_to_ccu_pll(hw);
drivers/clk/thead/clk-th1520-ap.c
327
regmap_set_bits(pll->common.map, pll->common.cfg1,
drivers/clk/thead/clk-th1520-ap.c
333
struct ccu_pll *pll = hw_to_ccu_pll(hw);
drivers/clk/thead/clk-th1520-ap.c
337
regmap_clear_bits(pll->common.map, pll->common.cfg1,
drivers/clk/thead/clk-th1520-ap.c
340
ret = regmap_read_poll_timeout_atomic(pll->common.map, TH1520_PLL_STS,
drivers/clk/thead/clk-th1520-ap.c
341
reg, reg & pll->lock_sts_mask,
drivers/clk/thead/clk-th1520-ap.c
353
struct ccu_pll *pll = hw_to_ccu_pll(hw);
drivers/clk/thead/clk-th1520-ap.c
355
return !regmap_test_bits(pll->common.map, pll->common.cfg1,
drivers/clk/thead/clk-th1520-ap.c
362
struct ccu_pll *pll = hw_to_ccu_pll(hw);
drivers/clk/thead/clk-th1520-ap.c
367
regmap_read(pll->common.map, pll->common.cfg0, &cfg0);
drivers/clk/thead/clk-th1520-ap.c
368
regmap_read(pll->common.map, pll->common.cfg1, &cfg1);
drivers/clk/thead/clk-th1520-ap.c
386
struct ccu_pll *pll = hw_to_ccu_pll(hw);
drivers/clk/thead/clk-th1520-ap.c
390
regmap_read(pll->common.map, pll->common.cfg0, &cfg0);
drivers/clk/thead/clk-th1520-ap.c
391
regmap_read(pll->common.map, pll->common.cfg1, &cfg1);
drivers/clk/thead/clk-th1520-ap.c
415
static const struct ccu_pll_cfg *ccu_pll_lookup_best_cfg(struct ccu_pll *pll,
drivers/clk/thead/clk-th1520-ap.c
422
for (i = 0; i < pll->cfgnum; i++) {
drivers/clk/thead/clk-th1520-ap.c
423
const struct ccu_pll_cfg *cfg = &pll->cfgs[i];
drivers/clk/thead/clk-th1520-ap.c
439
struct ccu_pll *pll = hw_to_ccu_pll(hw);
drivers/clk/thead/clk-th1520-ap.c
441
req->rate = ccu_pll_lookup_best_cfg(pll, req->rate)->freq;
drivers/clk/thead/clk-th1520-ap.c
449
struct ccu_pll *pll = hw_to_ccu_pll(hw);
drivers/clk/thead/clk-th1520-ap.c
452
cfg = ccu_pll_lookup_best_cfg(pll, rate);
drivers/clk/thead/clk-th1520-ap.c
456
regmap_write(pll->common.map, pll->common.cfg0,
drivers/clk/thead/clk-th1520-ap.c
462
regmap_update_bits(pll->common.map, pll->common.cfg1,
drivers/clk/visconti/pll.c
106
struct visconti_pll *pll = to_visconti_pll(hw);
drivers/clk/visconti/pll.c
107
const struct visconti_pll_rate_table *rate_table = pll->rate_table;
drivers/clk/visconti/pll.c
111
for (i = 0; i < pll->rate_count; i++)
drivers/clk/visconti/pll.c
127
struct visconti_pll *pll = to_visconti_pll(hw);
drivers/clk/visconti/pll.c
131
visconti_pll_get_params(pll, &rate_table);
drivers/clk/visconti/pll.c
133
return visconti_get_pll_rate_from_data(pll, &rate_table);
drivers/clk/visconti/pll.c
136
static int visconti_pll_set_params(struct visconti_pll *pll,
drivers/clk/visconti/pll.c
139
writel(PLL_CREATE_FRACMODE(rate_table), pll->pll_base + PLL_FRACMODE_REG);
drivers/clk/visconti/pll.c
140
writel(PLL_CREATE_OSTDIV(rate_table), pll->pll_base + PLL_POSTDIV_REG);
drivers/clk/visconti/pll.c
141
writel(rate_table->intin, pll->pll_base + PLL_INTIN_REG);
drivers/clk/visconti/pll.c
142
writel(rate_table->fracin, pll->pll_base + PLL_FRACIN_REG);
drivers/clk/visconti/pll.c
143
writel(rate_table->refdiv, pll->pll_base + PLL_REFDIV_REG);
drivers/clk/visconti/pll.c
151
struct visconti_pll *pll = to_visconti_pll(hw);
drivers/clk/visconti/pll.c
154
rate_table = visconti_get_pll_settings(pll, rate);
drivers/clk/visconti/pll.c
158
return visconti_pll_set_params(pll, rate_table);
drivers/clk/visconti/pll.c
163
struct visconti_pll *pll = to_visconti_pll(hw);
drivers/clk/visconti/pll.c
166
reg = readl(pll->pll_base + PLL_CTRL_REG);
drivers/clk/visconti/pll.c
173
struct visconti_pll *pll = to_visconti_pll(hw);
drivers/clk/visconti/pll.c
174
const struct visconti_pll_rate_table *rate_table = pll->rate_table;
drivers/clk/visconti/pll.c
181
spin_lock_irqsave(pll->lock, flags);
drivers/clk/visconti/pll.c
183
writel(PLL_CONFIG_SEL, pll->pll_base + PLL_CONF_REG);
drivers/clk/visconti/pll.c
185
reg = readl(pll->pll_base + PLL_CTRL_REG);
drivers/clk/visconti/pll.c
187
writel(reg, pll->pll_base + PLL_CTRL_REG);
drivers/clk/visconti/pll.c
189
visconti_pll_set_params(pll, &rate_table[0]);
drivers/clk/visconti/pll.c
191
reg = readl(pll->pll_base + PLL_CTRL_REG);
drivers/clk/visconti/pll.c
193
writel(reg, pll->pll_base + PLL_CTRL_REG);
drivers/clk/visconti/pll.c
197
reg = readl(pll->pll_base + PLL_CTRL_REG);
drivers/clk/visconti/pll.c
199
writel(reg, pll->pll_base + PLL_CTRL_REG);
drivers/clk/visconti/pll.c
203
reg = readl(pll->pll_base + PLL_CTRL_REG);
drivers/clk/visconti/pll.c
205
writel(reg, pll->pll_base + PLL_CTRL_REG);
drivers/clk/visconti/pll.c
207
spin_unlock_irqrestore(pll->lock, flags);
drivers/clk/visconti/pll.c
214
struct visconti_pll *pll = to_visconti_pll(hw);
drivers/clk/visconti/pll.c
221
spin_lock_irqsave(pll->lock, flags);
drivers/clk/visconti/pll.c
223
writel(PLL_CONFIG_SEL, pll->pll_base + PLL_CONF_REG);
drivers/clk/visconti/pll.c
225
reg = readl(pll->pll_base + PLL_CTRL_REG);
drivers/clk/visconti/pll.c
227
writel(reg, pll->pll_base + PLL_CTRL_REG);
drivers/clk/visconti/pll.c
229
reg = readl(pll->pll_base + PLL_CTRL_REG);
drivers/clk/visconti/pll.c
231
writel(reg, pll->pll_base + PLL_CTRL_REG);
drivers/clk/visconti/pll.c
233
spin_unlock_irqrestore(pll->lock, flags);
drivers/clk/visconti/pll.c
253
struct visconti_pll *pll;
drivers/clk/visconti/pll.c
266
pll = kzalloc_flex(*pll, rate_table, len);
drivers/clk/visconti/pll.c
267
if (!pll)
drivers/clk/visconti/pll.c
270
pll->rate_count = len;
drivers/clk/visconti/pll.c
271
memcpy(pll->rate_table, rate_table, len * sizeof(*pll->rate_table));
drivers/clk/visconti/pll.c
274
pll->hw.init = &init;
drivers/clk/visconti/pll.c
275
pll->pll_base = ctx->reg_base + offset;
drivers/clk/visconti/pll.c
276
pll->lock = lock;
drivers/clk/visconti/pll.c
277
pll->ctx = ctx;
drivers/clk/visconti/pll.c
279
pll_hw_clk = &pll->hw;
drivers/clk/visconti/pll.c
280
ret = clk_hw_register(NULL, &pll->hw);
drivers/clk/visconti/pll.c
283
kfree(pll);
drivers/clk/visconti/pll.c
56
static void visconti_pll_get_params(struct visconti_pll *pll,
drivers/clk/visconti/pll.c
61
val = readl(pll->pll_base + PLL_FRACMODE_REG);
drivers/clk/visconti/pll.c
66
rate_table->fracin = readl(pll->pll_base + PLL_FRACIN_REG) & PLL_FRACIN_MASK;
drivers/clk/visconti/pll.c
67
rate_table->intin = readl(pll->pll_base + PLL_INTIN_REG) & PLL_INTIN_MASK;
drivers/clk/visconti/pll.c
68
rate_table->refdiv = readl(pll->pll_base + PLL_REFDIV_REG) & PLL_REFDIV_MASK;
drivers/clk/visconti/pll.c
70
postdiv = readl(pll->pll_base + PLL_POSTDIV_REG);
drivers/clk/visconti/pll.c
75
static const struct visconti_pll_rate_table *visconti_get_pll_settings(struct visconti_pll *pll,
drivers/clk/visconti/pll.c
78
const struct visconti_pll_rate_table *rate_table = pll->rate_table;
drivers/clk/visconti/pll.c
81
for (i = 0; i < pll->rate_count; i++)
drivers/clk/visconti/pll.c
88
static unsigned long visconti_get_pll_rate_from_data(struct visconti_pll *pll,
drivers/clk/visconti/pll.c
91
const struct visconti_pll_rate_table *rate_table = pll->rate_table;
drivers/clk/visconti/pll.c
94
for (i = 0; i < pll->rate_count; i++)
drivers/clk/x86/clk-cgu-pll.c
109
pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL);
drivers/clk/x86/clk-cgu-pll.c
110
if (!pll)
drivers/clk/x86/clk-cgu-pll.c
113
pll->membase = ctx->membase;
drivers/clk/x86/clk-cgu-pll.c
114
pll->reg = list->reg;
drivers/clk/x86/clk-cgu-pll.c
115
pll->flags = list->flags;
drivers/clk/x86/clk-cgu-pll.c
116
pll->type = list->type;
drivers/clk/x86/clk-cgu-pll.c
117
pll->hw.init = &init;
drivers/clk/x86/clk-cgu-pll.c
119
hw = &pll->hw;
drivers/clk/x86/clk-cgu-pll.c
42
struct lgm_clk_pll *pll = to_lgm_clk_pll(hw);
drivers/clk/x86/clk-cgu-pll.c
45
mult = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 0, 12);
drivers/clk/x86/clk-cgu-pll.c
46
div = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 18, 6);
drivers/clk/x86/clk-cgu-pll.c
47
frac = lgm_get_clk_val(pll->membase, pll->reg, 2, 24);
drivers/clk/x86/clk-cgu-pll.c
49
if (pll->type == TYPE_LJPLL)
drivers/clk/x86/clk-cgu-pll.c
57
struct lgm_clk_pll *pll = to_lgm_clk_pll(hw);
drivers/clk/x86/clk-cgu-pll.c
60
ret = lgm_get_clk_val(pll->membase, pll->reg, 0, 1);
drivers/clk/x86/clk-cgu-pll.c
67
struct lgm_clk_pll *pll = to_lgm_clk_pll(hw);
drivers/clk/x86/clk-cgu-pll.c
71
lgm_set_clk_val(pll->membase, pll->reg, 0, 1, 1);
drivers/clk/x86/clk-cgu-pll.c
72
ret = regmap_read_poll_timeout_atomic(pll->membase, pll->reg,
drivers/clk/x86/clk-cgu-pll.c
81
struct lgm_clk_pll *pll = to_lgm_clk_pll(hw);
drivers/clk/x86/clk-cgu-pll.c
83
lgm_set_clk_val(pll->membase, pll->reg, 0, 1, 0);
drivers/clk/x86/clk-cgu-pll.c
98
struct lgm_clk_pll *pll;
drivers/clk/xilinx/xlnx_vcu.c
237
static int xvcu_pll_wait_for_lock(struct vcu_pll *pll)
drivers/clk/xilinx/xlnx_vcu.c
239
void __iomem *base = pll->reg_base;
drivers/clk/xilinx/xlnx_vcu.c
287
static int xvcu_pll_set_div(struct vcu_pll *pll, int div)
drivers/clk/xilinx/xlnx_vcu.c
289
void __iomem *base = pll->reg_base;
drivers/clk/xilinx/xlnx_vcu.c
316
struct vcu_pll *pll = to_vcu_pll(hw);
drivers/clk/xilinx/xlnx_vcu.c
319
req->rate = clamp_t(unsigned long, req->rate, pll->fvco_min,
drivers/clk/xilinx/xlnx_vcu.c
320
pll->fvco_max);
drivers/clk/xilinx/xlnx_vcu.c
333
struct vcu_pll *pll = to_vcu_pll(hw);
drivers/clk/xilinx/xlnx_vcu.c
334
void __iomem *base = pll->reg_base;
drivers/clk/xilinx/xlnx_vcu.c
347
struct vcu_pll *pll = to_vcu_pll(hw);
drivers/clk/xilinx/xlnx_vcu.c
349
return xvcu_pll_set_div(pll, rate / parent_rate);
drivers/clk/xilinx/xlnx_vcu.c
354
struct vcu_pll *pll = to_vcu_pll(hw);
drivers/clk/xilinx/xlnx_vcu.c
355
void __iomem *base = pll->reg_base;
drivers/clk/xilinx/xlnx_vcu.c
369
ret = xvcu_pll_wait_for_lock(pll);
drivers/clk/xilinx/xlnx_vcu.c
385
struct vcu_pll *pll = to_vcu_pll(hw);
drivers/clk/xilinx/xlnx_vcu.c
386
void __iomem *base = pll->reg_base;
drivers/clk/xilinx/xlnx_vcu.c
409
struct vcu_pll *pll;
drivers/clk/xilinx/xlnx_vcu.c
420
pll = devm_kmalloc(dev, sizeof(*pll), GFP_KERNEL);
drivers/clk/xilinx/xlnx_vcu.c
421
if (!pll)
drivers/clk/xilinx/xlnx_vcu.c
424
pll->hw.init = &init;
drivers/clk/xilinx/xlnx_vcu.c
425
pll->reg_base = reg_base;
drivers/clk/xilinx/xlnx_vcu.c
426
pll->fvco_min = FVCO_MIN;
drivers/clk/xilinx/xlnx_vcu.c
427
pll->fvco_max = FVCO_MAX;
drivers/clk/xilinx/xlnx_vcu.c
429
hw = &pll->hw;
drivers/clk/xilinx/xlnx_vcu.c
434
clk_hw_set_rate_range(hw, pll->fvco_min, pll->fvco_max);
drivers/clk/xilinx/xlnx_vcu.c
548
xvcu->pll = hw;
drivers/clk/xilinx/xlnx_vcu.c
550
hw = xvcu_register_pll_post(dev, "vcu_pll_post", xvcu->pll, reg_base);
drivers/clk/xilinx/xlnx_vcu.c
68
struct clk_hw *pll;
drivers/clk/zynq/pll.c
190
struct zynq_pll *pll;
drivers/clk/zynq/pll.c
203
pll = kmalloc_obj(*pll);
drivers/clk/zynq/pll.c
204
if (!pll)
drivers/clk/zynq/pll.c
208
pll->hw.init = &initd;
drivers/clk/zynq/pll.c
209
pll->pll_ctrl = pll_ctrl;
drivers/clk/zynq/pll.c
210
pll->pll_status = pll_status;
drivers/clk/zynq/pll.c
211
pll->lockbit = lock_index;
drivers/clk/zynq/pll.c
212
pll->lock = lock;
drivers/clk/zynq/pll.c
214
spin_lock_irqsave(pll->lock, flags);
drivers/clk/zynq/pll.c
216
reg = readl(pll->pll_ctrl);
drivers/clk/zynq/pll.c
218
writel(reg, pll->pll_ctrl);
drivers/clk/zynq/pll.c
220
spin_unlock_irqrestore(pll->lock, flags);
drivers/clk/zynq/pll.c
222
clk = clk_register(NULL, &pll->hw);
drivers/clk/zynq/pll.c
229
kfree(pll);
drivers/clk/zynqmp/pll.c
316
struct zynqmp_pll *pll;
drivers/clk/zynqmp/pll.c
329
pll = kzalloc_obj(*pll);
drivers/clk/zynqmp/pll.c
330
if (!pll)
drivers/clk/zynqmp/pll.c
333
pll->hw.init = &init;
drivers/clk/zynqmp/pll.c
334
pll->clk_id = clk_id;
drivers/clk/zynqmp/pll.c
336
hw = &pll->hw;
drivers/clk/zynqmp/pll.c
339
kfree(pll);
drivers/cpufreq/cpufreq-nforce2.c
116
static void nforce2_write_pll(int pll)
drivers/cpufreq/cpufreq-nforce2.c
125
pci_write_config_dword(nforce2_dev, NFORCE2_PLLREG, pll);
drivers/cpufreq/cpufreq-nforce2.c
174
int pll = 0;
drivers/cpufreq/cpufreq-nforce2.c
190
pll = nforce2_calc_pll(tfsb);
drivers/cpufreq/cpufreq-nforce2.c
192
if (pll < 0)
drivers/cpufreq/cpufreq-nforce2.c
195
nforce2_write_pll(pll);
drivers/cpufreq/cpufreq-nforce2.c
214
pll = nforce2_calc_pll(tfsb);
drivers/cpufreq/cpufreq-nforce2.c
215
if (pll == -1)
drivers/cpufreq/cpufreq-nforce2.c
218
nforce2_write_pll(pll);
drivers/cpufreq/cpufreq-nforce2.c
67
static int nforce2_calc_fsb(int pll)
drivers/cpufreq/cpufreq-nforce2.c
71
mul = (pll >> 8) & 0xff;
drivers/cpufreq/cpufreq-nforce2.c
72
div = pll & 0xff;
drivers/cpufreq/pmac32-cpufreq.c
47
extern void low_choose_750fx_pll(int pll);
drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c
123
struct amdgpu_pll *pll,
drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c
131
unsigned target_clock = pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV ?
drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c
141
fb_div_min = pll->min_feedback_div;
drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c
142
fb_div_max = pll->max_feedback_div;
drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c
144
if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) {
drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c
150
if (pll->flags & AMDGPU_PLL_USE_REF_DIV)
drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c
151
ref_div_min = pll->reference_div;
drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c
153
ref_div_min = pll->min_ref_div;
drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c
155
if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV &&
drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c
156
pll->flags & AMDGPU_PLL_USE_REF_DIV)
drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c
157
ref_div_max = pll->reference_div;
drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c
159
ref_div_max = pll->max_ref_div;
drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c
162
if (pll->flags & AMDGPU_PLL_USE_POST_DIV) {
drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c
163
post_div_min = pll->post_div;
drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c
164
post_div_max = pll->post_div;
drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c
168
if (pll->flags & AMDGPU_PLL_IS_LCD) {
drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c
169
vco_min = pll->lcd_pll_out_min;
drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c
170
vco_max = pll->lcd_pll_out_max;
drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c
172
vco_min = pll->pll_out_min;
drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c
173
vco_max = pll->pll_out_max;
drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c
176
if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) {
drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c
184
if (post_div_min < pll->min_post_div)
drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c
185
post_div_min = pll->min_post_div;
drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c
190
if (post_div_max > pll->max_post_div)
drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c
191
post_div_max = pll->max_post_div;
drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c
196
den = pll->reference_freq;
drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c
202
if (pll->flags & AMDGPU_PLL_PREFER_MINM_OVER_MAXP)
drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c
212
diff = abs(target_clock - (pll->reference_freq * fb_div) /
drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c
216
!(pll->flags & AMDGPU_PLL_PREFER_MINM_OVER_MAXP))) {
drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c
233
if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c
243
if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) {
drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c
251
*dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c
252
(pll->reference_freq * *frac_fb_div_p)) /
drivers/gpu/drm/amd/amdgpu/amdgpu_pll.h
28
struct amdgpu_pll *pll,
drivers/gpu/drm/amd/amdgpu/atombios_crtc.c
826
struct amdgpu_pll *pll;
drivers/gpu/drm/amd/amdgpu/atombios_crtc.c
836
pll = &adev->clock.ppll[0];
drivers/gpu/drm/amd/amdgpu/atombios_crtc.c
839
pll = &adev->clock.ppll[1];
drivers/gpu/drm/amd/amdgpu/atombios_crtc.c
844
pll = &adev->clock.ppll[2];
drivers/gpu/drm/amd/amdgpu/atombios_crtc.c
849
pll->flags = amdgpu_crtc->pll_flags;
drivers/gpu/drm/amd/amdgpu/atombios_crtc.c
850
pll->reference_div = amdgpu_crtc->pll_reference_div;
drivers/gpu/drm/amd/amdgpu/atombios_crtc.c
851
pll->post_div = amdgpu_crtc->pll_post_div;
drivers/gpu/drm/amd/amdgpu/atombios_crtc.c
853
amdgpu_pll_compute(adev, pll, amdgpu_crtc->adjusted_clock, &pll_clock,
drivers/gpu/drm/amd/amdgpu/atombios_crtc.c
875
(125 * 25 * pll->reference_freq / 100);
drivers/gpu/drm/amd/amdgpu/atombios_crtc.c
878
(125 * 25 * pll->reference_freq / 100);
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
2238
int pll;
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
2246
pll = amdgpu_pll_get_shared_dp_ppll(crtc);
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
2247
if (pll != ATOM_PPLL_INVALID)
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
2248
return pll;
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
2252
pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
2253
if (pll != ATOM_PPLL_INVALID)
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
2254
return pll;
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
2217
int pll;
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
2227
pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
2228
if (pll != ATOM_PPLL_INVALID)
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
2229
return pll;
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
2146
int pll;
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
2154
pll = amdgpu_pll_get_shared_dp_ppll(crtc);
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
2155
if (pll != ATOM_PPLL_INVALID)
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
2156
return pll;
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
2160
pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
2161
if (pll != ATOM_PPLL_INVALID)
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
2162
return pll;
drivers/gpu/drm/bridge/tc358768.c
398
u32 pll, diff, pll_in;
drivers/gpu/drm/bridge/tc358768.c
400
pll = (u32)div_u64((u64)refclk * fbd, divisor);
drivers/gpu/drm/bridge/tc358768.c
402
if (pll >= max_pll || pll < min_pll)
drivers/gpu/drm/bridge/tc358768.c
409
diff = max(pll, target_pll) - min(pll, target_pll);
drivers/gpu/drm/bridge/tc358768.c
413
best_pll = pll;
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
248
struct hibmc_display_panel_pll pll = {0};
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
259
pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_POD, pll.POD);
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
260
pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_OD, pll.OD);
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
261
pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_N, pll.N);
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
262
pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_M, pll.M);
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
267
static void set_vclock_hisilicon(struct drm_device *dev, u64 pll)
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
279
writel(pll, priv->mmio + CRT_PLL1_HS);
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
283
val = pll & ~(CRT_PLL1_HS_POWERON(1));
drivers/gpu/drm/i915/display/icl_dsi.c
675
struct intel_dpll *pll = crtc_state->intel_dpll;
drivers/gpu/drm/i915/display/icl_dsi.c
684
val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1206
.pll[0] = 0x4,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1207
.pll[1] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1208
.pll[2] = 0xB2,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1209
.pll[3] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1210
.pll[4] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1211
.pll[5] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1212
.pll[6] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1213
.pll[7] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1214
.pll[8] = 0x20,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1215
.pll[9] = 0x1,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1216
.pll[10] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1217
.pll[11] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1218
.pll[12] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1219
.pll[13] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1220
.pll[14] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1221
.pll[15] = 0xD,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1222
.pll[16] = 0x6,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1223
.pll[17] = 0x8F,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1224
.pll[18] = 0x84,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1225
.pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1231
.pll[0] = 0x34,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1232
.pll[1] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1233
.pll[2] = 0xC0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1234
.pll[3] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1235
.pll[4] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1236
.pll[5] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1237
.pll[6] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1238
.pll[7] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1239
.pll[8] = 0x20,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1240
.pll[9] = 0x1,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1241
.pll[10] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1242
.pll[11] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1243
.pll[12] = 0x80,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1244
.pll[13] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1245
.pll[14] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1246
.pll[15] = 0xD,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1247
.pll[16] = 0x6,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1248
.pll[17] = 0xCF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1249
.pll[18] = 0x84,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1250
.pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1256
.pll[0] = 0xF4,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1257
.pll[1] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1258
.pll[2] = 0x7A,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1259
.pll[3] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1260
.pll[4] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1261
.pll[5] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1262
.pll[6] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1263
.pll[7] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1264
.pll[8] = 0x20,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1265
.pll[9] = 0x1,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1266
.pll[10] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1267
.pll[11] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1268
.pll[12] = 0x58,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1269
.pll[13] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1270
.pll[14] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1271
.pll[15] = 0xB,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1272
.pll[16] = 0x6,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1273
.pll[17] = 0xF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1274
.pll[18] = 0x85,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1275
.pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1281
.pll[0] = 0xF4,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1282
.pll[1] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1283
.pll[2] = 0x7A,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1284
.pll[3] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1285
.pll[4] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1286
.pll[5] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1287
.pll[6] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1288
.pll[7] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1289
.pll[8] = 0x20,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1290
.pll[9] = 0x1,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1291
.pll[10] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1292
.pll[11] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1293
.pll[12] = 0x58,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1294
.pll[13] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1295
.pll[14] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1296
.pll[15] = 0xA,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1297
.pll[16] = 0x6,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1298
.pll[17] = 0xF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1299
.pll[18] = 0x85,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1300
.pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1306
.pll[0] = 0xF4,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1307
.pll[1] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1308
.pll[2] = 0x7A,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1309
.pll[3] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1310
.pll[4] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1311
.pll[5] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1312
.pll[6] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1313
.pll[7] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1314
.pll[8] = 0x20,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1315
.pll[9] = 0x1,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1316
.pll[10] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1317
.pll[11] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1318
.pll[12] = 0x58,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1319
.pll[13] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1320
.pll[14] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1321
.pll[15] = 0x8,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1322
.pll[16] = 0x6,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1323
.pll[17] = 0xF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1324
.pll[18] = 0x85,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1325
.pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1332
.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1333
.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1334
.pll[10] = 0xFF, .pll[11] = 0xCC, .pll[12] = 0x9C, .pll[13] = 0xCB, .pll[14] = 0xCC,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1335
.pll[15] = 0x0D, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1341
.pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xCC, .pll[3] = 0x00, .pll[4] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1342
.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1343
.pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x00, .pll[13] = 0x00, .pll[14] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1344
.pll[15] = 0x0D, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1350
.pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xDC, .pll[3] = 0x00, .pll[4] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1351
.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1352
.pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x00, .pll[13] = 0x00, .pll[14] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1353
.pll[15] = 0x0D, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1359
.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x62, .pll[3] = 0x00, .pll[4] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1360
.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1361
.pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0xA0, .pll[13] = 0x00, .pll[14] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1362
.pll[15] = 0x0C, .pll[16] = 0x09, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1368
.pll[0] = 0xC4, .pll[1] = 0x00, .pll[2] = 0x76, .pll[3] = 0x00, .pll[4] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1369
.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1370
.pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x00, .pll[13] = 0x00, .pll[14] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1371
.pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1377
.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1378
.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1379
.pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x55, .pll[13] = 0x55, .pll[14] = 0x55,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1380
.pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1386
.pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1387
.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1388
.pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x20, .pll[13] = 0x00, .pll[14] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1389
.pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1395
.pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xB0, .pll[3] = 0x00, .pll[4] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1396
.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1397
.pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x2A, .pll[13] = 0xA9, .pll[14] = 0xAA,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1398
.pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1404
.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xCE, .pll[3] = 0x00, .pll[4] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1405
.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1406
.pll[10] = 0xFF, .pll[11] = 0x77, .pll[12] = 0x57, .pll[13] = 0x77, .pll[14] = 0x77,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1407
.pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1413
.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1414
.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1415
.pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xD5, .pll[13] = 0x55, .pll[14] = 0x55,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1416
.pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1422
.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x66, .pll[3] = 0x00, .pll[4] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1423
.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1424
.pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xB5, .pll[13] = 0x55, .pll[14] = 0x55,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1425
.pll[15] = 0x0B, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1431
.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x72, .pll[3] = 0x00, .pll[4] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1432
.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1433
.pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xF5, .pll[13] = 0x55, .pll[14] = 0x55,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1434
.pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1440
.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1441
.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1442
.pll[10] = 0xFF, .pll[11] = 0x44, .pll[12] = 0x44, .pll[13] = 0x44, .pll[14] = 0x44,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1443
.pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1449
.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7C, .pll[3] = 0x00, .pll[4] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1450
.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1451
.pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x20, .pll[13] = 0x00, .pll[14] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1452
.pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1458
.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x84, .pll[3] = 0x00, .pll[4] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1459
.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1460
.pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x08, .pll[13] = 0x00, .pll[14] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1461
.pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1467
.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x92, .pll[3] = 0x00, .pll[4] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1468
.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1469
.pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x10, .pll[13] = 0x00, .pll[14] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1470
.pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1476
.pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0x98, .pll[3] = 0x00, .pll[4] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1477
.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1478
.pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x72, .pll[13] = 0xA9, .pll[14] = 0xAA,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1479
.pll[15] = 0x0B, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1485
.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBC, .pll[3] = 0x00, .pll[4] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1486
.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1487
.pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0xF0, .pll[13] = 0x00, .pll[14] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1488
.pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1494
.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1495
.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1496
.pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x80, .pll[13] = 0x00, .pll[14] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1497
.pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1503
.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1504
.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1505
.pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x50, .pll[13] = 0x00, .pll[14] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1506
.pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1512
.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD6, .pll[3] = 0x00, .pll[4] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1513
.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1514
.pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xF5, .pll[13] = 0x55, .pll[14] = 0x55,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1515
.pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1521
.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6C, .pll[3] = 0x00, .pll[4] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1522
.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1523
.pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x50, .pll[13] = 0x00, .pll[14] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1524
.pll[15] = 0x0A, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1530
.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x70, .pll[3] = 0x00, .pll[4] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1531
.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1532
.pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x22, .pll[13] = 0xA9, .pll[14] = 0xAA,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1533
.pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1539
.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x78, .pll[3] = 0x00, .pll[4] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1540
.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1541
.pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xA5, .pll[13] = 0x55, .pll[14] = 0x55,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1542
.pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1548
.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1549
.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1550
.pll[10] = 0xFF, .pll[11] = 0x44, .pll[12] = 0x44, .pll[13] = 0x44, .pll[14] = 0x44,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1551
.pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1557
.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x80, .pll[3] = 0x00, .pll[4] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1558
.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1559
.pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x35, .pll[13] = 0x55, .pll[14] = 0x55,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1560
.pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1566
.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x88, .pll[3] = 0x00, .pll[4] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1567
.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1568
.pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x60, .pll[13] = 0x00, .pll[14] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1569
.pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1575
.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x8C, .pll[3] = 0x00, .pll[4] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1576
.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1577
.pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0xFA, .pll[13] = 0xA9, .pll[14] = 0xAA,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1578
.pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1584
.pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1585
.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1586
.pll[10] = 0xFF, .pll[11] = 0x99, .pll[12] = 0x05, .pll[13] = 0x98, .pll[14] = 0x99,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1587
.pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1593
.pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1594
.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1595
.pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x20, .pll[13] = 0x00, .pll[14] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1596
.pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1602
.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBA, .pll[3] = 0x00, .pll[4] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1603
.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1604
.pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x45, .pll[13] = 0x55, .pll[14] = 0x55,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1605
.pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1611
.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xDA, .pll[3] = 0x00, .pll[4] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1612
.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1613
.pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0xC8, .pll[13] = 0x00, .pll[14] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1614
.pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1620
.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x68, .pll[3] = 0x00, .pll[4] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1621
.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1622
.pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x6C, .pll[13] = 0xA9, .pll[14] = 0xAA,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1623
.pll[15] = 0x09, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1629
.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6A, .pll[3] = 0x00, .pll[4] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1630
.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1631
.pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0xEC, .pll[13] = 0x00, .pll[14] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1632
.pll[15] = 0x09, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1638
.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1639
.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1640
.pll[10] = 0xFF, .pll[11] = 0x33, .pll[12] = 0x44, .pll[13] = 0x33, .pll[14] = 0x33,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1641
.pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1647
.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1648
.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1649
.pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x58, .pll[13] = 0x00, .pll[14] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1650
.pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1656
.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1657
.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1658
.pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x44, .pll[13] = 0xA9, .pll[14] = 0xAA,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1659
.pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1665
.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xE2, .pll[3] = 0x00, .pll[4] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1666
.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1667
.pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x9F, .pll[13] = 0x55, .pll[14] = 0x55,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1668
.pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1674
.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1675
.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1676
.pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x15, .pll[13] = 0x55, .pll[14] = 0x55,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1677
.pll[15] = 0x08, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1683
.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1684
.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1685
.pll[10] = 0xFF, .pll[11] = 0x3B, .pll[12] = 0x44, .pll[13] = 0xBA, .pll[14] = 0xBB,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
1686
.pll[15] = 0x08, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2003
return memchr_inv(&pll_state->pll[C10_PLL_SSC_REG_START_IDX],
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2004
0, sizeof(pll_state->pll[0]) * C10_PLL_SSC_REG_COUNT);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2016
drm_WARN_ON(display->drm, ARRAY_SIZE(pll_state->c10.pll) <
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2021
pll_state->c10.pll[i] = 0;
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2026
return !REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state->pll[15]);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2048
if (pll_state->pll[0] & C10_PLL0_FRACEN) {
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2049
frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11];
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2050
frac_rem = pll_state->pll[14] << 8 | pll_state->pll[13];
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2051
frac_den = pll_state->pll[10] << 8 | pll_state->pll[9];
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2054
multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, pll_state->pll[3]) << 8 |
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2055
pll_state->pll[2]) / 2 + 16;
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2057
tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, pll_state->pll[15]);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2058
hdmi_div = REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state->pll[15]);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2258
for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2259
pll_state->pll[i] = intel_cx0_read(encoder, lane, PHY_C10_VDR_PLL(i));
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2285
for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2287
pll_state->pll[i],
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2309
fracen = hw_state->pll[0] & C10_PLL0_FRACEN;
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2313
frac_quot = hw_state->pll[12] << 8 | hw_state->pll[11];
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2314
frac_rem = hw_state->pll[14] << 8 | hw_state->pll[13];
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2315
frac_den = hw_state->pll[10] << 8 | hw_state->pll[9];
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2320
multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, hw_state->pll[3]) << 8 |
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2321
hw_state->pll[2]) / 2 + 16;
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2322
tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, hw_state->pll[15]);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2329
BUILD_BUG_ON(ARRAY_SIZE(hw_state->pll) % 4);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2330
for (i = 0; i < ARRAY_SIZE(hw_state->pll); i = i + 4)
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2333
i, hw_state->pll[i], i + 1, hw_state->pll[i + 1],
drivers/gpu/drm/i915/display/intel_cx0_phy.c
2334
i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]);
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3284
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3412
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
3636
if (memcmp(&a->pll, &b->pll, sizeof(a->pll)) != 0)
drivers/gpu/drm/i915/display/intel_cx0_phy.c
557
.pll[0] = 0xB4,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
558
.pll[1] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
559
.pll[2] = 0x30,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
560
.pll[3] = 0x1,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
561
.pll[4] = 0x26,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
562
.pll[5] = 0x0C,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
563
.pll[6] = 0x98,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
564
.pll[7] = 0x46,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
565
.pll[8] = 0x1,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
566
.pll[9] = 0x1,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
567
.pll[10] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
568
.pll[11] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
569
.pll[12] = 0xC0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
570
.pll[13] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
571
.pll[14] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
572
.pll[15] = 0x2,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
573
.pll[16] = 0x84,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
574
.pll[17] = 0x4F,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
575
.pll[18] = 0xE5,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
576
.pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
582
.pll[0] = 0x4,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
583
.pll[1] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
584
.pll[2] = 0xA2,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
585
.pll[3] = 0x1,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
586
.pll[4] = 0x33,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
587
.pll[5] = 0x10,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
588
.pll[6] = 0x75,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
589
.pll[7] = 0xB3,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
590
.pll[8] = 0x1,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
591
.pll[9] = 0x1,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
592
.pll[10] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
593
.pll[11] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
594
.pll[12] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
595
.pll[13] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
596
.pll[14] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
597
.pll[15] = 0x2,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
598
.pll[16] = 0x85,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
599
.pll[17] = 0x0F,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
600
.pll[18] = 0xE6,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
601
.pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
607
.pll[0] = 0x34,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
608
.pll[1] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
609
.pll[2] = 0xDA,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
610
.pll[3] = 0x1,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
611
.pll[4] = 0x39,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
612
.pll[5] = 0x12,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
613
.pll[6] = 0xE3,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
614
.pll[7] = 0xE9,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
615
.pll[8] = 0x1,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
616
.pll[9] = 0x1,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
617
.pll[10] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
618
.pll[11] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
619
.pll[12] = 0x20,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
620
.pll[13] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
621
.pll[14] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
622
.pll[15] = 0x2,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
623
.pll[16] = 0x85,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
624
.pll[17] = 0x8F,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
625
.pll[18] = 0xE6,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
626
.pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
632
.pll[0] = 0xF4,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
633
.pll[1] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
634
.pll[2] = 0xF8,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
635
.pll[3] = 0x0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
636
.pll[4] = 0x20,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
637
.pll[5] = 0x0A,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
638
.pll[6] = 0x29,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
639
.pll[7] = 0x10,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
640
.pll[8] = 0x1, /* Verify */
drivers/gpu/drm/i915/display/intel_cx0_phy.c
641
.pll[9] = 0x1,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
642
.pll[10] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
643
.pll[11] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
644
.pll[12] = 0xA0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
645
.pll[13] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
646
.pll[14] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
647
.pll[15] = 0x1,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
648
.pll[16] = 0x84,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
649
.pll[17] = 0x4F,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
650
.pll[18] = 0xE5,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
651
.pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
657
.pll[0] = 0xB4,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
658
.pll[1] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
659
.pll[2] = 0x30,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
660
.pll[3] = 0x1,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
661
.pll[4] = 0x26,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
662
.pll[5] = 0x0C,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
663
.pll[6] = 0x98,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
664
.pll[7] = 0x46,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
665
.pll[8] = 0x1,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
666
.pll[9] = 0x1,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
667
.pll[10] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
668
.pll[11] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
669
.pll[12] = 0xC0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
670
.pll[13] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
671
.pll[14] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
672
.pll[15] = 0x1,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
673
.pll[16] = 0x85,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
674
.pll[17] = 0x4F,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
675
.pll[18] = 0xE6,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
676
.pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
682
.pll[0] = 0x4,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
683
.pll[1] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
684
.pll[2] = 0xA2,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
685
.pll[3] = 0x1,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
686
.pll[4] = 0x33,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
687
.pll[5] = 0x10,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
688
.pll[6] = 0x75,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
689
.pll[7] = 0xB3,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
690
.pll[8] = 0x1,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
691
.pll[9] = 0x1,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
692
.pll[10] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
693
.pll[11] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
694
.pll[12] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
695
.pll[13] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
696
.pll[14] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
697
.pll[15] = 0x1,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
698
.pll[16] = 0x85,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
699
.pll[17] = 0x0F,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
700
.pll[18] = 0xE6,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
701
.pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
707
.pll[0] = 0xF4,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
708
.pll[1] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
709
.pll[2] = 0xF8,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
710
.pll[3] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
711
.pll[4] = 0x20,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
712
.pll[5] = 0x0A,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
713
.pll[6] = 0x29,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
714
.pll[7] = 0x10,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
715
.pll[8] = 0x1,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
716
.pll[9] = 0x1,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
717
.pll[10] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
718
.pll[11] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
719
.pll[12] = 0xA0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
720
.pll[13] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
721
.pll[14] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
722
.pll[15] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
723
.pll[16] = 0x84,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
724
.pll[17] = 0x4F,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
725
.pll[18] = 0xE5,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
726
.pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
732
.pll[0] = 0xB4,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
733
.pll[1] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
734
.pll[2] = 0x3E,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
735
.pll[3] = 0x1,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
736
.pll[4] = 0xA8,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
737
.pll[5] = 0x0C,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
738
.pll[6] = 0x33,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
739
.pll[7] = 0x54,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
740
.pll[8] = 0x1,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
741
.pll[9] = 0x1,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
742
.pll[10] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
743
.pll[11] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
744
.pll[12] = 0xC8,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
745
.pll[13] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
746
.pll[14] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
747
.pll[15] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
748
.pll[16] = 0x85,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
749
.pll[17] = 0x8F,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
750
.pll[18] = 0xE6,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
751
.pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
757
.pll[0] = 0x34,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
758
.pll[1] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
759
.pll[2] = 0x84,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
760
.pll[3] = 0x1,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
761
.pll[4] = 0x30,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
762
.pll[5] = 0x0F,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
763
.pll[6] = 0x3D,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
764
.pll[7] = 0x98,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
765
.pll[8] = 0x1,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
766
.pll[9] = 0x1,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
767
.pll[10] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
768
.pll[11] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
769
.pll[12] = 0xF0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
770
.pll[13] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
771
.pll[14] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
772
.pll[15] = 0,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
773
.pll[16] = 0x84,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
774
.pll[17] = 0x0F,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
775
.pll[18] = 0xE5,
drivers/gpu/drm/i915/display/intel_cx0_phy.c
776
.pll[19] = 0x23,
drivers/gpu/drm/i915/display/intel_cx0_phy.h
33
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_cx0_phy.h
77
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_ddi.c
1606
const struct intel_dpll *pll = crtc_state->intel_dpll;
drivers/gpu/drm/i915/display/intel_ddi.c
1609
if (drm_WARN_ON(display->drm, !pll))
drivers/gpu/drm/i915/display/intel_ddi.c
1614
pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy),
drivers/gpu/drm/i915/display/intel_ddi.c
1650
const struct intel_dpll *pll = crtc_state->intel_dpll;
drivers/gpu/drm/i915/display/intel_ddi.c
1653
if (drm_WARN_ON(display->drm, !pll))
drivers/gpu/drm/i915/display/intel_ddi.c
1658
RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
drivers/gpu/drm/i915/display/intel_ddi.c
1694
const struct intel_dpll *pll = crtc_state->intel_dpll;
drivers/gpu/drm/i915/display/intel_ddi.c
1697
if (drm_WARN_ON(display->drm, !pll))
drivers/gpu/drm/i915/display/intel_ddi.c
1705
(pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) ||
drivers/gpu/drm/i915/display/intel_ddi.c
1706
(pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)))
drivers/gpu/drm/i915/display/intel_ddi.c
1711
DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
drivers/gpu/drm/i915/display/intel_ddi.c
1760
const struct intel_dpll *pll = crtc_state->intel_dpll;
drivers/gpu/drm/i915/display/intel_ddi.c
1763
if (drm_WARN_ON(display->drm, !pll))
drivers/gpu/drm/i915/display/intel_ddi.c
1768
ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
drivers/gpu/drm/i915/display/intel_ddi.c
1804
const struct intel_dpll *pll = crtc_state->intel_dpll;
drivers/gpu/drm/i915/display/intel_ddi.c
1807
if (drm_WARN_ON(display->drm, !pll))
drivers/gpu/drm/i915/display/intel_ddi.c
1847
const struct intel_dpll *pll = crtc_state->intel_dpll;
drivers/gpu/drm/i915/display/intel_ddi.c
1851
if (drm_WARN_ON(display->drm, !pll))
drivers/gpu/drm/i915/display/intel_ddi.c
1955
const struct intel_dpll *pll = crtc_state->intel_dpll;
drivers/gpu/drm/i915/display/intel_ddi.c
1958
if (drm_WARN_ON(display->drm, !pll))
drivers/gpu/drm/i915/display/intel_ddi.c
1966
DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
drivers/gpu/drm/i915/display/intel_ddi.c
2023
const struct intel_dpll *pll = crtc_state->intel_dpll;
drivers/gpu/drm/i915/display/intel_ddi.c
2026
if (drm_WARN_ON(display->drm, !pll))
drivers/gpu/drm/i915/display/intel_ddi.c
2029
intel_de_write(display, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
drivers/gpu/drm/i915/display/intel_ddi.c
246
static u32 hsw_pll_to_ddi_pll_sel(const struct intel_dpll *pll)
drivers/gpu/drm/i915/display/intel_ddi.c
248
switch (pll->info->id) {
drivers/gpu/drm/i915/display/intel_ddi.c
262
MISSING_CASE(pll->info->id);
drivers/gpu/drm/i915/display/intel_ddi.c
270
const struct intel_dpll *pll = crtc_state->intel_dpll;
drivers/gpu/drm/i915/display/intel_ddi.c
272
const enum intel_dpll_id id = pll->info->id;
drivers/gpu/drm/i915/display/intel_ddi.c
4229
struct intel_dpll *pll)
drivers/gpu/drm/i915/display/intel_ddi.c
4236
if (drm_WARN_ON(display->drm, !pll))
drivers/gpu/drm/i915/display/intel_ddi.c
4239
port_dpll->pll = pll;
drivers/gpu/drm/i915/display/intel_ddi.c
4240
pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state);
drivers/gpu/drm/i915/display/intel_ddi.c
4249
static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll)
drivers/gpu/drm/i915/display/intel_ddi.c
4251
return pll->info->id == DPLL_ID_ICL_TBTPLL;
drivers/gpu/drm/i915/display/intel_ddi.c
4261
struct intel_dpll *pll;
drivers/gpu/drm/i915/display/intel_ddi.c
4265
pll = intel_get_dpll_by_id(display, pll_id);
drivers/gpu/drm/i915/display/intel_ddi.c
4267
if (drm_WARN_ON(display->drm, !pll))
drivers/gpu/drm/i915/display/intel_ddi.c
4270
port_dpll->pll = pll;
drivers/gpu/drm/i915/display/intel_ddi.c
4271
pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state);
drivers/gpu/drm/i915/display/intel_ddi.c
4355
const struct intel_dpll *pll = crtc_state->intel_dpll;
drivers/gpu/drm/i915/display/intel_ddi.c
4357
if (drm_WARN_ON(display->drm, !pll))
drivers/gpu/drm/i915/display/intel_ddi.c
4360
if (icl_ddi_tc_pll_is_tbt(pll))
drivers/gpu/drm/i915/display/intel_ddi.c
4378
struct intel_dpll *pll)
drivers/gpu/drm/i915/display/intel_ddi.c
4385
if (drm_WARN_ON(display->drm, !pll))
drivers/gpu/drm/i915/display/intel_ddi.c
4388
if (icl_ddi_tc_pll_is_tbt(pll))
drivers/gpu/drm/i915/display/intel_ddi.c
4395
port_dpll->pll = pll;
drivers/gpu/drm/i915/display/intel_ddi.c
4396
pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state);
drivers/gpu/drm/i915/display/intel_ddi.h
43
struct intel_dpll *pll);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
637
struct intel_dpll *pll;
drivers/gpu/drm/i915/display/intel_display_debugfs.c
646
for_each_dpll(display, pll, i) {
drivers/gpu/drm/i915/display/intel_display_debugfs.c
647
drm_printf(&p, "DPLL%i: %s, id: %i\n", pll->index,
drivers/gpu/drm/i915/display/intel_display_debugfs.c
648
pll->info->name, pll->info->id);
drivers/gpu/drm/i915/display/intel_display_debugfs.c
650
pll->state.pipe_mask, pll->active_mask,
drivers/gpu/drm/i915/display/intel_display_debugfs.c
651
str_yes_no(pll->on));
drivers/gpu/drm/i915/display/intel_display_debugfs.c
653
intel_dpll_dump_hw_state(display, &p, &pll->state.hw_state);
drivers/gpu/drm/i915/display/intel_display_reg_defs.h
55
#define _PLL(pll, a, b) _PICK_EVEN(pll, a, b)
drivers/gpu/drm/i915/display/intel_display_reg_defs.h
62
#define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
drivers/gpu/drm/i915/display/intel_display_regs.h
1992
#define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
drivers/gpu/drm/i915/display/intel_display_regs.h
1996
#define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0)
drivers/gpu/drm/i915/display/intel_display_regs.h
2001
#define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1)
drivers/gpu/drm/i915/display/intel_display_regs.h
2676
#define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)
drivers/gpu/drm/i915/display/intel_display_regs.h
2703
#define PORT_CLK_SEL_WRPLL(pll) REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4 + (pll))
drivers/gpu/drm/i915/display/intel_display_regs.h
2874
#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
drivers/gpu/drm/i915/display/intel_display_regs.h
2878
#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \
drivers/gpu/drm/i915/display/intel_display_regs.h
2879
((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
drivers/gpu/drm/i915/display/intel_display_regs.h
2890
#define _DG1_DPCLKA_PLL_IDX(pll) ((pll) % 2)
drivers/gpu/drm/i915/display/intel_display_regs.h
2896
#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) (_DG1_DPCLKA_PLL_IDX(pll) << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
drivers/gpu/drm/i915/display/intel_display_regs.h
2929
#define ICL_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \
drivers/gpu/drm/i915/display/intel_display_regs.h
2935
#define DG2_PLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \
drivers/gpu/drm/i915/display/intel_display_regs.h
2950
#define DG1_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
drivers/gpu/drm/i915/display/intel_display_regs.h
2963
#define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \
drivers/gpu/drm/i915/display/intel_display_regs.h
2984
#define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
drivers/gpu/drm/i915/display/intel_display_regs.h
3011
#define TGL_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
drivers/gpu/drm/i915/display/intel_display_regs.h
3014
#define RKL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \
drivers/gpu/drm/i915/display/intel_display_regs.h
3019
#define TGL_DPLL0_DIV0(pll) _MMIO_PLL(pll, _TGL_DPLL0_DIV0, _TGL_DPLL1_DIV0)
drivers/gpu/drm/i915/display/intel_display_regs.h
3026
#define TGL_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
drivers/gpu/drm/i915/display/intel_display_regs.h
3029
#define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \
drivers/gpu/drm/i915/display/intel_display_regs.h
3034
#define DG1_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
drivers/gpu/drm/i915/display/intel_display_regs.h
3040
#define DG1_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
drivers/gpu/drm/i915/display/intel_display_regs.h
3047
#define ADLS_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
drivers/gpu/drm/i915/display/intel_display_regs.h
3053
#define ADLS_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
drivers/gpu/drm/i915/display/intel_display_types.h
1156
struct intel_dpll *pll;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1016
const struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1114
struct intel_dpll *pll;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1133
pll = intel_get_dpll_by_id(display, pll_id);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1135
if (!pll)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1138
return pll;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1142
const struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1147
switch (pll->info->id) {
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1194
const struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1241
struct intel_dpll *pll = NULL;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1244
pll = hsw_ddi_wrpll_get_dpll(state, crtc);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1246
pll = hsw_ddi_lcpll_get_dpll(crtc_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1248
pll = hsw_ddi_spll_get_dpll(state, crtc);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1250
if (!pll)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1254
pll, &crtc_state->dpll_hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1256
crtc_state->intel_dpll = pll;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
128
struct intel_dpll *pll;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1305
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1311
struct intel_dpll *pll)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1316
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
132
for_each_dpll(display, pll, i)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
133
dpll_state[pll->index] = pll->state;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1384
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1387
const enum intel_dpll_id id = pll->info->id;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1398
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1403
const enum intel_dpll_id id = pll->info->id;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1405
skl_ddi_pll_write_ctrl1(display, pll, hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1420
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1425
skl_ddi_pll_write_ctrl1(display, pll, hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1429
struct intel_dpll *pll)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1432
const enum intel_dpll_id id = pll->info->id;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1440
struct intel_dpll *pll)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1445
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1450
const enum intel_dpll_id id = pll->info->id;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1483
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1488
const enum intel_dpll_id id = pll->info->id;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
166
struct intel_dpll *pll;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
169
for_each_dpll(display, pll, i) {
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
170
if (pll->info->id == id)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
171
return pll;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1756
const struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
180
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
186
if (drm_WARN(display->drm, !pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
190
cur_state = intel_dpll_get_hw_state(display, pll, &hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1904
const struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
193
pll->info->name, str_on_off(state),
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1959
struct intel_dpll *pll;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1962
pll = intel_find_dpll(state, crtc,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1966
pll = intel_find_dpll(state, crtc,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1971
if (!pll)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1975
pll, &crtc_state->dpll_hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1977
crtc_state->intel_dpll = pll;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1983
const struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1993
return skl_ddi_wrpll_get_freq(display, pll, dpll_hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1995
return skl_ddi_lcpll_get_freq(display, pll, dpll_hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2058
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2062
enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2165
struct intel_dpll *pll)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2167
enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2187
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2191
enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
225
struct intel_dpll *pll)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
228
return DG1_DPLL_ENABLE(pll->info->id);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
230
(pll->info->id == DPLL_ID_EHL_DPLL4))
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
233
return ICL_DPLL_ENABLE(pll->info->id);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
238
struct intel_dpll *pll)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2387
const struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
240
const enum intel_dpll_id id = pll->info->id;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2456
struct intel_dpll *pll;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2461
pll = intel_get_dpll_by_id(display, id);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2464
crtc->base.base.id, crtc->base.name, pll->info->name);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2467
pll, &crtc_state->dpll_hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2469
crtc_state->intel_dpll = pll;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
250
struct intel_dpll *pll)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
252
if (pll->info->power_domain)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
253
pll->wakeref = intel_display_power_get(display, pll->info->power_domain);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
255
pll->info->funcs->enable(display, pll, &pll->state.hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
256
pll->on = true;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
260
struct intel_dpll *pll)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
262
pll->info->funcs->disable(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
263
pll->on = false;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
265
if (pll->info->power_domain)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
266
intel_display_power_put(display, pll->info->power_domain, pll->wakeref);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2782
const struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
279
struct intel_dpll *pll = crtc_state->intel_dpll;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
283
if (drm_WARN_ON(display->drm, !pll))
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2853
const struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
287
old_mask = pll->active_mask;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
289
if (drm_WARN_ON(display->drm, !(pll->state.pipe_mask & pipe_mask)) ||
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
290
drm_WARN_ON(display->drm, pll->active_mask & pipe_mask))
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
293
pll->active_mask |= pipe_mask;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
297
pll->info->name, pll->active_mask, pll->on,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
301
drm_WARN_ON(display->drm, !pll->on);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
302
assert_dpll_enabled(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
305
drm_WARN_ON(display->drm, pll->on);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
307
drm_dbg_kms(display->drm, "enabling %s\n", pll->info->name);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
309
_intel_enable_shared_dpll(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3226
const struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
325
struct intel_dpll *pll = crtc_state->intel_dpll;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3312
crtc_state->intel_dpll = port_dpll->pll;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
332
if (pll == NULL)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
336
if (drm_WARN(display->drm, !(pll->active_mask & pipe_mask),
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
337
"%s not used by [CRTC:%d:%s]\n", pll->info->name,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3415
port_dpll->pll = intel_find_dpll(state, crtc,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3418
if (!port_dpll->pll)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3422
port_dpll->pll, &port_dpll->hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
343
pll->info->name, pll->active_mask, pll->on,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
346
assert_dpll_enabled(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
347
drm_WARN_ON(display->drm, !pll->on);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3479
port_dpll->pll = intel_find_dpll(state, crtc,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3482
if (!port_dpll->pll)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3485
port_dpll->pll, &port_dpll->hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3489
port_dpll->pll = intel_find_dpll(state, crtc,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
349
pll->active_mask &= ~pipe_mask;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3492
if (!port_dpll->pll) {
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3497
port_dpll->pll, &port_dpll->hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
350
if (pll->active_mask)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3505
intel_unreference_dpll(state, crtc, port_dpll->pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3527
port_dpll->pll = intel_find_dpll(state, crtc,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
353
drm_dbg_kms(display->drm, "disabling %s\n", pll->info->name);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3530
if (!port_dpll->pll)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3534
port_dpll->pll, &port_dpll->hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
355
_intel_disable_shared_dpll(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3586
new_port_dpll->pll = NULL;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3588
if (!old_port_dpll->pll)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3591
intel_unreference_dpll(state, crtc, old_port_dpll->pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3596
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3600
const enum intel_dpll_id id = pll->info->id;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3606
intel_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
364
struct intel_dpll *pll;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3663
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3667
const enum intel_dpll_id id = pll->info->id;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3678
val = intel_de_read(display, intel_tc_pll_enable_reg(display, pll));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
368
for_each_dpll(display, pll, i) {
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
369
drm_WARN_ON(display->drm, dpll_mask & BIT(pll->info->id));
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
371
dpll_mask |= BIT(pll->info->id);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3735
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3740
const enum intel_dpll_id id = pll->info->id;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3796
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3799
intel_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3801
return icl_pll_get_hw_state(display, pll, dpll_hw_state, enable_reg);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3805
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3808
return icl_pll_get_hw_state(display, pll, dpll_hw_state, TBT_PLL_ENABLE);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3812
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3815
const enum intel_dpll_id id = pll->info->id;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3854
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3857
enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3897
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3900
enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
394
struct intel_dpll *pll;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
396
pll = intel_get_dpll_by_id(display, id);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3962
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
397
if (!pll)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3973
pll->info->id);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3977
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3984
drm_err(display->drm, "PLL %d not locked\n", pll->info->id);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3987
static void adlp_cmtg_clock_gating_wa(struct intel_display *display, struct intel_dpll *pll)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
3992
pll->info->id != DPLL_ID_ICL_DPLL0)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
401
if (dpll_state[pll->index].pipe_mask == 0) {
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4012
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4016
intel_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4018
icl_pll_power_enable(display, pll, enable_reg);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4020
icl_dpll_write(display, pll, hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4028
icl_pll_enable(display, pll, enable_reg);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
403
unused_pll = pll;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4030
adlp_cmtg_clock_gating_wa(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4036
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4041
icl_pll_power_enable(display, pll, TBT_PLL_ENABLE);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4043
icl_dpll_write(display, pll, hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4051
icl_pll_enable(display, pll, TBT_PLL_ENABLE);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4057
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4061
intel_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4063
icl_pll_power_enable(display, pll, enable_reg);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4066
dkl_pll_write(display, pll, hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4068
icl_mg_pll_write(display, pll, hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4076
icl_pll_enable(display, pll, enable_reg);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
408
&dpll_state[pll->index].hw_state,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4082
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4097
drm_err(display->drm, "PLL %d locked\n", pll->info->id);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4109
pll->info->id);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4113
struct intel_dpll *pll)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4115
intel_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4117
icl_pll_disable(display, pll, enable_reg);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4121
struct intel_dpll *pll)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4123
icl_pll_disable(display, pll, TBT_PLL_ENABLE);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4127
struct intel_dpll *pll)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4129
intel_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
413
pll->info->name,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4131
icl_pll_disable(display, pll, enable_reg);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
414
dpll_state[pll->index].pipe_mask,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
415
pll->active_mask);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
416
return pll;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4357
const struct intel_dpll *pll)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4365
if (mtl_id == pll->info->id)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4373
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4376
struct intel_encoder *encoder = get_intel_encoder(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4385
const struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4388
struct intel_encoder *encoder = get_intel_encoder(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4397
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4400
struct intel_encoder *encoder = get_intel_encoder(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4405
intel_mtl_pll_enable(encoder, pll, dpll_hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4409
struct intel_dpll *pll)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
441
const struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4411
struct intel_encoder *encoder = get_intel_encoder(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4427
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4433
struct intel_dpll *pll)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4438
const struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
451
crtc->base.base.id, crtc->base.name, pll->info->name);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
457
const struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4575
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4578
struct intel_encoder *encoder = get_intel_encoder(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4587
const struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4590
struct intel_encoder *encoder = get_intel_encoder(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4599
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4602
struct intel_encoder *encoder = get_intel_encoder(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4607
intel_xe3plpd_pll_enable(encoder, pll, dpll_hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4611
struct intel_dpll *pll)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4613
struct intel_encoder *encoder = get_intel_encoder(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
464
if (dpll_state[pll->index].pipe_mask == 0)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
465
dpll_state[pll->index].hw_state = *dpll_hw_state;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
467
intel_dpll_crtc_get(crtc, pll, &dpll_state[pll->index]);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
480
const struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
490
crtc->base.base.id, crtc->base.name, pll->info->name);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4933
const struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4936
if (drm_WARN_ON(display->drm, !pll->info->funcs->get_freq))
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4939
return pll->info->funcs->get_freq(display, pll, dpll_hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
495
const struct intel_dpll *pll)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4951
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4954
return pll->info->funcs->get_hw_state(display, pll, dpll_hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4958
struct intel_dpll *pll)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4962
pll->on = intel_dpll_get_hw_state(display, pll, &pll->state.hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4964
if (pll->on && pll->info->power_domain)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4965
pll->wakeref = intel_display_power_get(display, pll->info->power_domain);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4967
pll->state.pipe_mask = 0;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4972
if (crtc_state->hw.active && crtc_state->intel_dpll == pll)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4973
intel_dpll_crtc_get(crtc, pll, &pll->state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4975
pll->active_mask = pll->state.pipe_mask;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4979
pll->info->name, pll->state.pipe_mask, pll->on);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4990
struct intel_dpll *pll;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4993
for_each_dpll(display, pll, i)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4994
readout_dpll_hw_state(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
4998
struct intel_dpll *pll)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5000
if (!pll->on)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5003
adlp_cmtg_clock_gating_wa(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5005
if (pll->active_mask)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
501
intel_dpll_crtc_put(crtc, pll, &dpll_state[pll->index]);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5010
pll->info->name);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5012
_intel_disable_shared_dpll(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5017
struct intel_dpll *pll;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5022
for_each_dpll(display, pll, i)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5023
sanitize_dpll_state(display, pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5074
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5083
active = intel_dpll_get_hw_state(display, pll, &dpll_hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5085
if (!pll->info->always_on) {
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5086
INTEL_DISPLAY_STATE_WARN(display, !pll->on && pll->active_mask,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5088
pll->info->name);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5089
INTEL_DISPLAY_STATE_WARN(display, pll->on && !pll->active_mask,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5091
pll->info->name);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5092
INTEL_DISPLAY_STATE_WARN(display, pll->on != active,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5094
pll->info->name, pll->on, active);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5099
pll->active_mask & ~pll->state.pipe_mask,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5101
pll->info->name, pll->active_mask, pll->state.pipe_mask);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5109
INTEL_DISPLAY_STATE_WARN(display, !(pll->active_mask & pipe_mask),
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5111
pll->info->name, pipe_name(crtc->pipe), pll->active_mask);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5113
INTEL_DISPLAY_STATE_WARN(display, pll->active_mask & pipe_mask,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5115
pll->info->name, pipe_name(crtc->pipe), pll->active_mask);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5117
INTEL_DISPLAY_STATE_WARN(display, !(pll->state.pipe_mask & pipe_mask),
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5119
pll->info->name, pipe_mask, pll->state.pipe_mask);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5121
if (pll->on) {
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5125
pll_mismatch = !dpll_mgr->compare_hw_state(&pll->state.hw_state,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5128
pll_mismatch = memcmp(&pll->state.hw_state, &dpll_hw_state,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5134
pll->info->name)) {
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5137
drm_printf(&p, "PLL %s HW state:\n", pll->info->name);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5139
drm_printf(&p, "PLL %s SW state:\n", pll->info->name);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5140
intel_dpll_dump_hw_state(display, &p, &pll->state.hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5167
struct intel_dpll *pll = old_crtc_state->intel_dpll;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5169
INTEL_DISPLAY_STATE_WARN(display, pll->active_mask & pipe_mask,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5171
pll->info->name, pipe_name(crtc->pipe), pll->active_mask);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5176
pll->state.pipe_mask & pipe_mask,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5178
pll->info->name, pipe_name(crtc->pipe), pll->state.pipe_mask);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5185
struct intel_dpll *pll;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5188
for_each_dpll(display, pll, i)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
5189
verify_single_dpll_state(display, pll, NULL, NULL);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
535
struct intel_dpll *pll;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
541
for_each_dpll(display, pll, i)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
542
swap(pll->state, dpll_state[pll->index]);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
546
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
550
const enum intel_dpll_id id = pll->info->id;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
582
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
586
const enum intel_dpll_id id = pll->info->id;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
611
struct intel_dpll *pll)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
613
const enum intel_dpll_id id = pll->info->id;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
634
struct intel_dpll *pll;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
640
pll = intel_get_dpll_by_id(display, id);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
645
pll->info->name);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
647
pll = intel_find_dpll(state, crtc,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
653
if (!pll)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
658
pll, &crtc_state->dpll_hw_state);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
660
crtc_state->intel_dpll = pll;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
712
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
716
const enum intel_dpll_id id = pll->info->id;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
724
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
735
struct intel_dpll *pll)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
737
const enum intel_dpll_id id = pll->info->id;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
74
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
751
struct intel_dpll *pll)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
753
enum intel_dpll_id id = pll->info->id;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
767
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
771
const enum intel_dpll_id id = pll->info->id;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
789
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
83
struct intel_dpll *pll);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
91
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
99
const struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.h
246
u8 pll[20];
drivers/gpu/drm/i915/display/intel_dpll_mgr.h
410
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.h
423
const struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.h
431
const struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_dpll_mgr.h
434
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_lt_phy.c
1908
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_lt_phy.c
2221
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_lt_phy.c
2269
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_lt_phy.c
2272
intel_lt_phy_pll_enable(encoder, pll, dpll_hw_state);
drivers/gpu/drm/i915/display/intel_lt_phy.h
22
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_lt_phy.h
40
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_lt_phy.h
48
struct intel_dpll *pll,
drivers/gpu/drm/i915/display/intel_pch_display.c
499
struct intel_dpll *pll;
drivers/gpu/drm/i915/display/intel_pch_display.c
532
pll = crtc_state->intel_dpll;
drivers/gpu/drm/i915/display/intel_pch_display.c
534
pll_active = intel_dpll_get_hw_state(display, pll,
drivers/gpu/drm/i915/display/intel_pch_refclk.c
501
struct intel_dpll *pll;
drivers/gpu/drm/i915/display/intel_pch_refclk.c
537
for_each_dpll(display, pll, i) {
drivers/gpu/drm/i915/display/intel_pch_refclk.c
540
temp = intel_de_read(display, PCH_DPLL(pll->info->id));
drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c
337
pll_state->pll[0] = REG_FIELD_PREP(C10_PLL0_DIV5CLK_EN, pll_params.mpll_div5_en) |
drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c
341
pll_state->pll[2] = REG_FIELD_PREP(C10_PLL2_MULTIPLIERL_MASK, pll_params.multiplier);
drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c
342
pll_state->pll[3] = REG_FIELD_PREP(C10_PLL3_MULTIPLIERH_MASK, pll_params.multiplier >> 8);
drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c
343
pll_state->pll[8] = REG_FIELD_PREP(C10_PLL8_SSC_UP_SPREAD, pll_params.ssc_up_spread);
drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c
344
pll_state->pll[9] = REG_FIELD_PREP(C10_PLL9_FRACN_DENL_MASK, pll_params.fracn_den);
drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c
345
pll_state->pll[10] = REG_FIELD_PREP(C10_PLL10_FRACN_DENH_MASK, pll_params.fracn_den >> 8);
drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c
346
pll_state->pll[11] = REG_FIELD_PREP(C10_PLL11_FRACN_QUOT_L_MASK, pll_params.fracn_quot);
drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c
347
pll_state->pll[12] = REG_FIELD_PREP(C10_PLL12_FRACN_QUOT_H_MASK,
drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c
350
pll_state->pll[13] = REG_FIELD_PREP(C10_PLL13_FRACN_REM_L_MASK, pll_params.fracn_rem);
drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c
351
pll_state->pll[14] = REG_FIELD_PREP(C10_PLL14_FRACN_REM_H_MASK, pll_params.fracn_rem >> 8);
drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c
352
pll_state->pll[15] = REG_FIELD_PREP(C10_PLL15_TXCLKDIV_MASK, pll_params.tx_clk_div) |
drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c
354
pll_state->pll[16] = REG_FIELD_PREP(C10_PLL16_ANA_CPINT, pll_params.ana_cp_int) |
drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c
356
pll_state->pll[17] = REG_FIELD_PREP(C10_PLL17_ANA_CPINTGS_H_MASK, ana_cp_int_gs >> 1) |
drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c
358
pll_state->pll[18] =
drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c
362
pll_state->pll[19] = REG_FIELD_PREP(C10_PLL19_ANA_CPPROPGS_H_MASK, ana_cp_prop_gs >> 3) |
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
115
static void dsi_pll_calc_dec_frac(struct dsi_pll_10nm *pll, struct dsi_pll_config *config)
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
124
pll_freq = pll->vco_current_rate;
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
150
static void dsi_pll_calc_ssc(struct dsi_pll_10nm *pll, struct dsi_pll_config *config)
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
184
static void dsi_pll_ssc_commit(struct dsi_pll_10nm *pll, struct dsi_pll_config *config)
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
186
void __iomem *base = pll->phy->pll_base;
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
208
static void dsi_pll_config_hzindep_reg(struct dsi_pll_10nm *pll)
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
210
void __iomem *base = pll->phy->pll_base;
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
232
static void dsi_pll_commit(struct dsi_pll_10nm *pll, struct dsi_pll_config *config)
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
234
void __iomem *base = pll->phy->pll_base;
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
280
static int dsi_pll_10nm_lock_status(struct dsi_pll_10nm *pll)
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
282
struct device *dev = &pll->phy->pdev->dev;
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
288
rc = readl_poll_timeout_atomic(pll->phy->pll_base +
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
296
pll->phy->id, status);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
301
static void dsi_pll_disable_pll_bias(struct dsi_pll_10nm *pll)
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
303
u32 data = readl(pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
305
writel(0, pll->phy->pll_base + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
306
writel(data & ~BIT(5), pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
310
static void dsi_pll_enable_pll_bias(struct dsi_pll_10nm *pll)
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
312
u32 data = readl(pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
314
writel(data | BIT(5), pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
315
writel(0xc0, pll->phy->pll_base + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
319
static void dsi_pll_disable_global_clk(struct dsi_pll_10nm *pll)
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
323
data = readl(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
324
writel(data & ~BIT(5), pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
327
static void dsi_pll_enable_global_clk(struct dsi_pll_10nm *pll)
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
331
data = readl(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
332
writel(data | BIT(5), pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
381
static void dsi_pll_disable_sub(struct dsi_pll_10nm *pll)
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
383
writel(0, pll->phy->base + REG_DSI_10nm_PHY_CMN_RBUF_CTRL);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
384
dsi_pll_disable_pll_bias(pll);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
100
struct dsi_pll_14nm *pll;
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
167
static void pll_14nm_ssc_calc(struct dsi_pll_14nm *pll, struct dsi_pll_config *pconf)
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
206
static void pll_14nm_dec_frac_calc(struct dsi_pll_14nm *pll, struct dsi_pll_config *pconf)
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
252
static void pll_14nm_calc_vco_count(struct dsi_pll_14nm *pll, struct dsi_pll_config *pconf)
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
285
static void pll_db_commit_ssc(struct dsi_pll_14nm *pll, struct dsi_pll_config *pconf)
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
287
void __iomem *base = pll->phy->pll_base;
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
319
static void pll_db_commit_common(struct dsi_pll_14nm *pll,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
322
void __iomem *base = pll->phy->pll_base;
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
386
static void pll_db_commit_14nm(struct dsi_pll_14nm *pll,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
389
void __iomem *base = pll->phy->pll_base;
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
390
void __iomem *cmn_base = pll->phy->base;
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
393
DBG("DSI%d PLL", pll->phy->id);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
397
pll_db_commit_common(pll, pconf);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
399
pll_14nm_software_reset(pll);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
452
pll_db_commit_ssc(pll, pconf);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
608
struct dsi_pll_14nm *pll_14nm = postdiv->pll;
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
627
struct dsi_pll_14nm *pll_14nm = postdiv->pll;
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
638
struct dsi_pll_14nm *pll_14nm = postdiv->pll;
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
788
pll_postdiv->pll = pll_14nm;
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
113
static void dsi_pll_enable_pll_bias(struct dsi_pll_7nm *pll);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
114
static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
127
static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, struct dsi_pll_config *config)
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
136
pll_freq = pll->vco_current_rate;
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
144
if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_0) {
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
146
} else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_2)) {
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
167
} else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
176
} else if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
204
static void dsi_pll_calc_ssc(struct dsi_pll_7nm *pll, struct dsi_pll_config *config)
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
238
static void dsi_pll_ssc_commit(struct dsi_pll_7nm *pll, struct dsi_pll_config *config)
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
240
void __iomem *base = pll->phy->pll_base;
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
262
static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll)
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
264
void __iomem *base = pll->phy->pll_base;
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
267
if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_0))
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
268
if (pll->vco_current_rate >= 3100000000ULL)
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
271
if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
272
if (pll->vco_current_rate < 1520000000ULL)
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
274
else if (pll->vco_current_rate < 2990000000ULL)
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
278
if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) ||
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
279
(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3)) {
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
280
if (pll->vco_current_rate < 1520000000ULL)
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
282
else if (pll->vco_current_rate >= 2990000000ULL)
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
286
if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) ||
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
287
(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_2)) {
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
288
if (pll->vco_current_rate < 1557000000ULL)
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
316
writel(!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_0) ? 0x3f : 0x22,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
319
if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_0)) {
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
321
if (pll->slave)
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
322
writel(0x22, pll->slave->phy->pll_base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
326
static void dsi_pll_commit(struct dsi_pll_7nm *pll, struct dsi_pll_config *config)
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
328
void __iomem *base = pll->phy->pll_base;
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
341
writel(pll->phy->cphy_mode ? 0x00 : 0x10,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
378
static int dsi_pll_7nm_lock_status(struct dsi_pll_7nm *pll)
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
385
rc = readl_poll_timeout_atomic(pll->phy->pll_base +
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
393
pll->phy->id, status);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
398
static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll)
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
403
spin_lock_irqsave(&pll->pll_enable_lock, flags);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
404
--pll->pll_enable_cnt;
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
405
if (pll->pll_enable_cnt < 0) {
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
406
spin_unlock_irqrestore(&pll->pll_enable_lock, flags);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
407
DRM_DEV_ERROR_RATELIMITED(&pll->phy->pdev->dev,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
410
} else if (pll->pll_enable_cnt > 0) {
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
411
spin_unlock_irqrestore(&pll->pll_enable_lock, flags);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
415
data = readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
417
writel(0, pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
418
writel(data, pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
419
spin_unlock_irqrestore(&pll->pll_enable_lock, flags);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
423
static void dsi_pll_enable_pll_bias(struct dsi_pll_7nm *pll)
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
428
spin_lock_irqsave(&pll->pll_enable_lock, flags);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
429
pll->pll_enable_cnt++;
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
430
WARN_ON(pll->pll_enable_cnt == INT_MAX);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
432
data = readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
434
writel(data, pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
436
writel(0xc0, pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
437
spin_unlock_irqrestore(&pll->pll_enable_lock, flags);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
441
static void dsi_pll_cmn_clk_cfg0_write(struct dsi_pll_7nm *pll, u32 val)
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
445
spin_lock_irqsave(&pll->postdiv_lock, flags);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
446
writel(val, pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
447
spin_unlock_irqrestore(&pll->postdiv_lock, flags);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
450
static void dsi_pll_cmn_clk_cfg1_update(struct dsi_pll_7nm *pll, u32 mask,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
456
spin_lock_irqsave(&pll->pclk_mux_lock, flags);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
457
data = readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
461
writel(data, pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
462
spin_unlock_irqrestore(&pll->pclk_mux_lock, flags);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
465
static void dsi_pll_disable_global_clk(struct dsi_pll_7nm *pll)
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
467
dsi_pll_cmn_clk_cfg1_update(pll, DSI_7nm_PHY_CMN_CLK_CFG1_CLK_EN, 0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
470
static void dsi_pll_enable_global_clk(struct dsi_pll_7nm *pll)
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
474
writel(0x04, pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_3);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
475
dsi_pll_cmn_clk_cfg1_update(pll, cfg_1, cfg_1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
478
static void dsi_pll_phy_dig_reset(struct dsi_pll_7nm *pll)
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
485
writel(BIT(0), pll->phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
487
writel(0, pll->phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
539
static void dsi_pll_disable_sub(struct dsi_pll_7nm *pll)
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
541
writel(0, pll->phy->base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
542
dsi_pll_disable_pll_bias(pll);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
395
struct hdmi_pll_8996 *pll = hw_clk_to_pll(hw);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
396
struct hdmi_phy *phy = pll_get_phy(pll);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
414
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_BG_CTRL, 0x04);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
417
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL, 0x20);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
422
hdmi_tx_chan_write(pll, i,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
425
hdmi_tx_chan_write(pll, i,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
428
hdmi_tx_chan_write(pll, i,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
433
hdmi_tx_chan_write(pll, 0, REG_HDMI_PHY_QSERDES_TX_LX_LANE_MODE,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
435
hdmi_tx_chan_write(pll, 2, REG_HDMI_PHY_QSERDES_TX_LX_LANE_MODE,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
438
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1E);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
439
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x07);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
440
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SYSCLK_EN_SEL, 0x37);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
441
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SYS_CLK_CTRL, 0x02);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
442
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_CLK_ENABLE1, 0x0E);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
445
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SVS_MODE_CLK_SEL,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
448
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_BG_TRIM, 0x0F);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
449
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_PLL_IVCO, 0x0F);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
450
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_CTRL,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
453
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_BG_CTRL, 0x06);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
455
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_CLK_SELECT, 0x30);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
456
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_HSCLK_SEL,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
458
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_EN,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
461
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE0,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
463
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE0,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
465
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE0,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
467
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE0,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
469
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE0,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
471
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE0,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
473
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE0,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
476
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
478
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
481
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE0,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
483
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE0,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
485
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE0,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
488
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAP, 0x00);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
489
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_CORE_CLK_EN,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
491
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
493
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_CMN_CONFIG, 0x02);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
495
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_RESCODE_DIV_NUM, 0x15);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
499
hdmi_tx_chan_write(pll, i,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
502
hdmi_tx_chan_write(pll, i,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
505
hdmi_tx_chan_write(pll, i,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
508
hdmi_tx_chan_write(pll, i,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
511
hdmi_tx_chan_write(pll, i,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
514
hdmi_tx_chan_write(pll, i,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
517
hdmi_tx_chan_write(pll, i,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
520
hdmi_tx_chan_write(pll, i,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
523
hdmi_tx_chan_write(pll, i,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
564
static int hdmi_8996_pll_lock_status(struct hdmi_pll_8996 *pll)
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
574
status = hdmi_pll_read(pll,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
591
struct hdmi_pll_8996 *pll = hw_clk_to_pll(hw);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
592
struct hdmi_phy *phy = pll_get_phy(pll);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
601
ret = hdmi_8996_pll_lock_status(pll);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
606
hdmi_tx_chan_write(pll, i,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
611
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SSC_PER1, 0x0);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
612
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SSC_PER2, 0x0);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
613
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE1, 0x0);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
614
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE2, 0x0);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
615
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SSC_EN_CENTER, 0x2);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
641
struct hdmi_pll_8996 *pll = hw_clk_to_pll(hw);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
645
cmp1 = hdmi_pll_read(pll, REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE0);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
646
cmp2 = hdmi_pll_read(pll, REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE0);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
647
cmp3 = hdmi_pll_read(pll, REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE0);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
660
struct hdmi_pll_8996 *pll = hw_clk_to_pll(hw);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
661
struct hdmi_phy *phy = pll_get_phy(pll);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
669
struct hdmi_pll_8996 *pll = hw_clk_to_pll(hw);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
673
status = hdmi_pll_read(pll, REG_HDMI_PHY_QSERDES_COM_C_READY_STATUS);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
701
struct hdmi_pll_8996 *pll;
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
704
pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
705
if (!pll)
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
708
pll->pdev = pdev;
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
710
pll->mmio_qserdes_com = msm_ioremap(pdev, "hdmi_pll");
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
711
if (IS_ERR(pll->mmio_qserdes_com)) {
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
721
pll->mmio_qserdes_tx[i] = msm_ioremap(pdev, name);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
722
if (IS_ERR(pll->mmio_qserdes_tx[i])) {
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
727
pll->clk_hw.init = &pll_init;
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
729
ret = devm_clk_hw_register(dev, &pll->clk_hw);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
735
ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &pll->clk_hw);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
78
static inline struct hdmi_phy *pll_get_phy(struct hdmi_pll_8996 *pll)
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
80
return platform_get_drvdata(pll->pdev);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
83
static inline void hdmi_pll_write(struct hdmi_pll_8996 *pll, int offset,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
86
writel(data, pll->mmio_qserdes_com + offset);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
89
static inline u32 hdmi_pll_read(struct hdmi_pll_8996 *pll, int offset)
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
91
return readl(pll->mmio_qserdes_com + offset);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
94
static inline void hdmi_tx_chan_write(struct hdmi_pll_8996 *pll, int channel,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
97
writel(data, pll->mmio_qserdes_tx[channel] + offset);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
444
struct hdmi_pll_8998 *pll = hw_clk_to_pll(hw);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
445
struct hdmi_phy *phy = pll_get_phy(pll);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
461
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_RESETSM_CNTRL, 0x20);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
465
hdmi_tx_chan_write(pll, i,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
468
hdmi_tx_chan_write(pll, i,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
471
hdmi_tx_chan_write(pll, i,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
476
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_SYSCLK_BUF_ENABLE, 0x02);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
477
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x0B);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
478
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_SYSCLK_EN_SEL, 0x37);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
479
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_SYS_CLK_CTRL, 0x02);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
480
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_CLK_ENABLE1, 0x0E);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
483
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_SVS_MODE_CLK_SEL,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
486
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_PLL_IVCO, 0x07);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
487
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_VCO_TUNE_CTRL, 0x00);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
489
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_CLK_SEL, 0x30);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
490
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_HSCLK_SEL,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
492
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_LOCK_CMP_EN,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
495
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_PLL_CCTRL_MODE0,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
497
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_PLL_RCTRL_MODE0,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
499
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_CP_CTRL_MODE0,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
501
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_DEC_START_MODE0,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
503
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_DIV_FRAC_START1_MODE0,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
505
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_DIV_FRAC_START2_MODE0,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
507
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_DIV_FRAC_START3_MODE0,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
510
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
512
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
515
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_LOCK_CMP1_MODE0,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
517
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_LOCK_CMP2_MODE0,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
519
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_LOCK_CMP3_MODE0,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
522
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_VCO_TUNE_MAP, 0x00);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
523
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_CORE_CLK_EN,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
525
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_CORECLK_DIV_MODE0,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
530
hdmi_tx_chan_write(pll, i,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
533
hdmi_tx_chan_write(pll, i,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
536
hdmi_tx_chan_write(pll, i,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
539
hdmi_tx_chan_write(pll, i,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
542
hdmi_tx_chan_write(pll, i,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
550
hdmi_tx_chan_write(pll, i,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
561
pll->rate = rate;
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
586
static int hdmi_8998_pll_lock_status(struct hdmi_pll_8998 *pll)
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
594
status = hdmi_pll_read(pll,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
609
struct hdmi_pll_8998 *pll = hw_clk_to_pll(hw);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
610
struct hdmi_phy *phy = pll_get_phy(pll);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
619
ret = hdmi_8998_pll_lock_status(pll);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
624
hdmi_tx_chan_write(pll, i,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
658
struct hdmi_pll_8998 *pll = hw_clk_to_pll(hw);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
659
return pll->rate;
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
664
struct hdmi_pll_8998 *pll = hw_clk_to_pll(hw);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
665
struct hdmi_phy *phy = pll_get_phy(pll);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
673
struct hdmi_pll_8998 *pll = hw_clk_to_pll(hw);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
677
status = hdmi_pll_read(pll, REG_HDMI_8998_PHY_QSERDES_COM_C_READY_STATUS);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
705
struct hdmi_pll_8998 *pll;
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
708
pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
709
if (!pll)
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
712
pll->pdev = pdev;
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
714
pll->mmio_qserdes_com = msm_ioremap(pdev, "hdmi_pll");
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
715
if (IS_ERR(pll->mmio_qserdes_com)) {
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
725
pll->mmio_qserdes_tx[i] = msm_ioremap(pdev, name);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
726
if (IS_ERR(pll->mmio_qserdes_tx[i])) {
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
731
pll->clk_hw.init = &pll_init;
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
733
ret = devm_clk_hw_register(dev, &pll->clk_hw);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
739
ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &pll->clk_hw);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
77
static inline struct hdmi_phy *pll_get_phy(struct hdmi_pll_8998 *pll)
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
79
return platform_get_drvdata(pll->pdev);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
82
static inline void hdmi_pll_write(struct hdmi_pll_8998 *pll, int offset,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
85
writel(data, pll->mmio_qserdes_com + offset);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
88
static inline u32 hdmi_pll_read(struct hdmi_pll_8998 *pll, int offset)
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
90
return readl(pll->mmio_qserdes_com + offset);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
93
static inline void hdmi_tx_chan_write(struct hdmi_pll_8998 *pll, int channel,
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
96
writel(data, pll->mmio_qserdes_tx[channel] + offset);
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
237
static inline void pll_write(struct hdmi_pll_8960 *pll, u32 reg, u32 data)
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
239
writel(data, pll->mmio + reg);
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
242
static inline u32 pll_read(struct hdmi_pll_8960 *pll, u32 reg)
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
244
return readl(pll->mmio + reg);
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
247
static inline struct hdmi_phy *pll_get_phy(struct hdmi_pll_8960 *pll)
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
249
return platform_get_drvdata(pll->pdev);
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
254
struct hdmi_pll_8960 *pll = hw_clk_to_pll(hw);
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
255
struct hdmi_phy *phy = pll_get_phy(pll);
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
262
pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2, 0x8d);
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
263
pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0, 0x10);
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
264
pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1, 0x1a);
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
274
pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2, 0x0d);
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
298
val = pll_read(pll, REG_HDMI_8960_PHY_PLL_PWRDN_B);
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
301
pll_write(pll, REG_HDMI_8960_PHY_PLL_PWRDN_B, val);
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
307
val = pll_read(pll, REG_HDMI_8960_PHY_PLL_STATUS0);
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
321
pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2, 0x8d);
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
323
pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2, 0x0d);
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
339
struct hdmi_pll_8960 *pll = hw_clk_to_pll(hw);
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
340
struct hdmi_phy *phy = pll_get_phy(pll);
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
349
val = pll_read(pll, REG_HDMI_8960_PHY_PLL_PWRDN_B);
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
352
pll_write(pll, REG_HDMI_8960_PHY_PLL_PWRDN_B, val);
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
371
struct hdmi_pll_8960 *pll = hw_clk_to_pll(hw);
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
373
return pll->pixclk;
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
389
struct hdmi_pll_8960 *pll = hw_clk_to_pll(hw);
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
396
pll_write(pll, pll_rate->conf[i].reg, pll_rate->conf[i].val);
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
398
pll->pixclk = rate;
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
426
struct hdmi_pll_8960 *pll;
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
434
pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL);
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
435
if (!pll)
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
438
pll->mmio = msm_ioremap(pdev, "hdmi_pll");
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
439
if (IS_ERR(pll->mmio)) {
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
444
pll->pdev = pdev;
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
445
pll->clk_hw.init = &pll_init;
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
447
ret = devm_clk_hw_register(dev, &pll->clk_hw);
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
453
ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &pll->clk_hw);
drivers/gpu/drm/nouveau/dispnv04/hw.c
265
enum nvbios_pll_type pll = head ? PLL_VPLL1 : PLL_VPLL0;
drivers/gpu/drm/nouveau/dispnv04/hw.c
267
if (nvbios_pll_parse(bios, pll, &pll_lim))
drivers/gpu/drm/nouveau/dispnv04/hw.c
269
nouveau_hw_get_pllvals(dev, pll, &pv);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c
59
read_pll(struct gf100_clk *clk, u32 pll)
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c
62
u32 ctrl = nvkm_rd32(device, pll + 0x00);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c
63
u32 coef = nvkm_rd32(device, pll + 0x04);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c
72
switch (pll) {
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c
88
sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c
60
read_pll(struct gk104_clk *clk, u32 pll)
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c
63
u32 ctrl = nvkm_rd32(device, pll + 0x00);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c
64
u32 coef = nvkm_rd32(device, pll + 0x04);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c
74
switch (pll) {
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c
86
fN = nvkm_rd32(device, pll + 0x10) >> 16;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c
92
sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
103
struct gk20a_pll *pll)
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
198
pll->m = best_m;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
199
pll->n = best_n;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
200
pll->pl = best_pl;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
202
target_freq = gk20a_pllg_calc_rate(clk, pll);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
206
target_freq / KHZ, pll->m, pll->n, pll->pl,
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
207
clk->pl_to_div(pll->pl));
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
216
struct gk20a_pll pll;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
220
gk20a_pllg_read_mnp(clk, &pll);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
222
if (n == pll.n)
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
231
pll.n = n;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
233
gk20a_pllg_write_mnp(clk, &pll);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
297
gk20a_pllg_program_mnp(struct gk20a_clk *clk, const struct gk20a_pll *pll)
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
317
gk20a_pllg_write_mnp(clk, pll);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
336
gk20a_pllg_program_mnp_slide(struct gk20a_clk *clk, const struct gk20a_pll *pll)
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
345
if (pll->m == cur_pll.m && pll->pl == cur_pll.pl)
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
346
return gk20a_pllg_slide(clk, pll->n);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
356
cur_pll = *pll;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
363
return gk20a_pllg_slide(clk, pll->n);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
466
struct gk20a_pll pll;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
472
gk20a_pllg_read_mnp(clk, &pll);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
473
return gk20a_pllg_calc_rate(clk, &pll) / GK20A_CLK_GPC_MDIV;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
486
GK20A_CLK_GPC_MDIV, &clk->pll);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
495
ret = gk20a_pllg_program_mnp_slide(clk, &clk->pll);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
497
ret = gk20a_pllg_program_mnp(clk, &clk->pll);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
551
struct gk20a_pll pll;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
554
gk20a_pllg_read_mnp(clk, &pll);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
555
n_lo = gk20a_pllg_n_lo(clk, &pll);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
66
gk20a_pllg_read_mnp(struct gk20a_clk *clk, struct gk20a_pll *pll)
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
72
pll->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
73
pll->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
74
pll->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
78
gk20a_pllg_write_mnp(struct gk20a_clk *clk, const struct gk20a_pll *pll)
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
83
val = (pll->m & MASK(GPCPLL_COEFF_M_WIDTH)) << GPCPLL_COEFF_M_SHIFT;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
84
val |= (pll->n & MASK(GPCPLL_COEFF_N_WIDTH)) << GPCPLL_COEFF_N_SHIFT;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
85
val |= (pll->pl & MASK(GPCPLL_COEFF_P_WIDTH)) << GPCPLL_COEFF_P_SHIFT;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
90
gk20a_pllg_calc_rate(struct gk20a_clk *clk, struct gk20a_pll *pll)
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
95
rate = clk->parent_rate * pll->n;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
96
divider = pll->m * clk->pl_to_div(pll->pl);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h
119
struct gk20a_pll pll;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h
144
gk20a_pllg_n_lo(struct gk20a_clk *clk, struct gk20a_pll *pll)
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h
146
return DIV_ROUND_UP(pll->m * clk->params->min_vco,
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
161
gm20b_pllg_read_mnp(struct gm20b_clk *clk, struct gm20b_pll *pll)
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
167
gk20a_pllg_read_mnp(&clk->base, &pll->base);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
169
pll->sdm_din = (val >> GPCPLL_CFG2_SDM_DIN_SHIFT) &
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
174
gm20b_pllg_write_mnp(struct gm20b_clk *clk, const struct gm20b_pll *pll)
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
179
pll->sdm_din << GPCPLL_CFG2_SDM_DIN_SHIFT);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
180
gk20a_pllg_write_mnp(&clk->base, &pll->base);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
271
struct gm20b_pll pll;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
279
gm20b_pllg_read_mnp(clk, &pll);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
281
if (n_int == pll.base.n && sdm_din == pll.sdm_din)
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
293
pll.base.n = n_int;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
295
gk20a_pllg_write_mnp(&clk->base, &pll.base);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
361
gm20b_pllg_program_mnp(struct gm20b_clk *clk, const struct gk20a_pll *pll)
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
371
gm20b_dvfs_calc_ndiv(clk, pll->n, &n_int, &sdm_din);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
374
cur_pll.base.m == pll->m;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
391
u32 new = pll->pl;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
411
cur_pll.base = *pll;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
434
gm20b_pllg_program_mnp_slide(struct gm20b_clk *clk, const struct gk20a_pll *pll)
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
443
if (pll->m == cur_pll.m && pll->pl == cur_pll.pl)
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
444
return gm20b_pllg_slide(clk, pll->n);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
454
cur_pll = *pll;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
461
return gm20b_pllg_slide(clk, pll->n);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
489
gm20b_dvfs_calc_safe_pll(struct gm20b_clk *clk, struct gk20a_pll *pll)
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
491
u32 rate = gk20a_pllg_calc_rate(&clk->base, pll) / KHZ;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
502
nmin = DIV_ROUND_UP(pll->m * clk->base.params->min_vco, parent_rate);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
503
nsafe = pll->m * rate / (clk->base.parent_rate);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
506
pll->pl = DIV_ROUND_UP(nmin * parent_rate, pll->m * rate);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
510
pll->n = nsafe;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
608
pll_safe = clk->base.pll;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
633
clk->base.pll = clk->new_pll;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
635
return gm20b_pllg_program_mnp_slide(clk, &clk->base.pll);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
728
struct gk20a_pll pll;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
731
gk20a_pllg_read_mnp(&clk->base, &pll);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
732
n_lo = gk20a_pllg_n_lo(&clk->base, &pll);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
108
read_pll(struct gt215_clk *clk, int idx, u32 pll)
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
111
u32 ctrl = nvkm_rd32(device, pll + 0);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
117
u32 coef = nvkm_rd32(device, pll + 4);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
125
if ((pll & 0x00ff00) == 0x00e800)
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
235
gt215_pll_info(struct nvkm_clk *base, int idx, u32 pll, u32 khz,
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
244
info->pll = 0;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
250
if (!pll || (diff >= -2000 && diff < 3000)) {
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
255
ret = nvbios_pll_parse(subdev->device->bios, pll, &limits);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
265
info->pll = (P << 16) | (N << 8) | M;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
275
int idx, u32 pll, int dom)
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
277
int ret = gt215_pll_info(&clk->base, idx, pll, cstate->domain[dom],
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
363
prog_pll(struct gt215_clk *clk, int idx, u32 pll, int dom)
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
369
const u32 ctrl = pll + 0;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
370
const u32 coef = pll + 4;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
373
if (info->pll) {
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
383
nvkm_wr32(device, coef, info->pll);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
474
if (core->pll) {
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
498
if (core->pll)
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.h
8
u32 pll;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
166
struct nvbios_pll pll;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
169
ret = nvbios_pll_parse(subdev->device->bios, reg, &pll);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
173
pll.vco2.max_freq = 0;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
174
pll.refclk = nvkm_clk_read(&clk->base, nv_clk_src_href);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
175
if (!pll.refclk)
drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
178
return nv04_pll_calc(subdev, &pll, clock, N, M, NULL, NULL, P);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c
128
struct nvbios_pll pll;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c
131
ret = nvbios_pll_parse(subdev->device->bios, reg, &pll);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c
135
if (khz < pll.vco1.max_freq)
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c
136
pll.vco2.max_freq = 0;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c
138
ret = nv04_pll_calc(subdev, &pll, khz, N1, M1, N2, M2, log2P);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
329
struct nvbios_pll pll;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
332
ret = nvbios_pll_parse(subdev->device->bios, reg, &pll);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
336
pll.vco2.max_freq = 0;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
337
pll.refclk = read_pll_ref(clk, reg);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
338
if (!pll.refclk)
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
341
return nv04_pll_calc(subdev, &pll, idx, N, M, NULL, NULL, P);
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c
150
uint32_t pll = (oldpll & 0xfff80000) | pv->log2P << 16 | pv->NM1;
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c
154
if (oldpll == pll)
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c
178
nvkm_wr32(device, reg, pll);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
458
ram_wr32(fuc, 0x004004, mclk->pll);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
602
pll2pll = (!(ctrl & 0x00000008)) && mclk.pll;
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
615
if (mclk.pll && !pll2pll) {
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
694
if (mclk.pll) {
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
737
if (mclk.pll) {
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
870
if (mclk.pll) {
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c
39
struct nvbios_pll pll;
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c
43
ret = nvbios_pll_parse(bios, 0x04, &pll);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c
49
ret = nv04_pll_calc(subdev, &pll, freq, &N1, &M1, &N2, &M2, &log2P);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c
54
ram->ctrl |= min(pll.bias_p + log2P, (int)pll.max_p) << 20;
drivers/gpu/drm/omapdrm/dss/dispc.c
3173
struct dss_pll *pll;
drivers/gpu/drm/omapdrm/dss/dispc.c
3176
pll = dss_pll_find_by_src(dispc->dss, src);
drivers/gpu/drm/omapdrm/dss/dispc.c
3179
r = pll->cinfo.clkout[clkout_idx];
drivers/gpu/drm/omapdrm/dss/dispc.c
3201
struct dss_pll *pll;
drivers/gpu/drm/omapdrm/dss/dispc.c
3204
pll = dss_pll_find_by_src(dispc->dss, src);
drivers/gpu/drm/omapdrm/dss/dispc.c
3207
r = pll->cinfo.clkout[clkout_idx];
drivers/gpu/drm/omapdrm/dss/dpi.c
204
return dss_pll_hsdiv_calc_a(ctx->dpi->pll, clkdco,
drivers/gpu/drm/omapdrm/dss/dpi.c
229
clkin = clk_get_rate(dpi->pll->clkin);
drivers/gpu/drm/omapdrm/dss/dpi.c
231
if (dpi->pll->hw->type == DSS_PLL_TYPE_A) {
drivers/gpu/drm/omapdrm/dss/dpi.c
240
return dss_pll_calc_a(ctx->dpi->pll, clkin,
drivers/gpu/drm/omapdrm/dss/dpi.c
244
dss_pll_calc_b(dpi->pll, clkin, pck, &ctx->pll_cinfo);
drivers/gpu/drm/omapdrm/dss/dpi.c
299
r = dss_pll_set_config(dpi->pll, &ctx.pll_cinfo);
drivers/gpu/drm/omapdrm/dss/dpi.c
334
if (dpi->pll)
drivers/gpu/drm/omapdrm/dss/dpi.c
362
if (dpi->pll) {
drivers/gpu/drm/omapdrm/dss/dpi.c
38
struct dss_pll *pll;
drivers/gpu/drm/omapdrm/dss/dpi.c
382
static int dpi_verify_pll(struct dss_pll *pll)
drivers/gpu/drm/omapdrm/dss/dpi.c
388
r = dss_pll_enable(pll);
drivers/gpu/drm/omapdrm/dss/dpi.c
392
dss_pll_disable(pll);
drivers/gpu/drm/omapdrm/dss/dpi.c
399
struct dss_pll *pll;
drivers/gpu/drm/omapdrm/dss/dpi.c
401
if (dpi->pll)
drivers/gpu/drm/omapdrm/dss/dpi.c
406
pll = dss_pll_find_by_src(dpi->dss, dpi->clk_src);
drivers/gpu/drm/omapdrm/dss/dpi.c
407
if (!pll)
drivers/gpu/drm/omapdrm/dss/dpi.c
410
if (dpi_verify_pll(pll)) {
drivers/gpu/drm/omapdrm/dss/dpi.c
415
dpi->pll = pll;
drivers/gpu/drm/omapdrm/dss/dpi.c
504
if (dpi->pll) {
drivers/gpu/drm/omapdrm/dss/dpi.c
505
r = dss_pll_enable(dpi->pll);
drivers/gpu/drm/omapdrm/dss/dpi.c
526
if (dpi->pll)
drivers/gpu/drm/omapdrm/dss/dpi.c
527
dss_pll_disable(dpi->pll);
drivers/gpu/drm/omapdrm/dss/dpi.c
542
if (dpi->pll) {
drivers/gpu/drm/omapdrm/dss/dpi.c
545
dss_pll_disable(dpi->pll);
drivers/gpu/drm/omapdrm/dss/dsi.c
1332
unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4;
drivers/gpu/drm/omapdrm/dss/dsi.c
1339
unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4;
drivers/gpu/drm/omapdrm/dss/dsi.c
3390
r = dss_pll_set_config(&dsi->pll, &cinfo);
drivers/gpu/drm/omapdrm/dss/dsi.c
3433
r = dss_pll_enable(&dsi->pll);
drivers/gpu/drm/omapdrm/dss/dsi.c
3482
dss_pll_disable(&dsi->pll);
drivers/gpu/drm/omapdrm/dss/dsi.c
3498
dss_pll_disable(&dsi->pll);
drivers/gpu/drm/omapdrm/dss/dsi.c
3706
return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, ctx->req_pck_min,
drivers/gpu/drm/omapdrm/dss/dsi.c
3720
clkin = clk_get_rate(dsi->pll.clkin);
drivers/gpu/drm/omapdrm/dss/dsi.c
3736
ctx->pll = &dsi->pll;
drivers/gpu/drm/omapdrm/dss/dsi.c
3745
return dss_pll_calc_a(ctx->pll, clkin,
drivers/gpu/drm/omapdrm/dss/dsi.c
4006
return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, ctx->req_pck_min,
drivers/gpu/drm/omapdrm/dss/dsi.c
4023
clkin = clk_get_rate(dsi->pll.clkin);
drivers/gpu/drm/omapdrm/dss/dsi.c
4027
ctx->pll = &dsi->pll;
drivers/gpu/drm/omapdrm/dss/dsi.c
4048
return dss_pll_calc_a(ctx->pll, clkin,
drivers/gpu/drm/omapdrm/dss/dsi.c
4530
struct dss_pll *pll = &dsi->pll;
drivers/gpu/drm/omapdrm/dss/dsi.c
4540
pll->name = dsi->module_id == 0 ? "dsi0" : "dsi1";
drivers/gpu/drm/omapdrm/dss/dsi.c
4541
pll->id = dsi->module_id == 0 ? DSS_PLL_DSI1 : DSS_PLL_DSI2;
drivers/gpu/drm/omapdrm/dss/dsi.c
4542
pll->clkin = clk;
drivers/gpu/drm/omapdrm/dss/dsi.c
4543
pll->base = dsi->pll_base;
drivers/gpu/drm/omapdrm/dss/dsi.c
4544
pll->hw = dsi->data->pll_hw;
drivers/gpu/drm/omapdrm/dss/dsi.c
4545
pll->ops = &dsi_pll_ops;
drivers/gpu/drm/omapdrm/dss/dsi.c
4547
r = dss_pll_register(dss, pll);
drivers/gpu/drm/omapdrm/dss/dsi.c
4607
dss_pll_unregister(&dsi->pll);
drivers/gpu/drm/omapdrm/dss/dsi.c
777
return dsi->pll.cinfo.clkout[HSDIV_DISPC];
drivers/gpu/drm/omapdrm/dss/dsi.c
782
return dsi->pll.cinfo.clkout[HSDIV_DSI];
drivers/gpu/drm/omapdrm/dss/dsi.c
787
return dsi->pll.cinfo.clkdco / 16;
drivers/gpu/drm/omapdrm/dss/dsi.c
913
static int dsi_pll_enable(struct dss_pll *pll)
drivers/gpu/drm/omapdrm/dss/dsi.c
915
struct dsi_data *dsi = container_of(pll, struct dsi_data, pll);
drivers/gpu/drm/omapdrm/dss/dsi.c
963
static void dsi_pll_disable(struct dss_pll *pll)
drivers/gpu/drm/omapdrm/dss/dsi.c
965
struct dsi_data *dsi = container_of(pll, struct dsi_data, pll);
drivers/gpu/drm/omapdrm/dss/dsi.c
980
struct dss_pll_clock_info *cinfo = &dsi->pll.cinfo;
drivers/gpu/drm/omapdrm/dss/dsi.c
983
struct dss_pll *pll = &dsi->pll;
drivers/gpu/drm/omapdrm/dss/dsi.c
993
seq_printf(s, "dsi pll clkin\t%lu\n", clk_get_rate(pll->clkin));
drivers/gpu/drm/omapdrm/dss/dsi.h
298
struct dss_pll *pll;
drivers/gpu/drm/omapdrm/dss/dsi.h
364
struct dss_pll pll;
drivers/gpu/drm/omapdrm/dss/dss.c
147
void dss_ctrl_pll_enable(struct dss_pll *pll, bool enable)
drivers/gpu/drm/omapdrm/dss/dss.c
152
if (!pll->dss->syscon_pll_ctrl)
drivers/gpu/drm/omapdrm/dss/dss.c
157
switch (pll->id) {
drivers/gpu/drm/omapdrm/dss/dss.c
168
DSSERR("illegal DSS PLL ID %d\n", pll->id);
drivers/gpu/drm/omapdrm/dss/dss.c
172
regmap_update_bits(pll->dss->syscon_pll_ctrl,
drivers/gpu/drm/omapdrm/dss/dss.c
173
pll->dss->syscon_pll_ctrl_offset,
drivers/gpu/drm/omapdrm/dss/dss.h
144
int (*enable)(struct dss_pll *pll);
drivers/gpu/drm/omapdrm/dss/dss.h
145
void (*disable)(struct dss_pll *pll);
drivers/gpu/drm/omapdrm/dss/dss.h
146
int (*set_config)(struct dss_pll *pll,
drivers/gpu/drm/omapdrm/dss/dss.h
317
void dss_video_pll_uninit(struct dss_pll *pll);
drivers/gpu/drm/omapdrm/dss/dss.h
319
void dss_ctrl_pll_enable(struct dss_pll *pll, bool enable);
drivers/gpu/drm/omapdrm/dss/dss.h
506
int dss_pll_register(struct dss_device *dss, struct dss_pll *pll);
drivers/gpu/drm/omapdrm/dss/dss.h
507
void dss_pll_unregister(struct dss_pll *pll);
drivers/gpu/drm/omapdrm/dss/dss.h
512
int dss_pll_enable(struct dss_pll *pll);
drivers/gpu/drm/omapdrm/dss/dss.h
513
void dss_pll_disable(struct dss_pll *pll);
drivers/gpu/drm/omapdrm/dss/dss.h
514
int dss_pll_set_config(struct dss_pll *pll,
drivers/gpu/drm/omapdrm/dss/dss.h
517
bool dss_pll_hsdiv_calc_a(const struct dss_pll *pll, unsigned long clkdco,
drivers/gpu/drm/omapdrm/dss/dss.h
520
bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin,
drivers/gpu/drm/omapdrm/dss/dss.h
524
bool dss_pll_calc_b(const struct dss_pll *pll, unsigned long clkin,
drivers/gpu/drm/omapdrm/dss/dss.h
527
int dss_pll_write_config_type_a(struct dss_pll *pll,
drivers/gpu/drm/omapdrm/dss/dss.h
529
int dss_pll_write_config_type_b(struct dss_pll *pll,
drivers/gpu/drm/omapdrm/dss/dss.h
531
int dss_pll_wait_reset_done(struct dss_pll *pll);
drivers/gpu/drm/omapdrm/dss/hdmi.h
234
struct dss_pll pll;
drivers/gpu/drm/omapdrm/dss/hdmi.h
318
void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s);
drivers/gpu/drm/omapdrm/dss/hdmi.h
320
struct hdmi_pll_data *pll, struct hdmi_wp_data *wp);
drivers/gpu/drm/omapdrm/dss/hdmi.h
357
struct hdmi_pll_data pll;
drivers/gpu/drm/omapdrm/dss/hdmi4.c
174
dss_pll_calc_b(&hdmi->pll.pll, clk_get_rate(hdmi->pll.pll.clkin),
drivers/gpu/drm/omapdrm/dss/hdmi4.c
177
r = dss_pll_enable(&hdmi->pll.pll);
drivers/gpu/drm/omapdrm/dss/hdmi4.c
183
r = dss_pll_set_config(&hdmi->pll.pll, &hdmi_cinfo);
drivers/gpu/drm/omapdrm/dss/hdmi4.c
222
dss_pll_disable(&hdmi->pll.pll);
drivers/gpu/drm/omapdrm/dss/hdmi4.c
238
dss_pll_disable(&hdmi->pll.pll);
drivers/gpu/drm/omapdrm/dss/hdmi4.c
255
hdmi_pll_dump(&hdmi->pll, s);
drivers/gpu/drm/omapdrm/dss/hdmi4.c
655
r = hdmi_pll_init(dss, hdmi->pdev, &hdmi->pll, &hdmi->wp);
drivers/gpu/drm/omapdrm/dss/hdmi4.c
679
hdmi_pll_uninit(&hdmi->pll);
drivers/gpu/drm/omapdrm/dss/hdmi4.c
695
hdmi_pll_uninit(&hdmi->pll);
drivers/gpu/drm/omapdrm/dss/hdmi5.c
168
dss_pll_calc_b(&hdmi->pll.pll, clk_get_rate(hdmi->pll.pll.clkin),
drivers/gpu/drm/omapdrm/dss/hdmi5.c
176
r = dss_pll_enable(&hdmi->pll.pll);
drivers/gpu/drm/omapdrm/dss/hdmi5.c
182
r = dss_pll_set_config(&hdmi->pll.pll, &hdmi_cinfo);
drivers/gpu/drm/omapdrm/dss/hdmi5.c
221
dss_pll_disable(&hdmi->pll.pll);
drivers/gpu/drm/omapdrm/dss/hdmi5.c
237
dss_pll_disable(&hdmi->pll.pll);
drivers/gpu/drm/omapdrm/dss/hdmi5.c
254
hdmi_pll_dump(&hdmi->pll, s);
drivers/gpu/drm/omapdrm/dss/hdmi5.c
631
r = hdmi_pll_init(dss, hdmi->pdev, &hdmi->pll, &hdmi->wp);
drivers/gpu/drm/omapdrm/dss/hdmi5.c
647
hdmi_pll_uninit(&hdmi->pll);
drivers/gpu/drm/omapdrm/dss/hdmi5.c
660
hdmi_pll_uninit(&hdmi->pll);
drivers/gpu/drm/omapdrm/dss/hdmi_pll.c
132
struct dss_pll *pll = &hpll->pll;
drivers/gpu/drm/omapdrm/dss/hdmi_pll.c
142
pll->name = "hdmi";
drivers/gpu/drm/omapdrm/dss/hdmi_pll.c
143
pll->id = DSS_PLL_HDMI;
drivers/gpu/drm/omapdrm/dss/hdmi_pll.c
144
pll->base = hpll->base;
drivers/gpu/drm/omapdrm/dss/hdmi_pll.c
145
pll->clkin = clk;
drivers/gpu/drm/omapdrm/dss/hdmi_pll.c
148
pll->hw = &dss_omap4_hdmi_pll_hw;
drivers/gpu/drm/omapdrm/dss/hdmi_pll.c
150
pll->hw = &dss_omap5_hdmi_pll_hw;
drivers/gpu/drm/omapdrm/dss/hdmi_pll.c
152
pll->ops = &hdmi_pll_ops;
drivers/gpu/drm/omapdrm/dss/hdmi_pll.c
154
r = dss_pll_register(dss, pll);
drivers/gpu/drm/omapdrm/dss/hdmi_pll.c
162
struct hdmi_pll_data *pll, struct hdmi_wp_data *wp)
drivers/gpu/drm/omapdrm/dss/hdmi_pll.c
166
pll->pdev = pdev;
drivers/gpu/drm/omapdrm/dss/hdmi_pll.c
167
pll->wp = wp;
drivers/gpu/drm/omapdrm/dss/hdmi_pll.c
169
pll->base = devm_platform_ioremap_resource_byname(pdev, "pll");
drivers/gpu/drm/omapdrm/dss/hdmi_pll.c
170
if (IS_ERR(pll->base))
drivers/gpu/drm/omapdrm/dss/hdmi_pll.c
171
return PTR_ERR(pll->base);
drivers/gpu/drm/omapdrm/dss/hdmi_pll.c
173
r = hdmi_init_pll_data(dss, pdev, pll);
drivers/gpu/drm/omapdrm/dss/hdmi_pll.c
184
struct dss_pll *pll = &hpll->pll;
drivers/gpu/drm/omapdrm/dss/hdmi_pll.c
186
dss_pll_unregister(pll);
drivers/gpu/drm/omapdrm/dss/hdmi_pll.c
23
void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s)
drivers/gpu/drm/omapdrm/dss/hdmi_pll.c
26
hdmi_read_reg(pll->base, r))
drivers/gpu/drm/omapdrm/dss/hdmi_pll.c
41
struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll);
drivers/gpu/drm/omapdrm/dss/hdmi_pll.c
42
struct hdmi_wp_data *wp = pll->wp;
drivers/gpu/drm/omapdrm/dss/hdmi_pll.c
45
r = pm_runtime_get_sync(&pll->pdev->dev);
drivers/gpu/drm/omapdrm/dss/hdmi_pll.c
59
struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll);
drivers/gpu/drm/omapdrm/dss/hdmi_pll.c
60
struct hdmi_wp_data *wp = pll->wp;
drivers/gpu/drm/omapdrm/dss/hdmi_pll.c
67
r = pm_runtime_put_sync(&pll->pdev->dev);
drivers/gpu/drm/omapdrm/dss/pll.c
123
int dss_pll_enable(struct dss_pll *pll)
drivers/gpu/drm/omapdrm/dss/pll.c
127
r = clk_prepare_enable(pll->clkin);
drivers/gpu/drm/omapdrm/dss/pll.c
131
if (pll->regulator) {
drivers/gpu/drm/omapdrm/dss/pll.c
132
r = regulator_enable(pll->regulator);
drivers/gpu/drm/omapdrm/dss/pll.c
137
r = pll->ops->enable(pll);
drivers/gpu/drm/omapdrm/dss/pll.c
144
if (pll->regulator)
drivers/gpu/drm/omapdrm/dss/pll.c
145
regulator_disable(pll->regulator);
drivers/gpu/drm/omapdrm/dss/pll.c
147
clk_disable_unprepare(pll->clkin);
drivers/gpu/drm/omapdrm/dss/pll.c
151
void dss_pll_disable(struct dss_pll *pll)
drivers/gpu/drm/omapdrm/dss/pll.c
153
pll->ops->disable(pll);
drivers/gpu/drm/omapdrm/dss/pll.c
155
if (pll->regulator)
drivers/gpu/drm/omapdrm/dss/pll.c
156
regulator_disable(pll->regulator);
drivers/gpu/drm/omapdrm/dss/pll.c
158
clk_disable_unprepare(pll->clkin);
drivers/gpu/drm/omapdrm/dss/pll.c
160
memset(&pll->cinfo, 0, sizeof(pll->cinfo));
drivers/gpu/drm/omapdrm/dss/pll.c
163
int dss_pll_set_config(struct dss_pll *pll, const struct dss_pll_clock_info *cinfo)
drivers/gpu/drm/omapdrm/dss/pll.c
167
r = pll->ops->set_config(pll, cinfo);
drivers/gpu/drm/omapdrm/dss/pll.c
171
pll->cinfo = *cinfo;
drivers/gpu/drm/omapdrm/dss/pll.c
176
bool dss_pll_hsdiv_calc_a(const struct dss_pll *pll, unsigned long clkdco,
drivers/gpu/drm/omapdrm/dss/pll.c
180
const struct dss_pll_hw *hw = pll->hw;
drivers/gpu/drm/omapdrm/dss/pll.c
205
bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin,
drivers/gpu/drm/omapdrm/dss/pll.c
209
const struct dss_pll_hw *hw = pll->hw;
drivers/gpu/drm/omapdrm/dss/pll.c
272
bool dss_pll_calc_b(const struct dss_pll *pll, unsigned long clkin,
drivers/gpu/drm/omapdrm/dss/pll.c
279
const struct dss_pll_hw *hw = pll->hw;
drivers/gpu/drm/omapdrm/dss/pll.c
28
int dss_pll_register(struct dss_device *dss, struct dss_pll *pll)
drivers/gpu/drm/omapdrm/dss/pll.c
34
dss->plls[i] = pll;
drivers/gpu/drm/omapdrm/dss/pll.c
35
pll->dss = dss;
drivers/gpu/drm/omapdrm/dss/pll.c
356
int dss_pll_wait_reset_done(struct dss_pll *pll)
drivers/gpu/drm/omapdrm/dss/pll.c
358
void __iomem *base = pll->base;
drivers/gpu/drm/omapdrm/dss/pll.c
366
static int dss_wait_hsdiv_ack(struct dss_pll *pll, u32 hsdiv_ack_mask)
drivers/gpu/drm/omapdrm/dss/pll.c
371
u32 v = readl_relaxed(pll->base + PLL_STATUS);
drivers/gpu/drm/omapdrm/dss/pll.c
396
int dss_pll_write_config_type_a(struct dss_pll *pll,
drivers/gpu/drm/omapdrm/dss/pll.c
399
const struct dss_pll_hw *hw = pll->hw;
drivers/gpu/drm/omapdrm/dss/pll.c
400
void __iomem *base = pll->base;
drivers/gpu/drm/omapdrm/dss/pll.c
43
void dss_pll_unregister(struct dss_pll *pll)
drivers/gpu/drm/omapdrm/dss/pll.c
45
struct dss_device *dss = pll->dss;
drivers/gpu/drm/omapdrm/dss/pll.c
49
if (dss->plls[i] == pll) {
drivers/gpu/drm/omapdrm/dss/pll.c
51
pll->dss = NULL;
drivers/gpu/drm/omapdrm/dss/pll.c
510
r = dss_wait_hsdiv_ack(pll,
drivers/gpu/drm/omapdrm/dss/pll.c
524
int dss_pll_write_config_type_b(struct dss_pll *pll,
drivers/gpu/drm/omapdrm/dss/pll.c
527
const struct dss_pll_hw *hw = pll->hw;
drivers/gpu/drm/omapdrm/dss/pll.c
528
void __iomem *base = pll->base;
drivers/gpu/drm/omapdrm/dss/pll.c
72
struct dss_pll *pll;
drivers/gpu/drm/omapdrm/dss/pll.c
85
pll = dss_pll_find(dss, "dsi0");
drivers/gpu/drm/omapdrm/dss/pll.c
86
if (!pll)
drivers/gpu/drm/omapdrm/dss/pll.c
87
pll = dss_pll_find(dss, "video0");
drivers/gpu/drm/omapdrm/dss/pll.c
88
return pll;
drivers/gpu/drm/omapdrm/dss/pll.c
93
pll = dss_pll_find(dss, "dsi1");
drivers/gpu/drm/omapdrm/dss/pll.c
94
if (!pll)
drivers/gpu/drm/omapdrm/dss/pll.c
95
pll = dss_pll_find(dss, "video1");
drivers/gpu/drm/omapdrm/dss/pll.c
96
return pll;
drivers/gpu/drm/omapdrm/dss/video-pll.c
143
struct dss_pll *pll;
drivers/gpu/drm/omapdrm/dss/video-pll.c
173
pll = &vpll->pll;
drivers/gpu/drm/omapdrm/dss/video-pll.c
175
pll->name = id == 0 ? "video0" : "video1";
drivers/gpu/drm/omapdrm/dss/video-pll.c
176
pll->id = id == 0 ? DSS_PLL_VIDEO1 : DSS_PLL_VIDEO2;
drivers/gpu/drm/omapdrm/dss/video-pll.c
177
pll->clkin = clk;
drivers/gpu/drm/omapdrm/dss/video-pll.c
178
pll->regulator = regulator;
drivers/gpu/drm/omapdrm/dss/video-pll.c
179
pll->base = pll_base;
drivers/gpu/drm/omapdrm/dss/video-pll.c
18
struct dss_pll pll;
drivers/gpu/drm/omapdrm/dss/video-pll.c
180
pll->hw = &dss_dra7_video_pll_hw;
drivers/gpu/drm/omapdrm/dss/video-pll.c
181
pll->ops = &dss_pll_ops;
drivers/gpu/drm/omapdrm/dss/video-pll.c
183
r = dss_pll_register(dss, pll);
drivers/gpu/drm/omapdrm/dss/video-pll.c
187
return pll;
drivers/gpu/drm/omapdrm/dss/video-pll.c
190
void dss_video_pll_uninit(struct dss_pll *pll)
drivers/gpu/drm/omapdrm/dss/video-pll.c
192
dss_pll_unregister(pll);
drivers/gpu/drm/omapdrm/dss/video-pll.c
54
static int dss_video_pll_enable(struct dss_pll *pll)
drivers/gpu/drm/omapdrm/dss/video-pll.c
56
struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll);
drivers/gpu/drm/omapdrm/dss/video-pll.c
59
r = dss_runtime_get(pll->dss);
drivers/gpu/drm/omapdrm/dss/video-pll.c
63
dss_ctrl_pll_enable(pll, true);
drivers/gpu/drm/omapdrm/dss/video-pll.c
67
r = dss_pll_wait_reset_done(pll);
drivers/gpu/drm/omapdrm/dss/video-pll.c
77
dss_ctrl_pll_enable(pll, false);
drivers/gpu/drm/omapdrm/dss/video-pll.c
78
dss_runtime_put(pll->dss);
drivers/gpu/drm/omapdrm/dss/video-pll.c
83
static void dss_video_pll_disable(struct dss_pll *pll)
drivers/gpu/drm/omapdrm/dss/video-pll.c
85
struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll);
drivers/gpu/drm/omapdrm/dss/video-pll.c
91
dss_ctrl_pll_enable(pll, false);
drivers/gpu/drm/omapdrm/dss/video-pll.c
93
dss_runtime_put(pll->dss);
drivers/gpu/drm/radeon/atombios_crtc.c
1063
struct radeon_pll *pll;
drivers/gpu/drm/radeon/atombios_crtc.c
1074
pll = &rdev->clock.p1pll;
drivers/gpu/drm/radeon/atombios_crtc.c
1077
pll = &rdev->clock.p2pll;
drivers/gpu/drm/radeon/atombios_crtc.c
1082
pll = &rdev->clock.dcpll;
drivers/gpu/drm/radeon/atombios_crtc.c
1087
pll->flags = radeon_crtc->pll_flags;
drivers/gpu/drm/radeon/atombios_crtc.c
1088
pll->reference_div = radeon_crtc->pll_reference_div;
drivers/gpu/drm/radeon/atombios_crtc.c
1089
pll->post_div = radeon_crtc->pll_post_div;
drivers/gpu/drm/radeon/atombios_crtc.c
1093
radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
drivers/gpu/drm/radeon/atombios_crtc.c
1096
radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock,
drivers/gpu/drm/radeon/atombios_crtc.c
1099
radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
drivers/gpu/drm/radeon/atombios_crtc.c
1122
(125 * 25 * pll->reference_freq / 100);
drivers/gpu/drm/radeon/atombios_crtc.c
1125
(125 * 25 * pll->reference_freq / 100);
drivers/gpu/drm/radeon/atombios_crtc.c
1835
int pll;
drivers/gpu/drm/radeon/atombios_crtc.c
1844
pll = radeon_get_shared_dp_ppll(crtc);
drivers/gpu/drm/radeon/atombios_crtc.c
1845
if (pll != ATOM_PPLL_INVALID)
drivers/gpu/drm/radeon/atombios_crtc.c
1846
return pll;
drivers/gpu/drm/radeon/atombios_crtc.c
1850
pll = radeon_get_shared_nondp_ppll(crtc);
drivers/gpu/drm/radeon/atombios_crtc.c
1851
if (pll != ATOM_PPLL_INVALID)
drivers/gpu/drm/radeon/atombios_crtc.c
1852
return pll;
drivers/gpu/drm/radeon/atombios_crtc.c
1892
pll = radeon_get_shared_dp_ppll(crtc);
drivers/gpu/drm/radeon/atombios_crtc.c
1893
if (pll != ATOM_PPLL_INVALID)
drivers/gpu/drm/radeon/atombios_crtc.c
1894
return pll;
drivers/gpu/drm/radeon/atombios_crtc.c
1898
pll = radeon_get_shared_nondp_ppll(crtc);
drivers/gpu/drm/radeon/atombios_crtc.c
1899
if (pll != ATOM_PPLL_INVALID)
drivers/gpu/drm/radeon/atombios_crtc.c
1900
return pll;
drivers/gpu/drm/radeon/atombios_crtc.c
1947
pll = radeon_get_shared_dp_ppll(crtc);
drivers/gpu/drm/radeon/atombios_crtc.c
1948
if (pll != ATOM_PPLL_INVALID)
drivers/gpu/drm/radeon/atombios_crtc.c
1949
return pll;
drivers/gpu/drm/radeon/atombios_crtc.c
1953
pll = radeon_get_shared_nondp_ppll(crtc);
drivers/gpu/drm/radeon/atombios_crtc.c
1954
if (pll != ATOM_PPLL_INVALID)
drivers/gpu/drm/radeon/atombios_crtc.c
1955
return pll;
drivers/gpu/drm/radeon/radeon_display.c
1000
pll->flags & RADEON_PLL_USE_REF_DIV)
drivers/gpu/drm/radeon/radeon_display.c
1001
ref_div_max = pll->reference_div;
drivers/gpu/drm/radeon/radeon_display.c
1002
else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
drivers/gpu/drm/radeon/radeon_display.c
1004
ref_div_max = min(pll->max_ref_div, 7u);
drivers/gpu/drm/radeon/radeon_display.c
1006
ref_div_max = pll->max_ref_div;
drivers/gpu/drm/radeon/radeon_display.c
1009
if (pll->flags & RADEON_PLL_USE_POST_DIV) {
drivers/gpu/drm/radeon/radeon_display.c
1010
post_div_min = pll->post_div;
drivers/gpu/drm/radeon/radeon_display.c
1011
post_div_max = pll->post_div;
drivers/gpu/drm/radeon/radeon_display.c
1015
if (pll->flags & RADEON_PLL_IS_LCD) {
drivers/gpu/drm/radeon/radeon_display.c
1016
vco_min = pll->lcd_pll_out_min;
drivers/gpu/drm/radeon/radeon_display.c
1017
vco_max = pll->lcd_pll_out_max;
drivers/gpu/drm/radeon/radeon_display.c
1019
vco_min = pll->pll_out_min;
drivers/gpu/drm/radeon/radeon_display.c
1020
vco_max = pll->pll_out_max;
drivers/gpu/drm/radeon/radeon_display.c
1023
if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
drivers/gpu/drm/radeon/radeon_display.c
1031
if (post_div_min < pll->min_post_div)
drivers/gpu/drm/radeon/radeon_display.c
1032
post_div_min = pll->min_post_div;
drivers/gpu/drm/radeon/radeon_display.c
1037
if (post_div_max > pll->max_post_div)
drivers/gpu/drm/radeon/radeon_display.c
1038
post_div_max = pll->max_post_div;
drivers/gpu/drm/radeon/radeon_display.c
1043
den = pll->reference_freq;
drivers/gpu/drm/radeon/radeon_display.c
1049
if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
drivers/gpu/drm/radeon/radeon_display.c
1059
diff = abs(target_clock - (pll->reference_freq * fb_div) /
drivers/gpu/drm/radeon/radeon_display.c
1063
!(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
drivers/gpu/drm/radeon/radeon_display.c
1080
if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
drivers/gpu/drm/radeon/radeon_display.c
1090
if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
drivers/gpu/drm/radeon/radeon_display.c
1098
*dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
drivers/gpu/drm/radeon/radeon_display.c
1099
(pll->reference_freq * *frac_fb_div_p)) /
drivers/gpu/drm/radeon/radeon_display.c
1118
void radeon_compute_pll_legacy(struct radeon_pll *pll,
drivers/gpu/drm/radeon/radeon_display.c
1126
uint32_t min_ref_div = pll->min_ref_div;
drivers/gpu/drm/radeon/radeon_display.c
1127
uint32_t max_ref_div = pll->max_ref_div;
drivers/gpu/drm/radeon/radeon_display.c
1128
uint32_t min_post_div = pll->min_post_div;
drivers/gpu/drm/radeon/radeon_display.c
1129
uint32_t max_post_div = pll->max_post_div;
drivers/gpu/drm/radeon/radeon_display.c
1132
uint32_t best_vco = pll->best_vco;
drivers/gpu/drm/radeon/radeon_display.c
1143
DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
drivers/gpu/drm/radeon/radeon_display.c
1146
if (pll->flags & RADEON_PLL_IS_LCD) {
drivers/gpu/drm/radeon/radeon_display.c
1147
pll_out_min = pll->lcd_pll_out_min;
drivers/gpu/drm/radeon/radeon_display.c
1148
pll_out_max = pll->lcd_pll_out_max;
drivers/gpu/drm/radeon/radeon_display.c
1150
pll_out_min = pll->pll_out_min;
drivers/gpu/drm/radeon/radeon_display.c
1151
pll_out_max = pll->pll_out_max;
drivers/gpu/drm/radeon/radeon_display.c
1157
if (pll->flags & RADEON_PLL_USE_REF_DIV)
drivers/gpu/drm/radeon/radeon_display.c
1158
min_ref_div = max_ref_div = pll->reference_div;
drivers/gpu/drm/radeon/radeon_display.c
1162
uint32_t pll_in = pll->reference_freq / mid;
drivers/gpu/drm/radeon/radeon_display.c
1163
if (pll_in < pll->pll_in_min)
drivers/gpu/drm/radeon/radeon_display.c
1165
else if (pll_in > pll->pll_in_max)
drivers/gpu/drm/radeon/radeon_display.c
1172
if (pll->flags & RADEON_PLL_USE_POST_DIV)
drivers/gpu/drm/radeon/radeon_display.c
1173
min_post_div = max_post_div = pll->post_div;
drivers/gpu/drm/radeon/radeon_display.c
1175
if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
drivers/gpu/drm/radeon/radeon_display.c
1176
min_fractional_feed_div = pll->min_frac_feedback_div;
drivers/gpu/drm/radeon/radeon_display.c
1177
max_fractional_feed_div = pll->max_frac_feedback_div;
drivers/gpu/drm/radeon/radeon_display.c
1183
if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
drivers/gpu/drm/radeon/radeon_display.c
1187
if (pll->flags & RADEON_PLL_LEGACY) {
drivers/gpu/drm/radeon/radeon_display.c
1201
uint32_t pll_in = pll->reference_freq / ref_div;
drivers/gpu/drm/radeon/radeon_display.c
1202
uint32_t min_feed_div = pll->min_feedback_div;
drivers/gpu/drm/radeon/radeon_display.c
1203
uint32_t max_feed_div = pll->max_feedback_div + 1;
drivers/gpu/drm/radeon/radeon_display.c
1205
if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
drivers/gpu/drm/radeon/radeon_display.c
1217
tmp = (uint64_t)pll->reference_freq * feedback_div;
drivers/gpu/drm/radeon/radeon_display.c
1230
tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
drivers/gpu/drm/radeon/radeon_display.c
1231
tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
drivers/gpu/drm/radeon/radeon_display.c
1234
if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
drivers/gpu/drm/radeon/radeon_display.c
1263
} else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
drivers/gpu/drm/radeon/radeon_display.c
1264
((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
drivers/gpu/drm/radeon/radeon_display.c
1265
((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
drivers/gpu/drm/radeon/radeon_display.c
1266
((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
drivers/gpu/drm/radeon/radeon_display.c
1267
((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
drivers/gpu/drm/radeon/radeon_display.c
1268
((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
drivers/gpu/drm/radeon/radeon_display.c
967
void radeon_compute_pll_avivo(struct radeon_pll *pll,
drivers/gpu/drm/radeon/radeon_display.c
975
unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
drivers/gpu/drm/radeon/radeon_display.c
985
fb_div_min = pll->min_feedback_div;
drivers/gpu/drm/radeon/radeon_display.c
986
fb_div_max = pll->max_feedback_div;
drivers/gpu/drm/radeon/radeon_display.c
988
if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
drivers/gpu/drm/radeon/radeon_display.c
994
if (pll->flags & RADEON_PLL_USE_REF_DIV)
drivers/gpu/drm/radeon/radeon_display.c
995
ref_div_min = pll->reference_div;
drivers/gpu/drm/radeon/radeon_display.c
997
ref_div_min = pll->min_ref_div;
drivers/gpu/drm/radeon/radeon_display.c
999
if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
drivers/gpu/drm/radeon/radeon_legacy_crtc.c
741
struct radeon_pll *pll;
drivers/gpu/drm/radeon/radeon_legacy_crtc.c
764
pll = &rdev->clock.p2pll;
drivers/gpu/drm/radeon/radeon_legacy_crtc.c
766
pll = &rdev->clock.p1pll;
drivers/gpu/drm/radeon/radeon_legacy_crtc.c
768
pll->flags = RADEON_PLL_LEGACY;
drivers/gpu/drm/radeon/radeon_legacy_crtc.c
771
pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
drivers/gpu/drm/radeon/radeon_legacy_crtc.c
773
pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
drivers/gpu/drm/radeon/radeon_legacy_crtc.c
785
pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
drivers/gpu/drm/radeon/radeon_legacy_crtc.c
800
pll->flags |= RADEON_PLL_USE_REF_DIV;
drivers/gpu/drm/radeon/radeon_legacy_crtc.c
808
radeon_compute_pll_legacy(pll, mode->clock,
drivers/gpu/drm/radeon/radeon_legacy_crtc.c
839
pll_gain = radeon_compute_pll_gain(pll->reference_freq,
drivers/gpu/drm/radeon/radeon_legacy_tv.c
244
struct radeon_pll *pll;
drivers/gpu/drm/radeon/radeon_legacy_tv.c
248
pll = &rdev->clock.p2pll;
drivers/gpu/drm/radeon/radeon_legacy_tv.c
250
pll = &rdev->clock.p1pll;
drivers/gpu/drm/radeon/radeon_legacy_tv.c
253
*pll_ref_freq = pll->reference_freq;
drivers/gpu/drm/radeon/radeon_legacy_tv.c
258
if (pll->reference_freq == 2700)
drivers/gpu/drm/radeon/radeon_legacy_tv.c
263
if (pll->reference_freq == 2700)
drivers/gpu/drm/radeon/radeon_mode.h
774
extern void radeon_compute_pll_legacy(struct radeon_pll *pll,
drivers/gpu/drm/radeon/radeon_mode.h
782
extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c
142
unsigned long target, struct pll_info *pll,
drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c
245
if (diff < pll->diff) {
drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c
246
pll->diff = diff;
drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c
247
pll->pll_m = m;
drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c
248
pll->pll_n = n;
drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c
249
pll->pll_e = e;
drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c
250
pll->div = div;
drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c
251
pll->clksel = clksel;
drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c
261
output = fin * pll->pll_n / pll->pll_m / (1 << pll->pll_e)
drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c
262
/ div7 / pll->div;
drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c
269
pll->pll_m, pll->pll_n, pll->pll_e, pll->div);
drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c
275
struct pll_info pll = { .diff = (unsigned long)-1 };
drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c
278
rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[0], freq, &pll,
drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c
280
rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[1], freq, &pll,
drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c
282
rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.extal, freq, &pll,
drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c
285
lvdpllcr = LVDPLLCR_PLLON | pll.clksel | LVDPLLCR_CLKOUT
drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c
286
| LVDPLLCR_PLLN(pll.pll_n - 1) | LVDPLLCR_PLLM(pll.pll_m - 1);
drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c
288
if (pll.pll_e > 0)
drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c
290
| LVDPLLCR_PLLE(pll.pll_e - 1);
drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c
297
if (pll.div > 1)
drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c
303
LVDDIV_DIVRESET | LVDDIV_DIV(pll.div - 1));
drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c
1248
dsi->clocks.pll = rcar_mipi_dsi_get_clock(dsi, "pll", true);
drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c
1249
if (IS_ERR(dsi->clocks.pll))
drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c
1250
return PTR_ERR(dsi->clocks.pll);
drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c
1256
if (!dsi->clocks.pll && !dsi->clocks.dsi) {
drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c
556
rcar_mipi_dsi_parameters_calc(dsi, dsi->clocks.pll,
drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c
70
struct clk *pll;
drivers/gpu/drm/sprd/megacores_pll.c
111
struct dphy_pll *pll = &ctx->pll;
drivers/gpu/drm/sprd/megacores_pll.c
114
pll->freq = dsi->slave->hs_rate;
drivers/gpu/drm/sprd/megacores_pll.c
117
ret = dphy_calc_pll_param(pll);
drivers/gpu/drm/sprd/megacores_pll.c
122
dphy_set_pll_reg(pll, regmap);
drivers/gpu/drm/sprd/megacores_pll.c
217
struct dphy_pll *pll = &ctx->pll;
drivers/gpu/drm/sprd/megacores_pll.c
226
t_ui = 1000 * scale / (pll->freq / 1000);
drivers/gpu/drm/sprd/megacores_pll.c
30
static int dphy_calc_pll_param(struct dphy_pll *pll)
drivers/gpu/drm/sprd/megacores_pll.c
38
pll->potential_fvco = pll->freq / khz;
drivers/gpu/drm/sprd/megacores_pll.c
39
pll->ref_clk = PHY_REF_CLK / khz;
drivers/gpu/drm/sprd/megacores_pll.c
42
if (pll->potential_fvco >= VCO_BAND_LOW &&
drivers/gpu/drm/sprd/megacores_pll.c
43
pll->potential_fvco <= VCO_BAND_HIGH) {
drivers/gpu/drm/sprd/megacores_pll.c
44
pll->fvco = pll->potential_fvco;
drivers/gpu/drm/sprd/megacores_pll.c
45
pll->out_sel = BIT(i);
drivers/gpu/drm/sprd/megacores_pll.c
48
pll->potential_fvco <<= 1;
drivers/gpu/drm/sprd/megacores_pll.c
50
if (pll->fvco == 0)
drivers/gpu/drm/sprd/megacores_pll.c
53
if (pll->fvco >= VCO_BAND_LOW && pll->fvco <= VCO_BAND_MID) {
drivers/gpu/drm/sprd/megacores_pll.c
55
pll->vco_band = 0x0;
drivers/gpu/drm/sprd/megacores_pll.c
57
pll->lpf_sel = 1;
drivers/gpu/drm/sprd/megacores_pll.c
58
} else if (pll->fvco > VCO_BAND_MID && pll->fvco <= VCO_BAND_HIGH) {
drivers/gpu/drm/sprd/megacores_pll.c
59
pll->vco_band = 0x1;
drivers/gpu/drm/sprd/megacores_pll.c
60
pll->lpf_sel = 0;
drivers/gpu/drm/sprd/megacores_pll.c
65
pll->nint = pll->fvco / pll->ref_clk;
drivers/gpu/drm/sprd/megacores_pll.c
66
tmp = pll->fvco * factor * mhz;
drivers/gpu/drm/sprd/megacores_pll.c
67
do_div(tmp, pll->ref_clk);
drivers/gpu/drm/sprd/megacores_pll.c
68
tmp = tmp - pll->nint * factor * mhz;
drivers/gpu/drm/sprd/megacores_pll.c
71
pll->kint = (u32)tmp;
drivers/gpu/drm/sprd/megacores_pll.c
72
pll->refin = 3; /* pre-divider bypass */
drivers/gpu/drm/sprd/megacores_pll.c
73
pll->sdm_en = true; /* use fraction N PLL */
drivers/gpu/drm/sprd/megacores_pll.c
74
pll->fdk_s = 0x1; /* fraction */
drivers/gpu/drm/sprd/megacores_pll.c
75
pll->cp_s = 0x0;
drivers/gpu/drm/sprd/megacores_pll.c
76
pll->det_delay = 0x1;
drivers/gpu/drm/sprd/megacores_pll.c
81
static void dphy_set_pll_reg(struct dphy_pll *pll, struct regmap *regmap)
drivers/gpu/drm/sprd/megacores_pll.c
91
reg_val[0] = 1 | (1 << 1) | (pll->lpf_sel << 2);
drivers/gpu/drm/sprd/megacores_pll.c
92
reg_val[1] = pll->div | (1 << 3) | (pll->cp_s << 5) | (pll->fdk_s << 7);
drivers/gpu/drm/sprd/megacores_pll.c
93
reg_val[2] = pll->nint;
drivers/gpu/drm/sprd/megacores_pll.c
94
reg_val[3] = pll->vco_band | (pll->sdm_en << 1) | (pll->refin << 2);
drivers/gpu/drm/sprd/megacores_pll.c
95
reg_val[4] = pll->kint >> 12;
drivers/gpu/drm/sprd/megacores_pll.c
96
reg_val[5] = pll->kint >> 4;
drivers/gpu/drm/sprd/megacores_pll.c
97
reg_val[6] = pll->out_sel | ((pll->kint << 4) & 0xf);
drivers/gpu/drm/sprd/megacores_pll.c
99
reg_val[8] = pll->det_delay;
drivers/gpu/drm/sprd/sprd_dsi.h
89
struct dphy_pll pll;
drivers/gpu/drm/tegra/hdmi.c
1612
err = regulator_enable(hdmi->pll);
drivers/gpu/drm/tegra/hdmi.c
1635
regulator_disable(hdmi->pll);
drivers/gpu/drm/tegra/hdmi.c
1653
regulator_disable(hdmi->pll);
drivers/gpu/drm/tegra/hdmi.c
1844
hdmi->pll = devm_regulator_get(&pdev->dev, "pll");
drivers/gpu/drm/tegra/hdmi.c
1845
err = PTR_ERR_OR_ZERO(hdmi->pll);
drivers/gpu/drm/tegra/hdmi.c
70
struct regulator *pll;
drivers/media/dvb-frontends/dib0090.c
2236
const struct dib0090_pll *pll = state->current_pll_table_index;
drivers/media/dvb-frontends/dib0090.c
2350
pll = dib0090_pll_table;
drivers/media/dvb-frontends/dib0090.c
2352
pll = dib0090_p1g_pll_table;
drivers/media/dvb-frontends/dib0090.c
2357
while (state->rf_request > pll->max_freq)
drivers/media/dvb-frontends/dib0090.c
2358
pll++;
drivers/media/dvb-frontends/dib0090.c
2361
state->current_pll_table_index = pll;
drivers/media/dvb-frontends/dib0090.c
2365
VCOF_kHz = (pll->hfdiv * state->rf_request) * 2;
drivers/media/dvb-frontends/dib0090.c
2371
FBDiv = (VCOF_kHz / pll->topresc / FREF);
drivers/media/dvb-frontends/dib0090.c
2372
Rest = (VCOF_kHz / pll->topresc) - FBDiv * FREF;
drivers/media/dvb-frontends/dib0090.c
2391
if (pll->vco_band)
drivers/media/dvb-frontends/dib0090.c
2396
if (pll->vco_band)
drivers/media/dvb-frontends/dib0090.c
2414
lo5 |= (pll->hfdiv_code << 11) | (pll->vco_band << 7); /* bit 15 is the split to the slave, we do not do it here */
drivers/media/dvb-frontends/dib0090.c
2464
dprintk("HFDIV code: %d\n", (u32) pll->hfdiv_code);
drivers/media/dvb-frontends/dib0090.c
2465
dprintk("VCO = %d\n", (u32) pll->vco_band);
drivers/media/dvb-frontends/dib0090.c
2466
dprintk("VCOF in kHz: %d ((%d*%d) << 1))\n", (u32) ((pll->hfdiv * state->rf_request) * 2), (u32) pll->hfdiv, (u32) state->rf_request);
drivers/media/dvb-frontends/dib8000.c
1097
if (state->cfg.pll->ifreq == 0)
drivers/media/dvb-frontends/dib8000.c
2196
if (state->cfg.pll->ifreq == 0)
drivers/media/dvb-frontends/dib8000.c
2519
u32 value, internal = state->cfg.pll->internal;
drivers/media/dvb-frontends/dib8000.c
2700
u32 dds = state->cfg.pll->ifreq & 0x1ffffff;
drivers/media/dvb-frontends/dib8000.c
2701
u8 invert = !!(state->cfg.pll->ifreq & (1 << 25));
drivers/media/dvb-frontends/dib8000.c
2719
unit_khz_dds_val = 67108864 / state->cfg.pll->internal;
drivers/media/dvb-frontends/dib8000.c
2733
if (abs_offset_khz <= (state->cfg.pll->internal / ratio)) {
drivers/media/dvb-frontends/dib8000.c
2761
if (state->cfg.pll->ifreq == 0) { /* low if tuner */
drivers/media/dvb-frontends/dib8000.c
4478
state->timf_default = cfg->pll->timf;
drivers/media/dvb-frontends/dib8000.c
695
const struct dibx000_bandwidth_config *pll = state->cfg.pll;
drivers/media/dvb-frontends/dib8000.c
700
(pll->pll_prediv << 8) | (pll->pll_ratio << 0));
drivers/media/dvb-frontends/dib8000.c
702
clk_cfg1 = (1 << 10) | (0 << 9) | (pll->IO_CLK_en_core << 8) |
drivers/media/dvb-frontends/dib8000.c
703
(pll->bypclk_div << 5) | (pll->enable_refdiv << 4) |
drivers/media/dvb-frontends/dib8000.c
704
(1 << 3) | (pll->pll_range << 1) |
drivers/media/dvb-frontends/dib8000.c
705
(pll->pll_reset << 0);
drivers/media/dvb-frontends/dib8000.c
708
clk_cfg1 = (clk_cfg1 & 0xfff7) | (pll->pll_bypass << 3);
drivers/media/dvb-frontends/dib8000.c
714
if (state->cfg.pll->ADClkSrc == 0)
drivers/media/dvb-frontends/dib8000.c
717
(pll->modulo << 8) |
drivers/media/dvb-frontends/dib8000.c
718
(pll->ADClkSrc << 7) | (0 << 1));
drivers/media/dvb-frontends/dib8000.c
722
(pll->modulo << 8) |
drivers/media/dvb-frontends/dib8000.c
723
(pll->ADClkSrc << 7) | (0 << 1));
drivers/media/dvb-frontends/dib8000.c
726
(3 << 10) | (pll->modulo << 8) |
drivers/media/dvb-frontends/dib8000.c
727
(pll->ADClkSrc << 7) | (0 << 1));
drivers/media/dvb-frontends/dib8000.c
729
dib8000_write_word(state, 1856, (!pll->pll_reset<<13) |
drivers/media/dvb-frontends/dib8000.c
730
(pll->pll_range<<12) | (pll->pll_ratio<<6) |
drivers/media/dvb-frontends/dib8000.c
731
(pll->pll_prediv));
drivers/media/dvb-frontends/dib8000.c
734
dib8000_write_word(state, 1857, reg|(!pll->pll_bypass<<15));
drivers/media/dvb-frontends/dib8000.c
739
dib8000_write_word(state, 904, (pll->modulo << 8));
drivers/media/dvb-frontends/dib8000.c
742
dib8000_reset_pll_common(state, pll);
drivers/media/dvb-frontends/dib8000.c
746
struct dibx000_bandwidth_config *pll, u32 bw, u8 ratio)
drivers/media/dvb-frontends/dib8000.c
750
u8 loopdiv, prediv, oldprediv = state->cfg.pll->pll_prediv ;
drivers/media/dvb-frontends/dib8000.c
757
if ((pll == NULL) || (pll->pll_prediv == prediv &&
drivers/media/dvb-frontends/dib8000.c
758
pll->pll_ratio == loopdiv))
drivers/media/dvb-frontends/dib8000.c
761
dprintk("Updating pll (prediv: old = %d new = %d ; loopdiv : old = %d new = %d)\n", prediv, pll->pll_prediv, loopdiv, pll->pll_ratio);
drivers/media/dvb-frontends/dib8000.c
769
((pll->pll_ratio & 0x3f) << 6) |
drivers/media/dvb-frontends/dib8000.c
770
(pll->pll_prediv & 0x3f));
drivers/media/dvb-frontends/dib8000.c
776
internal = 1000 * (xtal/pll->pll_prediv) * pll->pll_ratio;
drivers/media/dvb-frontends/dib8000.c
796
dprintk("PLL: Bandwidth Change %d MHz -> %d MHz (prediv: %d->%d)\n", state->current_demod_bw / 1000, bw / 1000, oldprediv, state->cfg.pll->pll_prediv);
drivers/media/dvb-frontends/dib8000.c
798
if (state->cfg.pll->pll_prediv != oldprediv) {
drivers/media/dvb-frontends/dib8000.c
802
dprintk("PLL: New Setting for %d MHz Bandwidth (prediv: %d, ratio: %d)\n", bw/1000, state->cfg.pll->pll_prediv, state->cfg.pll->pll_ratio);
drivers/media/dvb-frontends/dib8000.c
807
ratio = state->cfg.pll->pll_ratio;
drivers/media/dvb-frontends/dib8000.c
814
dprintk("PLL: Update ratio (prediv: %d, ratio: %d)\n", state->cfg.pll->pll_prediv, ratio);
drivers/media/dvb-frontends/dib8000.c
815
dib8000_write_word(state, 901, (state->cfg.pll->pll_prediv << 8) | (ratio << 0)); /* only the PLL ratio is updated. */
drivers/media/dvb-frontends/dib8000.h
15
struct dibx000_bandwidth_config *pll;
drivers/media/dvb-frontends/dib8000.h
46
struct dibx000_bandwidth_config *pll, u32 bw, u8 ratio);
drivers/media/dvb-frontends/mb86a20s.c
1744
u64 pll;
drivers/media/dvb-frontends/mb86a20s.c
1791
pll = (((u64)1) << 34) * state->if_freq;
drivers/media/dvb-frontends/mb86a20s.c
1792
do_div(pll, 63 * fclk);
drivers/media/dvb-frontends/mb86a20s.c
1793
pll = (1 << 25) - pll;
drivers/media/dvb-frontends/mb86a20s.c
1797
rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff);
drivers/media/dvb-frontends/mb86a20s.c
1800
rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff);
drivers/media/dvb-frontends/mb86a20s.c
1803
rc = mb86a20s_writereg(state, 0x2b, pll & 0xff);
drivers/media/dvb-frontends/mb86a20s.c
1807
__func__, fclk, state->if_freq, (long long)pll);
drivers/media/dvb-frontends/mb86a20s.c
1810
pll = state->if_freq * 1677721600L;
drivers/media/dvb-frontends/mb86a20s.c
1811
do_div(pll, 1628571429L);
drivers/media/dvb-frontends/mb86a20s.c
1815
rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff);
drivers/media/dvb-frontends/mb86a20s.c
1818
rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff);
drivers/media/dvb-frontends/mb86a20s.c
1821
rc = mb86a20s_writereg(state, 0x2b, pll & 0xff);
drivers/media/dvb-frontends/mb86a20s.c
1825
__func__, state->if_freq, (long long)pll);
drivers/media/i2c/adv7604.c
1008
const u8 pll[2] = {
drivers/media/i2c/adv7604.c
1026
0x16, pll, 2))
drivers/media/i2c/adv7842.c
1054
const u8 pll[2] = {
drivers/media/i2c/adv7842.c
1073
if (i2c_smbus_write_i2c_block_data(client, 0x16, 2, pll)) {
drivers/media/i2c/aptina-pll.c
128
pll->ext_clock * pll->m));
drivers/media/i2c/aptina-pll.c
130
(pll->ext_clock * pll->m));
drivers/media/i2c/aptina-pll.c
139
mf_low = roundup(max(mf_min, DIV_ROUND_UP(pll->ext_clock * p1,
drivers/media/i2c/aptina-pll.c
141
mf_high = min(mf_max, pll->ext_clock * p1 /
drivers/media/i2c/aptina-pll.c
147
pll->n = div * mf_low / p1;
drivers/media/i2c/aptina-pll.c
148
pll->m *= mf_low;
drivers/media/i2c/aptina-pll.c
149
pll->p1 = p1;
drivers/media/i2c/aptina-pll.c
150
dev_dbg(dev, "PLL: N %u M %u P1 %u\n", pll->n, pll->m, pll->p1);
drivers/media/i2c/aptina-pll.c
17
struct aptina_pll *pll)
drivers/media/i2c/aptina-pll.c
27
pll->ext_clock, pll->pix_clock);
drivers/media/i2c/aptina-pll.c
29
if (pll->ext_clock < limits->ext_clock_min ||
drivers/media/i2c/aptina-pll.c
30
pll->ext_clock > limits->ext_clock_max) {
drivers/media/i2c/aptina-pll.c
35
if (pll->pix_clock == 0 || pll->pix_clock > limits->pix_clock_max) {
drivers/media/i2c/aptina-pll.c
41
div = gcd(pll->pix_clock, pll->ext_clock);
drivers/media/i2c/aptina-pll.c
42
pll->m = pll->pix_clock / div;
drivers/media/i2c/aptina-pll.c
43
div = pll->ext_clock / div;
drivers/media/i2c/aptina-pll.c
55
mf_min = DIV_ROUND_UP(limits->m_min, pll->m);
drivers/media/i2c/aptina-pll.c
57
(pll->ext_clock / limits->n_min * pll->m));
drivers/media/i2c/aptina-pll.c
59
mf_max = limits->m_max / pll->m;
drivers/media/i2c/aptina-pll.c
61
(pll->ext_clock / limits->n_max * pll->m));
drivers/media/i2c/aptina-pll.h
41
struct aptina_pll *pll);
drivers/media/i2c/ar0521.c
135
} pll;
drivers/media/i2c/ar0521.c
247
u32 pll = AR0521_PLL_MAX + 1;
drivers/media/i2c/ar0521.c
266
if (new_pll < pll) {
drivers/media/i2c/ar0521.c
267
pll = new_pll;
drivers/media/i2c/ar0521.c
273
pll = div64_round(sensor->extclk_freq * (u64)mult, pre);
drivers/media/i2c/ar0521.c
276
return pll;
drivers/media/i2c/ar0521.c
334
sensor->pll.vt_pix = bpp / 2;
drivers/media/i2c/ar0521.c
335
vco = pixel_clock * sensor->pll.vt_pix;
drivers/media/i2c/ar0521.c
339
sensor->pll.pre = sensor->pll.pre2 = pre;
drivers/media/i2c/ar0521.c
340
sensor->pll.mult = sensor->pll.mult2 = mult;
drivers/media/i2c/ar0521.c
347
/* 0x300 */ be(sensor->pll.vt_pix), /* vt_pix_clk_div = bpp / 2 */
drivers/media/i2c/ar0521.c
349
/* 0x304 */ be((sensor->pll.pre2 << 8) | sensor->pll.pre),
drivers/media/i2c/ar0521.c
350
/* 0x306 */ be((sensor->pll.mult2 << 8) | sensor->pll.mult),
drivers/media/i2c/ar0521.c
351
/* 0x308 */ be(sensor->pll.vt_pix * 2), /* op_pix_clk_div = 2 * vt_pix_clk_div */
drivers/media/i2c/ccs-pll.c
108
if (!(pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) ||
drivers/media/i2c/ccs-pll.c
123
pll->pixel_rate_pixel_array);
drivers/media/i2c/ccs-pll.c
125
pll->pixel_rate_csi);
drivers/media/i2c/ccs-pll.c
128
static void print_pll_flags(struct device *dev, struct ccs_pll *pll)
drivers/media/i2c/ccs-pll.c
131
pll->flags & PLL_FL(OP_PIX_CLOCK_PER_LANE) ? " op-pix-clock-per-lane" : "",
drivers/media/i2c/ccs-pll.c
132
pll->flags & PLL_FL(EVEN_PLL_MULTIPLIER) ? " even-pll-multiplier" : "",
drivers/media/i2c/ccs-pll.c
133
pll->flags & PLL_FL(NO_OP_CLOCKS) ? " no-op-clocks" : "",
drivers/media/i2c/ccs-pll.c
134
pll->flags & PLL_FL(LANE_SPEED_MODEL) ? " lane-speed" : "",
drivers/media/i2c/ccs-pll.c
135
pll->flags & PLL_FL(EXT_IP_PLL_DIVIDER) ?
drivers/media/i2c/ccs-pll.c
137
pll->flags & PLL_FL(FLEXIBLE_OP_PIX_CLK_DIV) ?
drivers/media/i2c/ccs-pll.c
139
pll->flags & PLL_FL(FIFO_DERATING) ? " fifo-derating" : "",
drivers/media/i2c/ccs-pll.c
140
pll->flags & PLL_FL(FIFO_OVERRATING) ? " fifo-overrating" : "",
drivers/media/i2c/ccs-pll.c
141
pll->flags & PLL_FL(DUAL_PLL) ? " dual-pll" : "",
drivers/media/i2c/ccs-pll.c
142
pll->flags & PLL_FL(OP_SYS_DDR) ? " op-sys-ddr" : "",
drivers/media/i2c/ccs-pll.c
143
pll->flags & PLL_FL(OP_PIX_DDR) ? " op-pix-ddr" : "");
drivers/media/i2c/ccs-pll.c
158
const struct ccs_pll *pll, unsigned int which)
drivers/media/i2c/ccs-pll.c
167
pll_fr = &pll->op_fr;
drivers/media/i2c/ccs-pll.c
170
pll_fr = &pll->vt_fr;
drivers/media/i2c/ccs-pll.c
198
const struct ccs_pll *pll, unsigned int which)
drivers/media/i2c/ccs-pll.c
206
if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)
drivers/media/i2c/ccs-pll.c
210
pll_bk = &pll->op_bk;
drivers/media/i2c/ccs-pll.c
213
pll_bk = &pll->vt_bk;
drivers/media/i2c/ccs-pll.c
238
static int check_ext_bounds(struct device *dev, const struct ccs_pll *pll)
drivers/media/i2c/ccs-pll.c
240
if (!(pll->flags & CCS_PLL_FLAG_FIFO_DERATING) &&
drivers/media/i2c/ccs-pll.c
241
pll->pixel_rate_pixel_array > pll->pixel_rate_csi) {
drivers/media/i2c/ccs-pll.c
246
if (!(pll->flags & CCS_PLL_FLAG_FIFO_OVERRATING) &&
drivers/media/i2c/ccs-pll.c
247
pll->pixel_rate_pixel_array < pll->pixel_rate_csi) {
drivers/media/i2c/ccs-pll.c
257
struct ccs_pll *pll, struct ccs_pll_branch_fr *pll_fr,
drivers/media/i2c/ccs-pll.c
297
struct ccs_pll *pll, u32 mul, u32 div)
drivers/media/i2c/ccs-pll.c
301
struct ccs_pll_branch_fr *pll_fr = &pll->vt_fr;
drivers/media/i2c/ccs-pll.c
302
struct ccs_pll_branch_bk *pll_bk = &pll->vt_bk;
drivers/media/i2c/ccs-pll.c
308
pll->ext_clk_freq_hz / pll_fr->pre_pll_clk_div;
drivers/media/i2c/ccs-pll.c
319
if (pll->flags & CCS_PLL_FLAG_EVEN_PLL_MULTIPLIER &&
drivers/media/i2c/ccs-pll.c
340
ccs_pll_find_vt_sys_div(dev, lim, pll, pll_fr, vt_div, vt_div,
drivers/media/i2c/ccs-pll.c
385
pll->pixel_rate_pixel_array =
drivers/media/i2c/ccs-pll.c
386
pll_bk->pix_clk_freq_hz * pll->vt_lanes;
drivers/media/i2c/ccs-pll.c
393
struct ccs_pll *pll)
drivers/media/i2c/ccs-pll.c
396
struct ccs_pll_branch_fr *pll_fr = &pll->vt_fr;
drivers/media/i2c/ccs-pll.c
401
pre_div = gcd(pll->pixel_rate_csi,
drivers/media/i2c/ccs-pll.c
402
pll->ext_clk_freq_hz * pll->vt_lanes);
drivers/media/i2c/ccs-pll.c
403
pre_mul = pll->pixel_rate_csi / pre_div;
drivers/media/i2c/ccs-pll.c
404
pre_div = pll->ext_clk_freq_hz * pll->vt_lanes / pre_div;
drivers/media/i2c/ccs-pll.c
409
DIV_ROUND_UP(pll->ext_clk_freq_hz,
drivers/media/i2c/ccs-pll.c
413
pll->ext_clk_freq_hz /
drivers/media/i2c/ccs-pll.c
415
if (!(pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER))
drivers/media/i2c/ccs-pll.c
424
(pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER) ? 1 :
drivers/media/i2c/ccs-pll.c
436
rval = __ccs_pll_calculate_vt_tree(dev, lim, pll,
drivers/media/i2c/ccs-pll.c
441
rval = check_fr_bounds(dev, lim, pll, PLL_VT);
drivers/media/i2c/ccs-pll.c
445
rval = check_bk_bounds(dev, lim, pll, PLL_VT);
drivers/media/i2c/ccs-pll.c
459
struct ccs_pll *pll, struct ccs_pll_branch_fr *pll_fr,
drivers/media/i2c/ccs-pll.c
469
if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)
drivers/media/i2c/ccs-pll.c
476
if (!(pll->flags & CCS_PLL_FLAG_FIFO_DERATING)) {
drivers/media/i2c/ccs-pll.c
479
* pll->vt_lanes * phy_const / pll->op_lanes
drivers/media/i2c/ccs-pll.c
480
/ (PHY_CONST_DIV << op_pix_ddr(pll->flags));
drivers/media/i2c/ccs-pll.c
490
/ pll->binning_horizontal)
drivers/media/i2c/ccs-pll.c
491
vt_op_binning_div = pll->binning_horizontal;
drivers/media/i2c/ccs-pll.c
507
dev_dbg(dev, "scale_m: %u\n", pll->scale_m);
drivers/media/i2c/ccs-pll.c
509
DIV_ROUND_UP(pll->bits_per_pixel
drivers/media/i2c/ccs-pll.c
510
* op_pll_bk->sys_clk_div * pll->scale_n
drivers/media/i2c/ccs-pll.c
511
* pll->vt_lanes * phy_const,
drivers/media/i2c/ccs-pll.c
512
(pll->flags &
drivers/media/i2c/ccs-pll.c
514
pll->csi2.lanes : 1)
drivers/media/i2c/ccs-pll.c
515
* vt_op_binning_div * pll->scale_m
drivers/media/i2c/ccs-pll.c
516
* PHY_CONST_DIV << op_pix_ddr(pll->flags));
drivers/media/i2c/ccs-pll.c
538
ccs_pll_find_vt_sys_div(dev, lim, pll, pll_fr, min_vt_div,
drivers/media/i2c/ccs-pll.c
582
pll->vt_bk.sys_clk_div = DIV_ROUND_UP(vt_div, best_pix_div);
drivers/media/i2c/ccs-pll.c
583
pll->vt_bk.pix_clk_div = best_pix_div;
drivers/media/i2c/ccs-pll.c
585
pll->vt_bk.sys_clk_freq_hz =
drivers/media/i2c/ccs-pll.c
586
pll_fr->pll_op_clk_freq_hz / pll->vt_bk.sys_clk_div;
drivers/media/i2c/ccs-pll.c
587
pll->vt_bk.pix_clk_freq_hz =
drivers/media/i2c/ccs-pll.c
588
pll->vt_bk.sys_clk_freq_hz / pll->vt_bk.pix_clk_div;
drivers/media/i2c/ccs-pll.c
591
pll->pixel_rate_pixel_array =
drivers/media/i2c/ccs-pll.c
592
pll->vt_bk.pix_clk_freq_hz * pll->vt_lanes;
drivers/media/i2c/ccs-pll.c
612
struct ccs_pll *pll, struct ccs_pll_branch_fr *op_pll_fr,
drivers/media/i2c/ccs-pll.c
642
/ (pll->ext_clk_freq_hz /
drivers/media/i2c/ccs-pll.c
659
pll->ext_clk_freq_hz /
drivers/media/i2c/ccs-pll.c
684
if (pll->flags & CCS_PLL_FLAG_EVEN_PLL_MULTIPLIER &&
drivers/media/i2c/ccs-pll.c
698
op_pll_fr->pll_ip_clk_freq_hz = pll->ext_clk_freq_hz
drivers/media/i2c/ccs-pll.c
704
if (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL)
drivers/media/i2c/ccs-pll.c
706
(pll->bits_per_pixel
drivers/media/i2c/ccs-pll.c
707
* pll->op_lanes * (phy_const << op_sys_ddr(pll->flags))
drivers/media/i2c/ccs-pll.c
708
/ PHY_CONST_DIV / pll->csi2.lanes / l)
drivers/media/i2c/ccs-pll.c
709
>> op_pix_ddr(pll->flags);
drivers/media/i2c/ccs-pll.c
712
(pll->bits_per_pixel
drivers/media/i2c/ccs-pll.c
713
* (phy_const << op_sys_ddr(pll->flags))
drivers/media/i2c/ccs-pll.c
714
/ PHY_CONST_DIV / l) >> op_pix_ddr(pll->flags);
drivers/media/i2c/ccs-pll.c
717
(op_sys_clk_freq_hz_sdr >> op_pix_ddr(pll->flags))
drivers/media/i2c/ccs-pll.c
720
op_sys_clk_freq_hz_sdr >> op_sys_ddr(pll->flags);
drivers/media/i2c/ccs-pll.c
728
struct ccs_pll *pll)
drivers/media/i2c/ccs-pll.c
734
bool cphy = pll->bus_type == CCS_PLL_BUS_TYPE_CSI2_CPHY;
drivers/media/i2c/ccs-pll.c
740
u32 l = (!pll->op_bits_per_lane ||
drivers/media/i2c/ccs-pll.c
741
pll->op_bits_per_lane >= pll->bits_per_pixel) ? 1 : 2;
drivers/media/i2c/ccs-pll.c
745
print_pll_flags(dev, pll);
drivers/media/i2c/ccs-pll.c
747
if (!(pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL)) {
drivers/media/i2c/ccs-pll.c
748
pll->op_lanes = 1;
drivers/media/i2c/ccs-pll.c
749
pll->vt_lanes = 1;
drivers/media/i2c/ccs-pll.c
752
if (pll->flags & CCS_PLL_FLAG_DUAL_PLL) {
drivers/media/i2c/ccs-pll.c
755
op_pll_fr = &pll->op_fr;
drivers/media/i2c/ccs-pll.c
756
op_pll_bk = &pll->op_bk;
drivers/media/i2c/ccs-pll.c
757
} else if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) {
drivers/media/i2c/ccs-pll.c
765
op_pll_fr = &pll->vt_fr;
drivers/media/i2c/ccs-pll.c
766
op_pll_bk = &pll->vt_bk;
drivers/media/i2c/ccs-pll.c
770
op_pll_fr = &pll->vt_fr;
drivers/media/i2c/ccs-pll.c
771
op_pll_bk = &pll->op_bk;
drivers/media/i2c/ccs-pll.c
774
if (!pll->op_lanes || !pll->vt_lanes || !pll->bits_per_pixel ||
drivers/media/i2c/ccs-pll.c
775
!pll->ext_clk_freq_hz || !pll->link_freq || !pll->scale_m ||
drivers/media/i2c/ccs-pll.c
78
static void print_pll(struct device *dev, const struct ccs_pll *pll)
drivers/media/i2c/ccs-pll.c
787
if (!(pll->flags & CCS_PLL_FLAG_FLEXIBLE_OP_PIX_CLK_DIV) &&
drivers/media/i2c/ccs-pll.c
788
(pll->bits_per_pixel * pll->op_lanes) %
drivers/media/i2c/ccs-pll.c
789
(pll->csi2.lanes * l << op_pix_ddr(pll->flags))) {
drivers/media/i2c/ccs-pll.c
791
pll->bits_per_pixel, pll->op_lanes, pll->csi2.lanes, l);
drivers/media/i2c/ccs-pll.c
795
dev_dbg(dev, "vt_lanes: %u\n", pll->vt_lanes);
drivers/media/i2c/ccs-pll.c
796
dev_dbg(dev, "op_lanes: %u\n", pll->op_lanes);
drivers/media/i2c/ccs-pll.c
798
dev_dbg(dev, "binning: %ux%u\n", pll->binning_horizontal,
drivers/media/i2c/ccs-pll.c
799
pll->binning_vertical);
drivers/media/i2c/ccs-pll.c
801
switch (pll->bus_type) {
drivers/media/i2c/ccs-pll.c
804
op_sys_clk_freq_hz_sdr = pll->link_freq * 2
drivers/media/i2c/ccs-pll.c
805
* (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
drivers/media/i2c/ccs-pll.c
806
1 : pll->csi2.lanes);
drivers/media/i2c/ccs-pll.c
812
pll->pixel_rate_csi =
drivers/media/i2c/ccs-pll.c
814
* (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
drivers/media/i2c/ccs-pll.c
815
pll->csi2.lanes : 1) * PHY_CONST_DIV,
drivers/media/i2c/ccs-pll.c
816
phy_const * pll->bits_per_pixel * l);
drivers/media/i2c/ccs-pll.c
823
DIV_ROUND_UP(pll->ext_clk_freq_hz,
drivers/media/i2c/ccs-pll.c
827
DIV_ROUND_UP(pll->ext_clk_freq_hz,
drivers/media/i2c/ccs-pll.c
833
pll->ext_clk_freq_hz << op_pix_ddr(pll->flags));
drivers/media/i2c/ccs-pll.c
835
div = (pll->ext_clk_freq_hz << op_pix_ddr(pll->flags)) / i;
drivers/media/i2c/ccs-pll.c
844
pll->ext_clk_freq_hz))));
drivers/media/i2c/ccs-pll.c
845
if (!(pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER))
drivers/media/i2c/ccs-pll.c
85
{ &pll->vt_fr, &pll->vt_bk, PLL_VT },
drivers/media/i2c/ccs-pll.c
853
(pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER) ? 1 :
drivers/media/i2c/ccs-pll.c
855
rval = ccs_pll_calculate_op(dev, lim, op_lim_fr, op_lim_bk, pll,
drivers/media/i2c/ccs-pll.c
86
{ &pll->op_fr, &pll->op_bk, PLL_OP }
drivers/media/i2c/ccs-pll.c
862
rval = check_fr_bounds(dev, lim, pll,
drivers/media/i2c/ccs-pll.c
863
pll->flags & CCS_PLL_FLAG_DUAL_PLL ?
drivers/media/i2c/ccs-pll.c
868
rval = check_bk_bounds(dev, lim, pll, PLL_OP);
drivers/media/i2c/ccs-pll.c
872
if (pll->flags & CCS_PLL_FLAG_DUAL_PLL)
drivers/media/i2c/ccs-pll.c
875
rval = ccs_pll_calculate_vt(dev, lim, op_lim_bk, pll, op_pll_fr,
drivers/media/i2c/ccs-pll.c
880
rval = check_bk_bounds(dev, lim, pll, PLL_VT);
drivers/media/i2c/ccs-pll.c
883
rval = check_ext_bounds(dev, pll);
drivers/media/i2c/ccs-pll.c
895
if (pll->flags & CCS_PLL_FLAG_DUAL_PLL) {
drivers/media/i2c/ccs-pll.c
896
rval = ccs_pll_calculate_vt_tree(dev, lim, pll);
drivers/media/i2c/ccs-pll.c
90
dev_dbg(dev, "ext_clk_freq_hz\t\t%u\n", pll->ext_clk_freq_hz);
drivers/media/i2c/ccs-pll.c
902
print_pll(dev, pll);
drivers/media/i2c/ccs-pll.c
95
if (pll->flags & CCS_PLL_FLAG_DUAL_PLL ||
drivers/media/i2c/ccs-pll.h
233
struct ccs_pll *pll);
drivers/media/i2c/ccs/ccs-core.c
1154
struct ccs_pll *pll = &sensor->pll;
drivers/media/i2c/ccs/ccs-core.c
1218
pll->binning_horizontal = 1;
drivers/media/i2c/ccs/ccs-core.c
1219
pll->binning_vertical = 1;
drivers/media/i2c/ccs/ccs-core.c
1220
pll->scale_m = CCS_LIM(sensor, SCALER_N_MIN);
drivers/media/i2c/ccs/ccs-core.c
1249
pll->bits_per_pixel = f->compressed;
drivers/media/i2c/ccs/ccs-core.c
1252
pll->link_freq = sensor->hwcfg.op_sys_clock[j];
drivers/media/i2c/ccs/ccs-core.c
1254
rval = ccs_pll_try(sensor, pll);
drivers/media/i2c/ccs/ccs-core.c
1256
pll->link_freq, pll->bits_per_pixel,
drivers/media/i2c/ccs/ccs-core.c
1352
sensor->pll.pixel_rate_pixel_array /
drivers/media/i2c/ccs/ccs-core.c
3459
sensor->pll.flags |= CCS_PLL_FLAG_NO_OP_CLOCKS;
drivers/media/i2c/ccs/ccs-core.c
3476
sensor->pll.bus_type = CCS_PLL_BUS_TYPE_CSI2_CPHY;
drivers/media/i2c/ccs/ccs-core.c
3481
sensor->pll.bus_type = CCS_PLL_BUS_TYPE_CSI2_DPHY;
drivers/media/i2c/ccs/ccs-core.c
3489
sensor->pll.csi2.lanes = sensor->hwcfg.lanes;
drivers/media/i2c/ccs/ccs-core.c
3492
sensor->pll.flags |= CCS_PLL_FLAG_LANE_SPEED_MODEL;
drivers/media/i2c/ccs/ccs-core.c
3495
sensor->pll.vt_lanes =
drivers/media/i2c/ccs/ccs-core.c
3497
sensor->pll.op_lanes =
drivers/media/i2c/ccs/ccs-core.c
3500
sensor->pll.vt_lanes = sensor->pll.csi2.lanes;
drivers/media/i2c/ccs/ccs-core.c
3501
sensor->pll.op_lanes = sensor->pll.csi2.lanes;
drivers/media/i2c/ccs/ccs-core.c
3506
sensor->pll.flags |= CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER;
drivers/media/i2c/ccs/ccs-core.c
3509
sensor->pll.flags |= CCS_PLL_FLAG_FLEXIBLE_OP_PIX_CLK_DIV;
drivers/media/i2c/ccs/ccs-core.c
3512
sensor->pll.flags |= CCS_PLL_FLAG_FIFO_DERATING;
drivers/media/i2c/ccs/ccs-core.c
3515
sensor->pll.flags |= CCS_PLL_FLAG_FIFO_DERATING |
drivers/media/i2c/ccs/ccs-core.c
3529
sensor->pll.flags |= CCS_PLL_FLAG_DUAL_PLL;
drivers/media/i2c/ccs/ccs-core.c
3531
sensor->pll.flags |= CCS_PLL_FLAG_DUAL_PLL;
drivers/media/i2c/ccs/ccs-core.c
3535
sensor->pll.flags |= CCS_PLL_FLAG_OP_SYS_DDR;
drivers/media/i2c/ccs/ccs-core.c
3538
sensor->pll.flags |= CCS_PLL_FLAG_OP_PIX_DDR;
drivers/media/i2c/ccs/ccs-core.c
3540
sensor->pll.op_bits_per_lane = CCS_LIM(sensor, OP_BITS_PER_LANE);
drivers/media/i2c/ccs/ccs-core.c
3541
sensor->pll.ext_clk_freq_hz = sensor->hwcfg.ext_clk;
drivers/media/i2c/ccs/ccs-core.c
3542
sensor->pll.scale_n = CCS_LIM(sensor, SCALER_N_MIN);
drivers/media/i2c/ccs/ccs-core.c
405
struct ccs_pll *pll = &sensor->pll;
drivers/media/i2c/ccs/ccs-core.c
408
rval = ccs_write(sensor, VT_PIX_CLK_DIV, pll->vt_bk.pix_clk_div);
drivers/media/i2c/ccs/ccs-core.c
412
rval = ccs_write(sensor, VT_SYS_CLK_DIV, pll->vt_bk.sys_clk_div);
drivers/media/i2c/ccs/ccs-core.c
416
rval = ccs_write(sensor, PRE_PLL_CLK_DIV, pll->vt_fr.pre_pll_clk_div);
drivers/media/i2c/ccs/ccs-core.c
420
rval = ccs_write(sensor, PLL_MULTIPLIER, pll->vt_fr.pll_multiplier);
drivers/media/i2c/ccs/ccs-core.c
428
DIV_ROUND_UP(pll->op_bk.sys_clk_freq_hz,
drivers/media/i2c/ccs/ccs-core.c
430
(pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
drivers/media/i2c/ccs/ccs-core.c
431
sensor->pll.csi2.lanes : 1) <<
drivers/media/i2c/ccs/ccs-core.c
432
(pll->flags & CCS_PLL_FLAG_OP_SYS_DDR ?
drivers/media/i2c/ccs/ccs-core.c
438
if (sensor->pll.flags & CCS_PLL_FLAG_NO_OP_CLOCKS)
drivers/media/i2c/ccs/ccs-core.c
441
rval = ccs_write(sensor, OP_PIX_CLK_DIV, pll->op_bk.pix_clk_div);
drivers/media/i2c/ccs/ccs-core.c
445
rval = ccs_write(sensor, OP_SYS_CLK_DIV, pll->op_bk.sys_clk_div);
drivers/media/i2c/ccs/ccs-core.c
449
if (!(pll->flags & CCS_PLL_FLAG_DUAL_PLL))
drivers/media/i2c/ccs/ccs-core.c
457
pll->op_fr.pre_pll_clk_div);
drivers/media/i2c/ccs/ccs-core.c
461
return ccs_write(sensor, OP_PLL_MULTIPLIER, pll->op_fr.pll_multiplier);
drivers/media/i2c/ccs/ccs-core.c
464
static int ccs_pll_try(struct ccs_sensor *sensor, struct ccs_pll *pll)
drivers/media/i2c/ccs/ccs-core.c
512
return ccs_pll_calculate(&client->dev, &lim, pll);
drivers/media/i2c/ccs/ccs-core.c
563
struct ccs_pll *pll = &sensor->pll;
drivers/media/i2c/ccs/ccs-core.c
575
pll->binning_horizontal = binh;
drivers/media/i2c/ccs/ccs-core.c
576
pll->binning_vertical = binv;
drivers/media/i2c/ccs/ccs-core.c
577
pll->link_freq =
drivers/media/i2c/ccs/ccs-core.c
579
pll->scale_m = scale_m;
drivers/media/i2c/ccs/ccs-core.c
580
pll->bits_per_pixel = sensor->csi_format->compressed;
drivers/media/i2c/ccs/ccs-core.c
582
rval = ccs_pll_try(sensor, pll);
drivers/media/i2c/ccs/ccs-core.c
587
pll->pixel_rate_pixel_array);
drivers/media/i2c/ccs/ccs-core.c
588
__v4l2_ctrl_s_ctrl_int64(sensor->pixel_rate_csi, pll->pixel_rate_csi);
drivers/media/i2c/ccs/ccs-quirk.c
193
sensor->pll.flags |= CCS_PLL_FLAG_LANE_SPEED_MODEL;
drivers/media/i2c/ccs/ccs-quirk.c
194
sensor->pll.vt_lanes = 1;
drivers/media/i2c/ccs/ccs-quirk.c
195
sensor->pll.op_lanes = sensor->pll.csi2.lanes;
drivers/media/i2c/ccs/ccs.h
245
struct ccs_pll pll;
drivers/media/i2c/cx25840/cx25840-core.c
1212
int pll = (28636363L * ((((u64)pll_int) << 25L) + pll_frac)) >> 25L;
drivers/media/i2c/cx25840/cx25840-core.c
1214
pll /= pll_post;
drivers/media/i2c/cx25840/cx25840-core.c
1217
pll / 1000000, pll % 1000000);
drivers/media/i2c/cx25840/cx25840-core.c
1220
pll / 8000000, (pll / 8) % 1000000);
drivers/media/i2c/cx25840/cx25840-core.c
1222
fin = ((u64)src_decimation * pll) >> 12;
drivers/media/i2c/cx25840/cx25840-core.c
1227
fsc = (((u64)sc) * pll) >> 24L;
drivers/media/i2c/imx111.c
1065
sensor->pll->pre_div, &ret);
drivers/media/i2c/imx111.c
1067
sensor->pll->mult, &ret);
drivers/media/i2c/imx111.c
1071
to_settle_delay(sensor->pll->extclk_rate), &ret);
drivers/media/i2c/imx111.c
1396
sensor->pll = &imx111_pll[i];
drivers/media/i2c/imx111.c
1400
if (!sensor->pll)
drivers/media/i2c/imx111.c
1405
system_clk = div_u64(extclk_rate, sensor->pll->pre_div) *
drivers/media/i2c/imx111.c
1406
sensor->pll->mult;
drivers/media/i2c/imx111.c
194
const struct imx111_pll *pll;
drivers/media/i2c/imx214.c
1139
bit_rate_mbps = imx214->pll.pixel_rate_csi / 1000000
drivers/media/i2c/imx214.c
1140
* imx214->pll.bits_per_pixel;
drivers/media/i2c/imx214.c
1360
struct ccs_pll pll;
drivers/media/i2c/imx214.c
1370
if (!imx214_pll_calculate(imx214, &pll, freq))
drivers/media/i2c/imx214.c
253
struct ccs_pll pll;
drivers/media/i2c/imx214.c
767
imx214->pll.vt_bk.pix_clk_div, &ret);
drivers/media/i2c/imx214.c
769
imx214->pll.vt_bk.sys_clk_div, &ret);
drivers/media/i2c/imx214.c
771
imx214->pll.vt_fr.pre_pll_clk_div, &ret);
drivers/media/i2c/imx214.c
773
imx214->pll.vt_fr.pll_multiplier, &ret);
drivers/media/i2c/imx214.c
775
imx214->pll.op_bk.pix_clk_div, &ret);
drivers/media/i2c/imx214.c
777
imx214->pll.op_bk.sys_clk_div, &ret);
drivers/media/i2c/imx214.c
781
IMX214_EXCK_FREQ(imx214->pll.ext_clk_freq_hz / 1000000), &ret);
drivers/media/i2c/imx214.c
884
static int imx214_pll_calculate(struct imx214 *imx214, struct ccs_pll *pll,
drivers/media/i2c/imx214.c
945
memset(pll, 0, sizeof(*pll));
drivers/media/i2c/imx214.c
947
pll->bus_type = CCS_PLL_BUS_TYPE_CSI2_DPHY;
drivers/media/i2c/imx214.c
948
pll->op_lanes = num_lanes;
drivers/media/i2c/imx214.c
949
pll->vt_lanes = num_lanes;
drivers/media/i2c/imx214.c
950
pll->csi2.lanes = num_lanes;
drivers/media/i2c/imx214.c
952
pll->binning_horizontal = 1;
drivers/media/i2c/imx214.c
953
pll->binning_vertical = 1;
drivers/media/i2c/imx214.c
954
pll->scale_m = 1;
drivers/media/i2c/imx214.c
955
pll->scale_n = 1;
drivers/media/i2c/imx214.c
956
pll->bits_per_pixel =
drivers/media/i2c/imx214.c
958
pll->flags = CCS_PLL_FLAG_LANE_SPEED_MODEL;
drivers/media/i2c/imx214.c
959
pll->link_freq = link_freq;
drivers/media/i2c/imx214.c
960
pll->ext_clk_freq_hz = clk_get_rate(imx214->xclk);
drivers/media/i2c/imx214.c
962
return ccs_pll_calculate(imx214->dev, &limits, pll);
drivers/media/i2c/imx214.c
971
ret = imx214_pll_calculate(imx214, &imx214->pll, link_freq);
drivers/media/i2c/imx214.c
978
imx214->pll.pixel_rate_pixel_array);
drivers/media/i2c/mt9m114.c
2411
sensor->pll.ext_clock = clk_get_rate(sensor->clk);
drivers/media/i2c/mt9m114.c
2412
sensor->pll.pix_clock = MT9M114_DEF_PIXCLOCK;
drivers/media/i2c/mt9m114.c
2414
ret = aptina_pll_calculate(&sensor->client->dev, &limits, &sensor->pll);
drivers/media/i2c/mt9m114.c
2418
pixrate = sensor->pll.ext_clock * sensor->pll.m
drivers/media/i2c/mt9m114.c
2419
/ (sensor->pll.n * sensor->pll.p1);
drivers/media/i2c/mt9m114.c
395
struct aptina_pll pll;
drivers/media/i2c/mt9m114.c
763
MT9M114_CAM_SYSCTL_PLL_DIVIDER_VALUE(sensor->pll.m,
drivers/media/i2c/mt9m114.c
764
sensor->pll.n),
drivers/media/i2c/mt9m114.c
767
MT9M114_CAM_SYSCTL_PLL_DIVIDER_P_VALUE(sensor->pll.p1),
drivers/media/i2c/mt9p031.c
133
struct aptina_pll pll;
drivers/media/i2c/mt9p031.c
261
mt9p031->pll.ext_clock = ext_freq;
drivers/media/i2c/mt9p031.c
262
mt9p031->pll.pix_clock = mt9p031->target_freq;
drivers/media/i2c/mt9p031.c
265
return aptina_pll_calculate(&client->dev, &limits, &mt9p031->pll);
drivers/media/i2c/mt9p031.c
282
(mt9p031->pll.m << 8) | (mt9p031->pll.n - 1));
drivers/media/i2c/mt9p031.c
286
ret = mt9p031_write(client, MT9P031_PLL_CONFIG_2, mt9p031->pll.p1 - 1);
drivers/media/i2c/ov2659.c
210
struct ov2659_pll_ctrl pll;
drivers/media/i2c/ov2659.c
924
ov2659->pll.ctrl1 = ctrl1_reg;
drivers/media/i2c/ov2659.c
925
ov2659->pll.ctrl2 = ctrl2_reg;
drivers/media/i2c/ov2659.c
926
ov2659->pll.ctrl3 = ctrl3_reg;
drivers/media/i2c/ov2659.c
937
{REG_SC_PLL_CTRL1, ov2659->pll.ctrl1},
drivers/media/i2c/ov2659.c
938
{REG_SC_PLL_CTRL2, ov2659->pll.ctrl2},
drivers/media/i2c/ov2659.c
939
{REG_SC_PLL_CTRL3, ov2659->pll.ctrl3},
drivers/media/pci/bt8xx/bttv-cards.c
1001
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1015
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1029
.pll = PLL_35,
drivers/media/pci/bt8xx/bttv-cards.c
1045
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1058
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
107
module_param_array(pll, int, NULL, 0444);
drivers/media/pci/bt8xx/bttv-cards.c
1075
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1098
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1123
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1138
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1161
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1176
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
118
MODULE_PARM_DESC(pll, "specify installed crystal (0=none, 28=28 MHz, 35=35 MHz, 14=14 MHz)");
drivers/media/pci/bt8xx/bttv-cards.c
1192
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1208
.pll = PLL_35,
drivers/media/pci/bt8xx/bttv-cards.c
1222
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1236
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1253
.pll = PLL_35,
drivers/media/pci/bt8xx/bttv-cards.c
1267
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1283
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1297
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1313
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1332
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1345
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1360
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1384
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1404
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1414
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1428
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1447
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1465
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1517
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1545
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1566
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1588
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1600
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1617
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1629
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1641
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1655
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1667
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1679
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1691
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1705
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1717
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1729
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1739
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1753
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1771
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1783
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1796
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1821
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1832
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1846
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1863
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1878
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1903
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1921
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1932
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1946
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1957
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1975
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
1988
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2000
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2016
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2030
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2043
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2058
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2092
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2104
.pll = PLL_35,
drivers/media/pci/bt8xx/bttv-cards.c
2115
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2129
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2157
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2172
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2194
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2223
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2238
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2256
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2271
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2287
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2300
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2317
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2342
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2378
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2399
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2415
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2445
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2460
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2479
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2496
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2524
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2540
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2555
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2591
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2638
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2653
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2671
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2694
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2707
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2720
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2733
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2759
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2783
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2797
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2809
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2828
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2835
.pll = PLL_14,
drivers/media/pci/bt8xx/bttv-cards.c
2844
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2858
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
2878
.pll = PLL_35,
drivers/media/pci/bt8xx/bttv-cards.c
3439
if (PLL_28 == bttv_tvcards[btv->c.type].pll) {
drivers/media/pci/bt8xx/bttv-cards.c
3440
btv->pll.pll_ifreq=28636363;
drivers/media/pci/bt8xx/bttv-cards.c
3441
btv->pll.pll_crystal=BT848_IFORM_XT0;
drivers/media/pci/bt8xx/bttv-cards.c
3443
if (PLL_35 == bttv_tvcards[btv->c.type].pll) {
drivers/media/pci/bt8xx/bttv-cards.c
3444
btv->pll.pll_ifreq=35468950;
drivers/media/pci/bt8xx/bttv-cards.c
3445
btv->pll.pll_crystal=BT848_IFORM_XT1;
drivers/media/pci/bt8xx/bttv-cards.c
3447
if (PLL_14 == bttv_tvcards[btv->c.type].pll) {
drivers/media/pci/bt8xx/bttv-cards.c
3448
btv->pll.pll_ifreq = 14318181;
drivers/media/pci/bt8xx/bttv-cards.c
3449
btv->pll.pll_crystal = BT848_IFORM_XT0;
drivers/media/pci/bt8xx/bttv-cards.c
3452
switch (pll[btv->c.nr]) {
drivers/media/pci/bt8xx/bttv-cards.c
3454
btv->pll.pll_crystal = 0;
drivers/media/pci/bt8xx/bttv-cards.c
3455
btv->pll.pll_ifreq = 0;
drivers/media/pci/bt8xx/bttv-cards.c
3456
btv->pll.pll_ofreq = 0;
drivers/media/pci/bt8xx/bttv-cards.c
3460
btv->pll.pll_ifreq = 28636363;
drivers/media/pci/bt8xx/bttv-cards.c
3461
btv->pll.pll_ofreq = 0;
drivers/media/pci/bt8xx/bttv-cards.c
3462
btv->pll.pll_crystal = BT848_IFORM_XT0;
drivers/media/pci/bt8xx/bttv-cards.c
3466
btv->pll.pll_ifreq = 35468950;
drivers/media/pci/bt8xx/bttv-cards.c
3467
btv->pll.pll_ofreq = 0;
drivers/media/pci/bt8xx/bttv-cards.c
3468
btv->pll.pll_crystal = BT848_IFORM_XT1;
drivers/media/pci/bt8xx/bttv-cards.c
3472
btv->pll.pll_ifreq = 14318181;
drivers/media/pci/bt8xx/bttv-cards.c
3473
btv->pll.pll_ofreq = 0;
drivers/media/pci/bt8xx/bttv-cards.c
3474
btv->pll.pll_crystal = BT848_IFORM_XT0;
drivers/media/pci/bt8xx/bttv-cards.c
3478
btv->pll.pll_current = -1;
drivers/media/pci/bt8xx/bttv-cards.c
391
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
455
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
467
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
480
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
518
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
533
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
561
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
622
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
635
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
650
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
665
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
705
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
778
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
790
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
816
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
842
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
858
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
86
static unsigned int pll[BTTV_MAX] = { [ 0 ... (BTTV_MAX-1) ] = UNSET };
drivers/media/pci/bt8xx/bttv-cards.c
873
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
888
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
901
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
915
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
933
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
944
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
959
.pll = PLL_28,
drivers/media/pci/bt8xx/bttv-cards.c
988
.pll = PLL_NONE,
drivers/media/pci/bt8xx/bttv-driver.c
1233
btv->pll.pll_current = -1;
drivers/media/pci/bt8xx/bttv-driver.c
784
if (!btv->pll.pll_crystal)
drivers/media/pci/bt8xx/bttv-driver.c
787
if (btv->pll.pll_ofreq == btv->pll.pll_current) {
drivers/media/pci/bt8xx/bttv-driver.c
792
if (btv->pll.pll_ifreq == btv->pll.pll_ofreq) {
drivers/media/pci/bt8xx/bttv-driver.c
794
if (btv->pll.pll_current == 0)
drivers/media/pci/bt8xx/bttv-driver.c
798
btv->c.nr, btv->pll.pll_ifreq);
drivers/media/pci/bt8xx/bttv-driver.c
801
btv->pll.pll_current = 0;
drivers/media/pci/bt8xx/bttv-driver.c
808
btv->pll.pll_ifreq, btv->pll.pll_ofreq);
drivers/media/pci/bt8xx/bttv-driver.c
809
set_pll_freq(btv, btv->pll.pll_ifreq, btv->pll.pll_ofreq);
drivers/media/pci/bt8xx/bttv-driver.c
819
btv->pll.pll_current = btv->pll.pll_ofreq;
drivers/media/pci/bt8xx/bttv-driver.c
825
btv->pll.pll_current = -1;
drivers/media/pci/bt8xx/bttv-driver.c
850
btv->pll.pll_ofreq = 27000000;
drivers/media/pci/bt8xx/bttv-driver.c
856
btv->pll.pll_ofreq = fsc;
drivers/media/pci/bt8xx/bttv.h
236
unsigned int pll:2;
drivers/media/pci/bt8xx/bttvp.h
326
struct bttv_pll_info pll;
drivers/media/pci/bt8xx/dvb-bt8xx.c
192
u32 band, pll;
drivers/media/pci/bt8xx/dvb-bt8xx.c
225
pll=0xf8000000|
drivers/media/pci/bt8xx/dvb-bt8xx.c
237
cx24110_pll_write(fe,pll);
drivers/media/pci/cx18/cx18-av-core.c
447
int fsc, pll;
drivers/media/pci/cx18/cx18-av-core.c
450
pll = (28636360L * ((((u64)pll_int) << 25) + pll_frac)) >> 25;
drivers/media/pci/cx18/cx18-av-core.c
451
pll /= pll_post;
drivers/media/pci/cx18/cx18-av-core.c
453
pll / 1000000, pll % 1000000);
drivers/media/pci/cx18/cx18-av-core.c
455
pll / 8000000, (pll / 8) % 1000000);
drivers/media/pci/cx88/cx88-core.c
757
u64 pll;
drivers/media/pci/cx88/cx88-core.c
766
pll = ofreq * 8 * prescale * (u64)(1 << 20);
drivers/media/pci/cx88/cx88-core.c
767
do_div(pll, xtal);
drivers/media/pci/cx88/cx88-core.c
768
reg = (pll & 0x3ffffff) | (pre[prescale] << 26);
drivers/media/radio/tef6862.c
104
pll = 1964 + ((freq - TEF6862_LO_FREQ) * 20) / FREQ_MUL;
drivers/media/radio/tef6862.c
106
i2cmsg[1] = (pll >> 8) & 0xff;
drivers/media/radio/tef6862.c
107
i2cmsg[2] = pll & 0xff;
drivers/media/radio/tef6862.c
96
u16 pll;
drivers/media/tuners/qm1d1b0004.c
107
u32 frequency, pll, lpf_freq;
drivers/media/tuners/qm1d1b0004.c
115
pll = QM1D1B0004_XTL_FREQ / 4;
drivers/media/tuners/qm1d1b0004.c
117
pll /= 2;
drivers/media/tuners/qm1d1b0004.c
118
word = DIV_ROUND_CLOSEST(frequency, pll);
drivers/media/tuners/r820t.c
80
u16 pll; /* kHz */
drivers/media/tuners/tda18271-common.c
256
enum tda18271_pll pll, int force,
drivers/media/tuners/tda18271-common.c
262
int r_cp = (pll == TDA18271_CAL_PLL) ? R_EB7 : R_EB4;
drivers/media/tuners/tda18271-common.c
271
enum tda18271_pll pll, int force)
drivers/media/tuners/tda18271-common.c
273
return __tda18271_charge_pump_source(fe, pll, force, true);
drivers/media/tuners/tda18271-priv.h
204
enum tda18271_pll pll, int force);
drivers/media/usb/dvb-usb/dib0700_devices.c
1199
.pll = &dib807x_bw_config_12_mhz,
drivers/media/usb/dvb-usb/dib0700_devices.c
1216
.pll = &dib807x_bw_config_12_mhz,
drivers/media/usb/dvb-usb/dib0700_devices.c
1560
.pll = &dib8090_pll_config_12mhz,
drivers/media/usb/dvb-usb/dib0700_devices.c
1579
.pll = &dib8090_pll_config_12mhz,
drivers/media/usb/dvb-usb/dib0700_devices.c
1976
.pll = &dib8096p_clock_config_12_mhz,
drivers/media/usb/dvb-usb/dib0700_devices.c
2109
struct dibx000_bandwidth_config pll;
drivers/media/usb/dvb-usb/dib0700_devices.c
2117
memset(&pll, 0, sizeof(struct dibx000_bandwidth_config));
drivers/media/usb/dvb-usb/dib0700_devices.c
2126
pll.pll_ratio = adc.pll_loopdiv;
drivers/media/usb/dvb-usb/dib0700_devices.c
2127
pll.pll_prediv = adc.pll_prediv;
drivers/media/usb/dvb-usb/dib0700_devices.c
2130
state->dib8000_ops.update_pll(fe, &pll, fe->dtv_property_cache.bandwidth_hz / 1000, 0);
drivers/media/usb/dvb-usb/dib0700_devices.c
2635
struct dibx000_bandwidth_config pll;
drivers/media/usb/dvb-usb/dib0700_devices.c
2644
memset(&pll, 0, sizeof(struct dibx000_bandwidth_config));
drivers/media/usb/dvb-usb/dib0700_devices.c
2650
pll.pll_ratio = adc.pll_loopdiv;
drivers/media/usb/dvb-usb/dib0700_devices.c
2651
pll.pll_prediv = adc.pll_prediv;
drivers/media/usb/dvb-usb/dib0700_devices.c
2653
state->dib7000p_ops.update_pll(fe, &pll);
drivers/mfd/twl6040.c
323
twl6040->pll = TWL6040_SYSCLK_SEL_LPPLL;
drivers/mfd/twl6040.c
354
if (twl6040->pll == TWL6040_SYSCLK_SEL_HPPLL) {
drivers/mfd/twl6040.c
380
if (pll_id != twl6040->pll) {
drivers/mfd/twl6040.c
409
if (twl6040->pll == pll_id)
drivers/mfd/twl6040.c
475
if (pll_id != twl6040->pll)
drivers/mfd/twl6040.c
503
twl6040->pll = pll_id;
drivers/mfd/twl6040.c
514
return twl6040->pll;
drivers/mmc/host/sdhci-pci-gli.c
1115
u32 pll;
drivers/mmc/host/sdhci-pci-gli.c
1120
pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll);
drivers/mmc/host/sdhci-pci-gli.c
1122
pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING |
drivers/mmc/host/sdhci-pci-gli.c
1125
pll |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING, step) |
drivers/mmc/host/sdhci-pci-gli.c
1129
pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll);
drivers/mmc/host/sdhci-pci-gli.c
1136
u32 pll;
drivers/mmc/host/sdhci-pci-gli.c
1140
pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll);
drivers/mmc/host/sdhci-pci-gli.c
1141
pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV |
drivers/mmc/host/sdhci-pci-gli.c
1144
pll |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV, ldiv) |
drivers/mmc/host/sdhci-pci-gli.c
1147
pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll);
drivers/mmc/host/sdhci-pci-gli.c
1166
u32 pll;
drivers/mmc/host/sdhci-pci-gli.c
1170
pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll);
drivers/mmc/host/sdhci-pci-gli.c
1171
pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN | PCIE_GLI_9767_SD_PLL_CTL_SSC_EN);
drivers/mmc/host/sdhci-pci-gli.c
1172
pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll);
drivers/mmc/host/sdhci-pci-gli.c
518
u32 pll;
drivers/mmc/host/sdhci-pci-gli.c
521
pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
drivers/mmc/host/sdhci-pci-gli.c
522
pll &= ~(SDHCI_GLI_9750_PLL_DIR | SDHCI_GLI_9750_PLLSSC_EN);
drivers/mmc/host/sdhci-pci-gli.c
523
sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
drivers/mmc/host/sdhci-pci-gli.c
529
u32 pll;
drivers/mmc/host/sdhci-pci-gli.c
532
pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
drivers/mmc/host/sdhci-pci-gli.c
533
pll &= ~(SDHCI_GLI_9750_PLL_LDIV |
drivers/mmc/host/sdhci-pci-gli.c
536
pll |= FIELD_PREP(SDHCI_GLI_9750_PLL_LDIV, ldiv) |
drivers/mmc/host/sdhci-pci-gli.c
539
sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
drivers/mmc/host/sdhci-pci-gli.c
561
u32 pll;
drivers/mmc/host/sdhci-pci-gli.c
565
pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
drivers/mmc/host/sdhci-pci-gli.c
567
pll &= ~(SDHCI_GLI_9750_PLLSSC_STEP |
drivers/mmc/host/sdhci-pci-gli.c
570
pll |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_STEP, step) |
drivers/mmc/host/sdhci-pci-gli.c
574
sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
drivers/mmc/host/sdhci-pci-gli.c
709
u32 pll;
drivers/mmc/host/sdhci-pci-gli.c
712
pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
drivers/mmc/host/sdhci-pci-gli.c
713
pll &= ~(PCI_GLI_9755_PLL_DIR | PCI_GLI_9755_PLLSSC_EN);
drivers/mmc/host/sdhci-pci-gli.c
714
pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
drivers/mmc/host/sdhci-pci-gli.c
720
u32 pll;
drivers/mmc/host/sdhci-pci-gli.c
723
pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
drivers/mmc/host/sdhci-pci-gli.c
724
pll &= ~(PCI_GLI_9755_PLL_LDIV |
drivers/mmc/host/sdhci-pci-gli.c
727
pll |= FIELD_PREP(PCI_GLI_9755_PLL_LDIV, ldiv) |
drivers/mmc/host/sdhci-pci-gli.c
730
pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
drivers/mmc/host/sdhci-pci-gli.c
752
u32 pll;
drivers/mmc/host/sdhci-pci-gli.c
756
pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
drivers/mmc/host/sdhci-pci-gli.c
758
pll &= ~(PCI_GLI_9755_PLLSSC_STEP |
drivers/mmc/host/sdhci-pci-gli.c
761
pll |= FIELD_PREP(PCI_GLI_9755_PLLSSC_STEP, step) |
drivers/mmc/host/sdhci-pci-gli.c
765
pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
drivers/net/dsa/sja1105/sja1105_clocking.c
691
struct sja1105_cgu_pll_ctrl pll = {0};
drivers/net/dsa/sja1105/sja1105_clocking.c
705
pll.pllclksrc = 0xA;
drivers/net/dsa/sja1105/sja1105_clocking.c
706
pll.msel = 0x1;
drivers/net/dsa/sja1105/sja1105_clocking.c
707
pll.autoblock = 0x1;
drivers/net/dsa/sja1105/sja1105_clocking.c
708
pll.psel = 0x1;
drivers/net/dsa/sja1105/sja1105_clocking.c
709
pll.direct = 0x0;
drivers/net/dsa/sja1105/sja1105_clocking.c
710
pll.fbsel = 0x1;
drivers/net/dsa/sja1105/sja1105_clocking.c
711
pll.bypass = 0x0;
drivers/net/dsa/sja1105/sja1105_clocking.c
712
pll.pd = 0x1;
drivers/net/dsa/sja1105/sja1105_clocking.c
714
sja1105_cgu_pll_control_packing(packed_buf, &pll, PACK);
drivers/net/dsa/sja1105/sja1105_clocking.c
723
pll.pd = 0x0;
drivers/net/dsa/sja1105/sja1105_clocking.c
725
sja1105_cgu_pll_control_packing(packed_buf, &pll, PACK);
drivers/net/mdio/mdio-mux-meson-g12a.c
100
return readl_poll_timeout(pll->base + ETH_PLL_CTL0, val,
drivers/net/mdio/mdio-mux-meson-g12a.c
106
struct g12a_ephy_pll *pll = g12a_ephy_pll_to_dev(hw);
drivers/net/mdio/mdio-mux-meson-g12a.c
109
val = readl(pll->base + ETH_PLL_CTL0);
drivers/net/mdio/mdio-mux-meson-g12a.c
112
writel(val, pll->base + ETH_PLL_CTL0);
drivers/net/mdio/mdio-mux-meson-g12a.c
117
struct g12a_ephy_pll *pll = g12a_ephy_pll_to_dev(hw);
drivers/net/mdio/mdio-mux-meson-g12a.c
120
val = readl(pll->base + ETH_PLL_CTL0);
drivers/net/mdio/mdio-mux-meson-g12a.c
127
struct g12a_ephy_pll *pll = g12a_ephy_pll_to_dev(hw);
drivers/net/mdio/mdio-mux-meson-g12a.c
130
writel(0x29c0040a, pll->base + ETH_PLL_CTL0);
drivers/net/mdio/mdio-mux-meson-g12a.c
131
writel(0x927e0000, pll->base + ETH_PLL_CTL1);
drivers/net/mdio/mdio-mux-meson-g12a.c
132
writel(0xac5f49e5, pll->base + ETH_PLL_CTL2);
drivers/net/mdio/mdio-mux-meson-g12a.c
133
writel(0x00000000, pll->base + ETH_PLL_CTL3);
drivers/net/mdio/mdio-mux-meson-g12a.c
134
writel(0x00000000, pll->base + ETH_PLL_CTL4);
drivers/net/mdio/mdio-mux-meson-g12a.c
135
writel(0x20200000, pll->base + ETH_PLL_CTL5);
drivers/net/mdio/mdio-mux-meson-g12a.c
136
writel(0x0000c002, pll->base + ETH_PLL_CTL6);
drivers/net/mdio/mdio-mux-meson-g12a.c
137
writel(0x00000023, pll->base + ETH_PLL_CTL7);
drivers/net/mdio/mdio-mux-meson-g12a.c
156
if (!__clk_is_enabled(priv->pll)) {
drivers/net/mdio/mdio-mux-meson-g12a.c
157
ret = clk_prepare_enable(priv->pll);
drivers/net/mdio/mdio-mux-meson-g12a.c
192
if (__clk_is_enabled(priv->pll))
drivers/net/mdio/mdio-mux-meson-g12a.c
193
clk_disable_unprepare(priv->pll);
drivers/net/mdio/mdio-mux-meson-g12a.c
227
struct g12a_ephy_pll *pll;
drivers/net/mdio/mdio-mux-meson-g12a.c
274
pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL);
drivers/net/mdio/mdio-mux-meson-g12a.c
275
if (!pll)
drivers/net/mdio/mdio-mux-meson-g12a.c
289
pll->base = priv->regs;
drivers/net/mdio/mdio-mux-meson-g12a.c
290
pll->hw.init = &init;
drivers/net/mdio/mdio-mux-meson-g12a.c
292
clk = devm_clk_register(dev, &pll->hw);
drivers/net/mdio/mdio-mux-meson-g12a.c
299
priv->pll = clk;
drivers/net/mdio/mdio-mux-meson-g12a.c
345
if (__clk_is_enabled(priv->pll))
drivers/net/mdio/mdio-mux-meson-g12a.c
346
clk_disable_unprepare(priv->pll);
drivers/net/mdio/mdio-mux-meson-g12a.c
58
struct clk *pll;
drivers/net/mdio/mdio-mux-meson-g12a.c
72
struct g12a_ephy_pll *pll = g12a_ephy_pll_to_dev(hw);
drivers/net/mdio/mdio-mux-meson-g12a.c
75
val = readl(pll->base + ETH_PLL_CTL0);
drivers/net/mdio/mdio-mux-meson-g12a.c
84
struct g12a_ephy_pll *pll = g12a_ephy_pll_to_dev(hw);
drivers/net/mdio/mdio-mux-meson-g12a.c
85
u32 val = readl(pll->base + ETH_PLL_CTL0);
drivers/net/mdio/mdio-mux-meson-g12a.c
89
writel(val, pll->base + ETH_PLL_CTL0);
drivers/net/mdio/mdio-mux-meson-g12a.c
93
writel(val, pll->base + ETH_PLL_CTL0);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
916
u32 pll;
drivers/net/wireless/ath/ath9k/ar5008_phy.c
918
pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
921
pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
923
pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
926
pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
928
pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
930
return pll;
drivers/net/wireless/ath/ath9k/ar5008_phy.c
936
u32 pll;
drivers/net/wireless/ath/ath9k/ar5008_phy.c
938
pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
drivers/net/wireless/ath/ath9k/ar5008_phy.c
941
pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
943
pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
946
pll |= SM(0xa, AR_RTC_PLL_DIV);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
948
pll |= SM(0xb, AR_RTC_PLL_DIV);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
950
return pll;
drivers/net/wireless/ath/ath9k/ar9002_phy.c
309
u32 pll;
drivers/net/wireless/ath/ath9k/ar9002_phy.c
320
pll = SM(ref_div, AR_RTC_9160_PLL_REFDIV);
drivers/net/wireless/ath/ath9k/ar9002_phy.c
321
pll |= SM(pll_div, AR_RTC_9160_PLL_DIV);
drivers/net/wireless/ath/ath9k/ar9002_phy.c
324
pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
drivers/net/wireless/ath/ath9k/ar9002_phy.c
326
pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
drivers/net/wireless/ath/ath9k/ar9002_phy.c
328
return pll;
drivers/net/wireless/ath/ath9k/ar9003_phy.c
579
u32 pll;
drivers/net/wireless/ath/ath9k/ar9003_phy.c
581
pll = SM(0x5, AR_RTC_9300_SOC_PLL_REFDIV);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
584
pll |= SM(0x1, AR_RTC_9300_SOC_PLL_CLKSEL);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
586
pll |= SM(0x2, AR_RTC_9300_SOC_PLL_CLKSEL);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
588
pll |= SM(0x2c, AR_RTC_9300_SOC_PLL_DIV_INT);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
590
return pll;
drivers/net/wireless/ath/ath9k/ar9003_phy.c
596
u32 pll;
drivers/net/wireless/ath/ath9k/ar9003_phy.c
598
pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
601
pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
603
pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
605
pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
607
return pll;
drivers/net/wireless/ath/ath9k/hw.c
764
u32 pll;
drivers/net/wireless/ath/ath9k/hw.c
766
pll = ath9k_hw_compute_pll_control(ah, chan);
drivers/net/wireless/ath/ath9k/hw.c
819
pll | AR_RTC_9300_PLL_BYPASS);
drivers/net/wireless/ath/ath9k/hw.c
837
pll | AR_RTC_9300_SOC_PLL_BYPASS);
drivers/net/wireless/ath/ath9k/hw.c
914
pll |= 0x40000;
drivers/net/wireless/ath/ath9k/hw.c
915
REG_WRITE(ah, AR_RTC_PLL_CONTROL(ah), pll);
drivers/pci/controller/pcie-brcmstb.c
441
int pll, ssc;
drivers/pci/controller/pcie-brcmstb.c
469
pll = FIELD_GET(SSC_STATUS_PLL_LOCK_MASK, tmp);
drivers/pci/controller/pcie-brcmstb.c
471
return ssc && pll ? 0 : -EIO;
drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
265
bool pll = false;
drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
270
pll = true;
drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
281
pll ? 0 : HSIO_IOB_RXENA);
drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
283
pll ? HSIO_IOB_TXENA : 0);
drivers/phy/freescale/phy-fsl-lynx-10g.c
295
static void lynx_10g_pll_read_configuration(struct lynx_pll *pll)
drivers/phy/freescale/phy-fsl-lynx-10g.c
299
val = lynx_pll_read(pll, PLLnCR0);
drivers/phy/freescale/phy-fsl-lynx-10g.c
300
pll->frate_sel = FIELD_GET(PLLnCR0_FRATE_SEL, val);
drivers/phy/freescale/phy-fsl-lynx-10g.c
301
pll->refclk_sel = FIELD_GET(PLLnCR0_REFCLK_SEL, val);
drivers/phy/freescale/phy-fsl-lynx-10g.c
302
pll->enabled = !(val & PLLnCR0_POFF);
drivers/phy/freescale/phy-fsl-lynx-10g.c
303
pll->locked = !!(val & PLLnCR0_PLL_LCK);
drivers/phy/freescale/phy-fsl-lynx-10g.c
305
if (!pll->enabled)
drivers/phy/freescale/phy-fsl-lynx-10g.c
308
switch (pll->frate_sel) {
drivers/phy/freescale/phy-fsl-lynx-10g.c
311
__set_bit(LANE_MODE_1000BASEX_SGMII, pll->supported);
drivers/phy/freescale/phy-fsl-lynx-10g.c
312
__set_bit(LANE_MODE_QSGMII, pll->supported);
drivers/phy/freescale/phy-fsl-lynx-10g.c
315
__set_bit(LANE_MODE_2500BASEX, pll->supported);
drivers/phy/freescale/phy-fsl-lynx-10g.c
319
__set_bit(LANE_MODE_10GBASER, pll->supported);
drivers/phy/freescale/phy-fsl-lynx-10g.c
320
__set_bit(LANE_MODE_USXGMII, pll->supported);
drivers/phy/freescale/phy-fsl-lynx-10g.c
321
__set_bit(LANE_MODE_10G_QXGMII, pll->supported);
drivers/phy/freescale/phy-fsl-lynx-10g.c
395
struct lynx_pll *pll;
drivers/phy/freescale/phy-fsl-lynx-10g.c
401
pll = &priv->pll[0];
drivers/phy/freescale/phy-fsl-lynx-10g.c
403
pll = &priv->pll[1];
drivers/phy/freescale/phy-fsl-lynx-10g.c
405
if (pll->frate_sel != PLLnCR0_FRATE_3_125G)
drivers/phy/freescale/phy-fsl-lynx-10g.c
64
#define PLLnCR0(pll) ((pll) * 0x20 + 0x4)
drivers/phy/freescale/phy-fsl-lynx-10g.c
914
struct lynx_pll *pll,
drivers/phy/freescale/phy-fsl-lynx-10g.c
919
switch (pll->frate_sel) {
drivers/phy/freescale/phy-fsl-lynx-10g.c
963
struct lynx_pll *pll)
drivers/phy/freescale/phy-fsl-lynx-10g.c
965
if (pll->id == 0) {
drivers/phy/freescale/phy-fsl-lynx-10g.c
980
struct lynx_pll *pll;
drivers/phy/freescale/phy-fsl-lynx-10g.c
983
pll = lynx_pll_get(priv, lane_mode);
drivers/phy/freescale/phy-fsl-lynx-10g.c
984
if (unlikely(!pll))
drivers/phy/freescale/phy-fsl-lynx-10g.c
987
lynx_10g_lane_set_pll(lane, pll);
drivers/phy/freescale/phy-fsl-lynx-10g.c
990
lynx_10g_lane_set_nrate(lane, pll, lane_mode);
drivers/phy/freescale/phy-fsl-lynx-28g.c
1060
static void lynx_28g_pll_read_configuration(struct lynx_pll *pll)
drivers/phy/freescale/phy-fsl-lynx-28g.c
1064
val = lynx_pll_read(pll, PLLnRSTCTL);
drivers/phy/freescale/phy-fsl-lynx-28g.c
1065
pll->enabled = !(val & PLLnRSTCTL_DIS);
drivers/phy/freescale/phy-fsl-lynx-28g.c
1066
pll->locked = !!(val & PLLnRSTCTL_LOCK);
drivers/phy/freescale/phy-fsl-lynx-28g.c
1068
val = lynx_pll_read(pll, PLLnCR0);
drivers/phy/freescale/phy-fsl-lynx-28g.c
1069
pll->refclk_sel = FIELD_GET(PLLnCR0_REFCLK_SEL, val);
drivers/phy/freescale/phy-fsl-lynx-28g.c
1071
val = lynx_pll_read(pll, PLLnCR1);
drivers/phy/freescale/phy-fsl-lynx-28g.c
1072
pll->frate_sel = FIELD_GET(PLLnCR1_FRATE_SEL, val);
drivers/phy/freescale/phy-fsl-lynx-28g.c
1074
if (!pll->enabled)
drivers/phy/freescale/phy-fsl-lynx-28g.c
1077
switch (pll->frate_sel) {
drivers/phy/freescale/phy-fsl-lynx-28g.c
1081
__set_bit(LANE_MODE_1000BASEX_SGMII, pll->supported);
drivers/phy/freescale/phy-fsl-lynx-28g.c
1085
__set_bit(LANE_MODE_10GBASER, pll->supported);
drivers/phy/freescale/phy-fsl-lynx-28g.c
1086
__set_bit(LANE_MODE_USXGMII, pll->supported);
drivers/phy/freescale/phy-fsl-lynx-28g.c
1090
__set_bit(LANE_MODE_25GBASER, pll->supported);
drivers/phy/freescale/phy-fsl-lynx-28g.c
44
#define PLLnRSTCTL(pll) (0x400 + (pll) * 0x100 + 0x0)
drivers/phy/freescale/phy-fsl-lynx-28g.c
467
struct lynx_28g_pll *pll,
drivers/phy/freescale/phy-fsl-lynx-28g.c
470
switch (pll->frate_sel) {
drivers/phy/freescale/phy-fsl-lynx-28g.c
48
#define PLLnCR0(pll) (0x400 + (pll) * 0x100 + 0x4)
drivers/phy/freescale/phy-fsl-lynx-28g.c
521
struct lynx_28g_pll *pll)
drivers/phy/freescale/phy-fsl-lynx-28g.c
523
if (pll->id == 0) {
drivers/phy/freescale/phy-fsl-lynx-28g.c
56
#define PLLnCR1(pll) (0x400 + (pll) * 0x100 + 0x8)
drivers/phy/freescale/phy-fsl-lynx-28g.c
811
struct lynx_pll *pll;
drivers/phy/freescale/phy-fsl-lynx-28g.c
814
pll = lynx_pll_get(priv, lane_mode);
drivers/phy/freescale/phy-fsl-lynx-28g.c
815
if (unlikely(!pll))
drivers/phy/freescale/phy-fsl-lynx-28g.c
818
lynx_28g_lane_set_pll(lane, pll);
drivers/phy/freescale/phy-fsl-lynx-28g.c
821
lynx_28g_lane_set_nrate(lane, pll, lane_mode);
drivers/phy/freescale/phy-fsl-lynx-core.c
162
struct lynx_pll *pll;
drivers/phy/freescale/phy-fsl-lynx-core.c
166
pll = &priv->pll[i];
drivers/phy/freescale/phy-fsl-lynx-core.c
168
if (!pll->enabled)
drivers/phy/freescale/phy-fsl-lynx-core.c
171
if (test_bit(mode, pll->supported))
drivers/phy/freescale/phy-fsl-lynx-core.c
172
return pll;
drivers/phy/freescale/phy-fsl-lynx-core.c
381
struct lynx_pll *pll = &priv->pll[i];
drivers/phy/freescale/phy-fsl-lynx-core.c
383
pll->priv = priv;
drivers/phy/freescale/phy-fsl-lynx-core.c
384
pll->id = i;
drivers/phy/freescale/phy-fsl-lynx-core.c
385
priv->info->pll_read_configuration(pll);
drivers/phy/freescale/phy-fsl-lynx-core.c
93
if (!priv->pll[i].enabled)
drivers/phy/freescale/phy-fsl-lynx-core.c
96
if (test_bit(mode, priv->pll[i].supported))
drivers/phy/freescale/phy-fsl-lynx-core.h
110
#define lynx_pll_read(pll, reg) \
drivers/phy/freescale/phy-fsl-lynx-core.h
111
lynx_read((pll)->priv, reg((pll)->id))
drivers/phy/freescale/phy-fsl-lynx-core.h
48
void (*pll_read_configuration)(struct lynx_pll *pll);
drivers/phy/freescale/phy-fsl-lynx-core.h
66
struct lynx_pll pll[LYNX_NUM_PLL];
drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
473
ret = clk_set_rate(hdmi_phy->pll, dp_opts->link_rate);
drivers/phy/mediatek/phy-mtk-hdmi.c
140
hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw);
drivers/phy/mediatek/phy-mtk-hdmi.c
141
if (IS_ERR(hdmi_phy->pll))
drivers/phy/mediatek/phy-mtk-hdmi.c
142
return dev_err_probe(dev, PTR_ERR(hdmi_phy->pll),
drivers/phy/mediatek/phy-mtk-hdmi.c
182
hdmi_phy->pll);
drivers/phy/mediatek/phy-mtk-hdmi.c
30
ret = clk_prepare_enable(hdmi_phy->pll);
drivers/phy/mediatek/phy-mtk-hdmi.c
43
clk_disable_unprepare(hdmi_phy->pll);
drivers/phy/mediatek/phy-mtk-hdmi.h
36
struct clk *pll;
drivers/phy/qualcomm/phy-qcom-edp.c
1000
writel(0x0c, edp->pll + DP_QSERDES_V8_COM_CLK_ENABLE1);
drivers/phy/qualcomm/phy-qcom-edp.c
1001
writel(0x06, edp->pll + DP_QSERDES_V8_COM_SYSCLK_BUF_ENABLE);
drivers/phy/qualcomm/phy-qcom-edp.c
1002
writel(0x30, edp->pll + DP_QSERDES_V8_COM_CLK_SELECT);
drivers/phy/qualcomm/phy-qcom-edp.c
1003
writel(hsclk_sel, edp->pll + DP_QSERDES_V8_COM_HSCLK_SEL_1);
drivers/phy/qualcomm/phy-qcom-edp.c
1004
writel(0x07, edp->pll + DP_QSERDES_V8_COM_PLL_IVCO);
drivers/phy/qualcomm/phy-qcom-edp.c
1005
writel(0x00, edp->pll + DP_QSERDES_V8_COM_LOCK_CMP_EN);
drivers/phy/qualcomm/phy-qcom-edp.c
1006
writel(0x36, edp->pll + DP_QSERDES_V8_COM_PLL_CCTRL_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
1007
writel(0x16, edp->pll + DP_QSERDES_V8_COM_PLL_RCTRL_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
1008
writel(0x06, edp->pll + DP_QSERDES_V8_COM_CP_CTRL_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
1009
writel(dec_start_mode0, edp->pll + DP_QSERDES_V8_COM_DEC_START_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
1010
writel(0x00, edp->pll + DP_QSERDES_V8_COM_DIV_FRAC_START1_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
1011
writel(div_frac_start2_mode0, edp->pll + DP_QSERDES_V8_COM_DIV_FRAC_START2_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
1012
writel(div_frac_start3_mode0, edp->pll + DP_QSERDES_V8_COM_DIV_FRAC_START3_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
1013
writel(0x96, edp->pll + DP_QSERDES_V8_COM_CMN_CONFIG_1);
drivers/phy/qualcomm/phy-qcom-edp.c
1014
writel(0x3f, edp->pll + DP_QSERDES_V8_COM_INTEGLOOP_GAIN0_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
1015
writel(0x00, edp->pll + DP_QSERDES_V8_COM_INTEGLOOP_GAIN1_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
1016
writel(0x00, edp->pll + DP_QSERDES_V8_COM_VCO_TUNE_MAP);
drivers/phy/qualcomm/phy-qcom-edp.c
1017
writel(lock_cmp1_mode0, edp->pll + DP_QSERDES_V8_COM_LOCK_CMP1_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
1018
writel(lock_cmp2_mode0, edp->pll + DP_QSERDES_V8_COM_LOCK_CMP2_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
1020
writel(0x0a, edp->pll + DP_QSERDES_V8_COM_BG_TIMER);
drivers/phy/qualcomm/phy-qcom-edp.c
1021
writel(0x0a, edp->pll + DP_QSERDES_V8_COM_CORECLK_DIV_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
1022
writel(0x00, edp->pll + DP_QSERDES_V8_COM_VCO_TUNE_CTRL);
drivers/phy/qualcomm/phy-qcom-edp.c
1023
writel(0x1f, edp->pll + DP_QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN);
drivers/phy/qualcomm/phy-qcom-edp.c
1024
writel(0x00, edp->pll + DP_QSERDES_V8_COM_CORE_CLK_EN);
drivers/phy/qualcomm/phy-qcom-edp.c
1025
writel(0xa0, edp->pll + DP_QSERDES_V8_COM_VCO_TUNE1_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
1026
writel(0x01, edp->pll + DP_QSERDES_V8_COM_VCO_TUNE2_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
1028
writel(code1_mode0, edp->pll + DP_QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
1029
writel(code2_mode0, edp->pll + DP_QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
1039
writel(0x20, edp->pll + DP_QSERDES_V8_COM_RESETSM_CNTRL);
drivers/phy/qualcomm/phy-qcom-edp.c
1041
return readl_poll_timeout(edp->pll + DP_QSERDES_V8_COM_C_READY_STATUS,
drivers/phy/qualcomm/phy-qcom-edp.c
1047
writel(0x3f, edp->pll + DP_QSERDES_V8_COM_CLK_FWD_CONFIG_1);
drivers/phy/qualcomm/phy-qcom-edp.c
105
void __iomem *pll;
drivers/phy/qualcomm/phy-qcom-edp.c
1055
writel(0x1f, edp->pll + DP_QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN);
drivers/phy/qualcomm/phy-qcom-edp.c
1070
return readl_poll_timeout(edp->pll + DP_QSERDES_V8_COM_CMN_STATUS,
drivers/phy/qualcomm/phy-qcom-edp.c
1442
edp->pll = devm_platform_ioremap_resource(pdev, 3);
drivers/phy/qualcomm/phy-qcom-edp.c
1443
if (IS_ERR(edp->pll))
drivers/phy/qualcomm/phy-qcom-edp.c
1444
return PTR_ERR(edp->pll);
drivers/phy/qualcomm/phy-qcom-edp.c
465
return readl_poll_timeout(edp->pll + QSERDES_V4_COM_CMN_STATUS,
drivers/phy/qualcomm/phy-qcom-edp.c
473
writel(0x20, edp->pll + QSERDES_V4_COM_RESETSM_CNTRL);
drivers/phy/qualcomm/phy-qcom-edp.c
475
return readl_poll_timeout(edp->pll + QSERDES_V4_COM_C_READY_STATUS,
drivers/phy/qualcomm/phy-qcom-edp.c
487
writel(0x17, edp->pll + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
drivers/phy/qualcomm/phy-qcom-edp.c
516
writel(0x01, edp->pll + QSERDES_V4_COM_SSC_EN_CENTER);
drivers/phy/qualcomm/phy-qcom-edp.c
517
writel(0x00, edp->pll + QSERDES_V4_COM_SSC_ADJ_PER1);
drivers/phy/qualcomm/phy-qcom-edp.c
518
writel(0x36, edp->pll + QSERDES_V4_COM_SSC_PER1);
drivers/phy/qualcomm/phy-qcom-edp.c
519
writel(0x01, edp->pll + QSERDES_V4_COM_SSC_PER2);
drivers/phy/qualcomm/phy-qcom-edp.c
520
writel(step1, edp->pll + QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
521
writel(step2, edp->pll + QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
578
writel(0x01, edp->pll + QSERDES_V4_COM_SVS_MODE_CLK_SEL);
drivers/phy/qualcomm/phy-qcom-edp.c
579
writel(0x0b, edp->pll + QSERDES_V4_COM_SYSCLK_EN_SEL);
drivers/phy/qualcomm/phy-qcom-edp.c
580
writel(0x02, edp->pll + QSERDES_V4_COM_SYS_CLK_CTRL);
drivers/phy/qualcomm/phy-qcom-edp.c
581
writel(0x0c, edp->pll + QSERDES_V4_COM_CLK_ENABLE1);
drivers/phy/qualcomm/phy-qcom-edp.c
582
writel(0x06, edp->pll + QSERDES_V4_COM_SYSCLK_BUF_ENABLE);
drivers/phy/qualcomm/phy-qcom-edp.c
583
writel(0x30, edp->pll + QSERDES_V4_COM_CLK_SELECT);
drivers/phy/qualcomm/phy-qcom-edp.c
584
writel(hsclk_sel, edp->pll + QSERDES_V4_COM_HSCLK_SEL);
drivers/phy/qualcomm/phy-qcom-edp.c
585
writel(0x0f, edp->pll + QSERDES_V4_COM_PLL_IVCO);
drivers/phy/qualcomm/phy-qcom-edp.c
586
writel(0x08, edp->pll + QSERDES_V4_COM_LOCK_CMP_EN);
drivers/phy/qualcomm/phy-qcom-edp.c
587
writel(0x36, edp->pll + QSERDES_V4_COM_PLL_CCTRL_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
588
writel(0x16, edp->pll + QSERDES_V4_COM_PLL_RCTRL_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
589
writel(0x06, edp->pll + QSERDES_V4_COM_CP_CTRL_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
590
writel(dec_start_mode0, edp->pll + QSERDES_V4_COM_DEC_START_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
591
writel(0x00, edp->pll + QSERDES_V4_COM_DIV_FRAC_START1_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
592
writel(div_frac_start2_mode0, edp->pll + QSERDES_V4_COM_DIV_FRAC_START2_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
593
writel(div_frac_start3_mode0, edp->pll + QSERDES_V4_COM_DIV_FRAC_START3_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
594
writel(0x02, edp->pll + QSERDES_V4_COM_CMN_CONFIG);
drivers/phy/qualcomm/phy-qcom-edp.c
595
writel(0x3f, edp->pll + QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
596
writel(0x00, edp->pll + QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
597
writel(0x00, edp->pll + QSERDES_V4_COM_VCO_TUNE_MAP);
drivers/phy/qualcomm/phy-qcom-edp.c
598
writel(lock_cmp1_mode0, edp->pll + QSERDES_V4_COM_LOCK_CMP1_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
599
writel(lock_cmp2_mode0, edp->pll + QSERDES_V4_COM_LOCK_CMP2_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
601
writel(0x0a, edp->pll + QSERDES_V4_COM_BG_TIMER);
drivers/phy/qualcomm/phy-qcom-edp.c
602
writel(0x14, edp->pll + QSERDES_V4_COM_CORECLK_DIV_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
603
writel(0x00, edp->pll + QSERDES_V4_COM_VCO_TUNE_CTRL);
drivers/phy/qualcomm/phy-qcom-edp.c
604
writel(0x17, edp->pll + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
drivers/phy/qualcomm/phy-qcom-edp.c
605
writel(0x0f, edp->pll + QSERDES_V4_COM_CORE_CLK_EN);
drivers/phy/qualcomm/phy-qcom-edp.c
606
writel(0xa0, edp->pll + QSERDES_V4_COM_VCO_TUNE1_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
607
writel(0x03, edp->pll + QSERDES_V4_COM_VCO_TUNE2_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
720
return readl_poll_timeout(edp->pll + QSERDES_V6_COM_CMN_STATUS,
drivers/phy/qualcomm/phy-qcom-edp.c
728
writel(0x20, edp->pll + QSERDES_V6_COM_RESETSM_CNTRL);
drivers/phy/qualcomm/phy-qcom-edp.c
730
return readl_poll_timeout(edp->pll + QSERDES_V6_COM_C_READY_STATUS,
drivers/phy/qualcomm/phy-qcom-edp.c
737
writel(0x1f, edp->pll + QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN);
drivers/phy/qualcomm/phy-qcom-edp.c
766
writel(0x01, edp->pll + QSERDES_V6_COM_SSC_EN_CENTER);
drivers/phy/qualcomm/phy-qcom-edp.c
767
writel(0x00, edp->pll + QSERDES_V6_COM_SSC_ADJ_PER1);
drivers/phy/qualcomm/phy-qcom-edp.c
768
writel(0x36, edp->pll + QSERDES_V6_COM_SSC_PER1);
drivers/phy/qualcomm/phy-qcom-edp.c
769
writel(0x01, edp->pll + QSERDES_V6_COM_SSC_PER2);
drivers/phy/qualcomm/phy-qcom-edp.c
770
writel(step1, edp->pll + QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
771
writel(step2, edp->pll + QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
838
writel(0x01, edp->pll + QSERDES_V6_COM_SVS_MODE_CLK_SEL);
drivers/phy/qualcomm/phy-qcom-edp.c
839
writel(0x0b, edp->pll + QSERDES_V6_COM_SYSCLK_EN_SEL);
drivers/phy/qualcomm/phy-qcom-edp.c
840
writel(0x02, edp->pll + QSERDES_V6_COM_SYS_CLK_CTRL);
drivers/phy/qualcomm/phy-qcom-edp.c
841
writel(0x0c, edp->pll + QSERDES_V6_COM_CLK_ENABLE1);
drivers/phy/qualcomm/phy-qcom-edp.c
842
writel(0x06, edp->pll + QSERDES_V6_COM_SYSCLK_BUF_ENABLE);
drivers/phy/qualcomm/phy-qcom-edp.c
843
writel(0x30, edp->pll + QSERDES_V6_COM_CLK_SELECT);
drivers/phy/qualcomm/phy-qcom-edp.c
844
writel(hsclk_sel, edp->pll + QSERDES_V6_COM_HSCLK_SEL_1);
drivers/phy/qualcomm/phy-qcom-edp.c
845
writel(0x07, edp->pll + QSERDES_V6_COM_PLL_IVCO);
drivers/phy/qualcomm/phy-qcom-edp.c
846
writel(0x08, edp->pll + QSERDES_V6_COM_LOCK_CMP_EN);
drivers/phy/qualcomm/phy-qcom-edp.c
847
writel(0x36, edp->pll + QSERDES_V6_COM_PLL_CCTRL_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
848
writel(0x16, edp->pll + QSERDES_V6_COM_PLL_RCTRL_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
849
writel(0x06, edp->pll + QSERDES_V6_COM_CP_CTRL_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
850
writel(dec_start_mode0, edp->pll + QSERDES_V6_COM_DEC_START_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
851
writel(0x00, edp->pll + QSERDES_V6_COM_DIV_FRAC_START1_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
852
writel(div_frac_start2_mode0, edp->pll + QSERDES_V6_COM_DIV_FRAC_START2_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
853
writel(div_frac_start3_mode0, edp->pll + QSERDES_V6_COM_DIV_FRAC_START3_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
854
writel(0x12, edp->pll + QSERDES_V6_COM_CMN_CONFIG_1);
drivers/phy/qualcomm/phy-qcom-edp.c
855
writel(0x3f, edp->pll + QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
856
writel(0x00, edp->pll + QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
857
writel(0x00, edp->pll + QSERDES_V6_COM_VCO_TUNE_MAP);
drivers/phy/qualcomm/phy-qcom-edp.c
858
writel(lock_cmp1_mode0, edp->pll + QSERDES_V6_COM_LOCK_CMP1_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
859
writel(lock_cmp2_mode0, edp->pll + QSERDES_V6_COM_LOCK_CMP2_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
861
writel(0x0a, edp->pll + QSERDES_V6_COM_BG_TIMER);
drivers/phy/qualcomm/phy-qcom-edp.c
862
writel(0x14, edp->pll + QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
863
writel(0x00, edp->pll + QSERDES_V6_COM_VCO_TUNE_CTRL);
drivers/phy/qualcomm/phy-qcom-edp.c
864
writel(0x1f, edp->pll + QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN);
drivers/phy/qualcomm/phy-qcom-edp.c
865
writel(0x0f, edp->pll + QSERDES_V6_COM_CORE_CLK_EN);
drivers/phy/qualcomm/phy-qcom-edp.c
866
writel(0xa0, edp->pll + QSERDES_V6_COM_VCO_TUNE1_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
867
writel(0x03, edp->pll + QSERDES_V6_COM_VCO_TUNE2_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
869
writel(code1_mode0, edp->pll + QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
870
writel(code2_mode0, edp->pll + QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
935
writel(0x01, edp->pll + DP_QSERDES_V8_COM_SSC_EN_CENTER);
drivers/phy/qualcomm/phy-qcom-edp.c
936
writel(0x00, edp->pll + DP_QSERDES_V8_COM_SSC_ADJ_PER1);
drivers/phy/qualcomm/phy-qcom-edp.c
937
writel(0x6b, edp->pll + DP_QSERDES_V8_COM_SSC_PER1);
drivers/phy/qualcomm/phy-qcom-edp.c
938
writel(0x02, edp->pll + DP_QSERDES_V8_COM_SSC_PER2);
drivers/phy/qualcomm/phy-qcom-edp.c
939
writel(step1, edp->pll + DP_QSERDES_V8_COM_SSC_STEP_SIZE1_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
940
writel(step2, edp->pll + DP_QSERDES_V8_COM_SSC_STEP_SIZE2_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
997
writel(0x01, edp->pll + DP_QSERDES_V8_COM_SVS_MODE_CLK_SEL);
drivers/phy/qualcomm/phy-qcom-edp.c
998
writel(0x3b, edp->pll + DP_QSERDES_V8_COM_SYSCLK_EN_SEL);
drivers/phy/qualcomm/phy-qcom-edp.c
999
writel(0x02, edp->pll + DP_QSERDES_V8_COM_SYS_CLK_CTRL);
drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
245
} pll;
drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
398
inno->pll.prediv = best_prediv;
drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
399
inno->pll.fbdiv = best_fbdiv;
drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
400
inno->pll.rate = best_freq;
drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
426
REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv));
drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
428
REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv));
drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
430
REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv));
drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
472
txbyteclkhs = inno->pll.rate / 8;
drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
515
if (inno->pll.rate <= timings[i].rate)
drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
1055
S(samsung->pll.scaler) | P(samsung->pll.prediv));
drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
1057
if (samsung->pll.dsm < 0) {
drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
1061
dsm_tmp = abs(samsung->pll.dsm);
drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
1066
regmap_write(samsung->regmap, PLL_CON1, samsung->pll.dsm);
drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
1070
M_MASK, M(samsung->pll.fbdiv));
drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
1072
if (samsung->pll.ssc_en) {
drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
1074
MRR(samsung->pll.mrr) | MFR(samsung->pll.mfr));
drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
1108
unsigned int lane_mbps = div64_ul(samsung->pll.rate, USEC_PER_SEC);
drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
1214
unsigned int lane_hs_rate = div64_ul(samsung->pll.rate, USEC_PER_SEC);
drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
1269
unsigned int lane_hs_rate = div64_ul(samsung->pll.rate, USEC_PER_SEC);
drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
1403
u16 prediv = samsung->pll.prediv;
drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
1404
u16 fbdiv = samsung->pll.fbdiv;
drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
1464
samsung->pll.prediv = prediv;
drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
1465
samsung->pll.fbdiv = fbdiv;
drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
1466
samsung->pll.dsm = dsm;
drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
1467
samsung->pll.scaler = scaler;
drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
1468
samsung->pll.rate = fout;
drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
1478
samsung->pll.ssc_en = true;
drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
1479
samsung->pll.mfr = mfr;
drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
1480
samsung->pll.mrr = mrr;
drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
1494
opts->mipi_dphy.hs_clk_rate = samsung->pll.rate;
drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
308
} pll;
drivers/phy/spacemit/phy-k1-pcie.c
306
k1_phy->pll = devm_clk_hw_get_clk(dev, hw, "pll");
drivers/phy/spacemit/phy-k1-pcie.c
307
if (IS_ERR(k1_phy->pll))
drivers/phy/spacemit/phy-k1-pcie.c
308
return PTR_ERR(k1_phy->pll);
drivers/phy/spacemit/phy-k1-pcie.c
404
return clk_prepare_enable(k1_phy->pll);
drivers/phy/spacemit/phy-k1-pcie.c
411
clk_disable_unprepare(k1_phy->pll);
drivers/phy/spacemit/phy-k1-pcie.c
63
struct clk *pll;
drivers/phy/tegra/xusb-tegra210.c
2803
pcie->pll = devm_clk_get(&pad->dev, "pll");
drivers/phy/tegra/xusb-tegra210.c
2804
if (IS_ERR(pcie->pll)) {
drivers/phy/tegra/xusb-tegra210.c
2805
err = PTR_ERR(pcie->pll);
drivers/phy/tegra/xusb-tegra210.c
475
err = clk_prepare_enable(pcie->pll);
drivers/phy/tegra/xusb-tegra210.c
678
clk_disable_unprepare(pcie->pll);
drivers/phy/tegra/xusb-tegra210.c
699
clk_disable_unprepare(pcie->pll);
drivers/phy/tegra/xusb-tegra210.c
724
err = clk_prepare_enable(sata->pll);
drivers/phy/tegra/xusb-tegra210.c
937
clk_disable_unprepare(sata->pll);
drivers/phy/tegra/xusb-tegra210.c
958
clk_disable_unprepare(sata->pll);
drivers/phy/tegra/xusb.h
245
struct clk *pll;
drivers/phy/tegra/xusb.h
260
struct clk *pll;
drivers/pinctrl/qcom/pinctrl-shikra.c
1024
[14] = PINGROUP(14, qup0_se5, pll, tgu_ch_trigout, dac_calib, wlan, _, _, _, _, _, _),
drivers/pinctrl/qcom/pinctrl-shikra.c
1032
[22] = PINGROUP(22, qup0_se8, pll, agera_pll, pbs_out, _, _, _, _, _, _, _),
drivers/pinctrl/qcom/pinctrl-shikra.c
1055
[43] = PINGROUP(43, cci_timer, emac_mcg, pll, _, _, _, _, _, _, _, _),
drivers/pinctrl/qcom/pinctrl-shikra.c
1056
[44] = PINGROUP(44, emac_mcg, pll, _, _, _, _, _, _, _, _, _),
drivers/pinctrl/qcom/pinctrl-shikra.c
1092
[74] = PINGROUP(74, pll, _, pbs_in, phase_flag, _, _, _, _, _, _, _),
drivers/pinctrl/qcom/pinctrl-shikra.c
1094
[76] = PINGROUP(76, pll, _, _, _, _, _, _, _, _, _, _),
drivers/pinctrl/qcom/pinctrl-shikra.c
967
MSM_PIN_FUNCTION(pll),
drivers/ptp/ptp_clockmatrix.c
1171
static int set_tod_ptp_pll(struct idtcm *idtcm, u8 index, u8 pll)
drivers/ptp/ptp_clockmatrix.c
1178
if (pll >= MAX_PLL) {
drivers/ptp/ptp_clockmatrix.c
1179
dev_err(idtcm->dev, "Pll%d not supported", pll);
drivers/ptp/ptp_clockmatrix.c
1183
idtcm->channel[index].pll = pll;
drivers/ptp/ptp_clockmatrix.c
1236
i, idtcm->channel[i].pll,
drivers/ptp/ptp_clockmatrix.c
2069
switch (channel->pll) {
drivers/ptp/ptp_clockmatrix.c
2376
idtcm->channel[0].pll = DEFAULT_TOD0_PTP_PLL;
drivers/ptp/ptp_clockmatrix.c
2377
idtcm->channel[1].pll = DEFAULT_TOD1_PTP_PLL;
drivers/ptp/ptp_clockmatrix.c
2378
idtcm->channel[2].pll = DEFAULT_TOD2_PTP_PLL;
drivers/ptp/ptp_clockmatrix.c
2379
idtcm->channel[3].pll = DEFAULT_TOD3_PTP_PLL;
drivers/ptp/ptp_clockmatrix.c
490
u8 pll,
drivers/ptp/ptp_clockmatrix.c
504
switch (pll) {
drivers/ptp/ptp_clockmatrix.c
566
if (pll == 5 && qn_plus_1 != 0) {
drivers/ptp/ptp_clockmatrix.c
588
if (pll == 6 && qn_plus_1 != 0) {
drivers/ptp/ptp_clockmatrix.c
619
u8 pll;
drivers/ptp/ptp_clockmatrix.c
646
for (pll = 0; pll < 8; pll++) {
drivers/ptp/ptp_clockmatrix.c
650
if (pll < 4) {
drivers/ptp/ptp_clockmatrix.c
656
} else if (pll == 4) {
drivers/ptp/ptp_clockmatrix.c
661
} else if (pll == 5) {
drivers/ptp/ptp_clockmatrix.c
668
} else if (pll == 6) {
drivers/ptp/ptp_clockmatrix.c
675
} else if (pll == 7) {
drivers/ptp/ptp_clockmatrix.c
683
err = _sync_pll_output(idtcm, pll, channel->sync_src,
drivers/ptp/ptp_clockmatrix.h
108
u8 pll;
drivers/staging/sm750fb/ddk750_chip.c
316
struct pll_value *pll)
drivers/staging/sm750fb/ddk750_chip.c
342
input = pll->input_freq / 1000;
drivers/staging/sm750fb/ddk750_chip.c
348
if (pll->clock_type == MXCLK_PLL)
drivers/staging/sm750fb/ddk750_chip.c
370
tmp_clock = pll->input_freq * M / N / X;
drivers/staging/sm750fb/ddk750_chip.c
373
pll->M = M;
drivers/staging/sm750fb/ddk750_chip.c
374
pll->N = N;
drivers/staging/sm750fb/ddk750_chip.c
375
pll->POD = 0;
drivers/staging/sm750fb/ddk750_chip.c
377
pll->POD = d - max_OD;
drivers/staging/sm750fb/ddk750_chip.c
378
pll->OD = d - pll->POD;
drivers/staging/sm750fb/ddk750_chip.c
58
struct pll_value pll;
drivers/staging/sm750fb/ddk750_chip.c
70
pll.input_freq = DEFAULT_INPUT_CLOCK; /* Defined in CLOCK.H */
drivers/staging/sm750fb/ddk750_chip.c
71
pll.clock_type = MXCLK_PLL;
drivers/staging/sm750fb/ddk750_chip.c
80
sm750_calc_pll_value(frequency, &pll);
drivers/staging/sm750fb/ddk750_chip.c
83
poke32(MXCLK_PLL_CTRL, sm750_format_pll_reg(&pll));
drivers/staging/sm750fb/ddk750_chip.h
97
unsigned int sm750_calc_pll_value(unsigned int request, struct pll_value *pll);
drivers/staging/sm750fb/ddk750_mode.c
137
} else if (pll->clock_type == PRIMARY_PLL) {
drivers/staging/sm750fb/ddk750_mode.c
140
poke32(PANEL_PLL_CTRL, sm750_format_pll_reg(pll));
drivers/staging/sm750fb/ddk750_mode.c
208
struct pll_value pll;
drivers/staging/sm750fb/ddk750_mode.c
210
pll.input_freq = DEFAULT_INPUT_CLOCK;
drivers/staging/sm750fb/ddk750_mode.c
211
pll.clock_type = clock;
drivers/staging/sm750fb/ddk750_mode.c
213
sm750_calc_pll_value(parm->pixel_clock, &pll);
drivers/staging/sm750fb/ddk750_mode.c
219
program_mode_registers(parm, &pll);
drivers/staging/sm750fb/ddk750_mode.c
79
struct pll_value *pll)
drivers/staging/sm750fb/ddk750_mode.c
84
if (pll->clock_type == SECONDARY_PLL) {
drivers/staging/sm750fb/ddk750_mode.c
86
poke32(CRT_PLL_CTRL, sm750_format_pll_reg(pll));
drivers/video/fbdev/aty/aty128fb.c
1270
static void aty128_set_pll(struct aty128_pll *pll,
drivers/video/fbdev/aty/aty128fb.c
1294
div3 |= pll->feedback_divider;
drivers/video/fbdev/aty/aty128fb.c
1296
div3 |= post_conv[pll->post_divider] << 16;
drivers/video/fbdev/aty/aty128fb.c
1312
static int aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll,
drivers/video/fbdev/aty/aty128fb.c
1334
pll->post_divider = post_dividers[i];
drivers/video/fbdev/aty/aty128fb.c
1346
pll->feedback_divider = round_div(n, d);
drivers/video/fbdev/aty/aty128fb.c
1347
pll->vclk = vclk;
drivers/video/fbdev/aty/aty128fb.c
1350
"vclk_per: %d\n", pll->post_divider,
drivers/video/fbdev/aty/aty128fb.c
1351
pll->feedback_divider, vclk, output_freq,
drivers/video/fbdev/aty/aty128fb.c
1358
static int aty128_pll_to_var(const struct aty128_pll *pll,
drivers/video/fbdev/aty/aty128fb.c
1361
var->pixclock = 100000000 / pll->vclk;
drivers/video/fbdev/aty/aty128fb.c
1376
const struct aty128_pll *pll,
drivers/video/fbdev/aty/aty128fb.c
1391
d = pll->vclk * bpp;
drivers/video/fbdev/aty/aty128fb.c
1464
aty128_set_pll(&par->pll, par);
drivers/video/fbdev/aty/aty128fb.c
1510
struct aty128_pll pll;
drivers/video/fbdev/aty/aty128fb.c
1516
if ((err = aty128_var_to_pll(var->pixclock, &pll, par)))
drivers/video/fbdev/aty/aty128fb.c
1519
if ((err = aty128_ddafifo(&fifo_reg, &pll, crtc.depth, par)))
drivers/video/fbdev/aty/aty128fb.c
1523
par->pll = pll;
drivers/video/fbdev/aty/aty128fb.c
1539
if ((err = aty128_pll_to_var(&par->pll, var)))
drivers/video/fbdev/aty/aty128fb.c
390
struct aty128_pll pll;
drivers/video/fbdev/aty/atyfb.h
139
union aty_pll pll;
drivers/video/fbdev/aty/atyfb.h
301
const union aty_pll * pll, u32 bpp, u32 accel);
drivers/video/fbdev/aty/atyfb.h
316
int (*var_to_pll) (const struct fb_info * info, u32 vclk_per, u32 bpp, union aty_pll * pll);
drivers/video/fbdev/aty/atyfb.h
317
u32 (*pll_to_var) (const struct fb_info * info, const union aty_pll * pll);
drivers/video/fbdev/aty/atyfb.h
318
void (*set_pll) (const struct fb_info * info, const union aty_pll * pll);
drivers/video/fbdev/aty/atyfb.h
319
void (*get_pll) (const struct fb_info *info, union aty_pll * pll);
drivers/video/fbdev/aty/atyfb.h
320
int (*init_pll) (const struct fb_info * info, union aty_pll * pll);
drivers/video/fbdev/aty/atyfb.h
321
void (*resume_pll)(const struct fb_info *info, union aty_pll *pll);
drivers/video/fbdev/aty/atyfb.h
333
extern void aty_set_pll_ct(const struct fb_info *info, const union aty_pll *pll);
drivers/video/fbdev/aty/atyfb_base.c
1329
var->bits_per_pixel, &par->pll);
drivers/video/fbdev/aty/atyfb_base.c
1348
par->dac_ops->set_dac(info, &par->pll,
drivers/video/fbdev/aty/atyfb_base.c
1350
par->pll_ops->set_pll(info, &par->pll);
drivers/video/fbdev/aty/atyfb_base.c
1354
pixclock_in_ps = par->pll_ops->pll_to_var(info, &par->pll);
drivers/video/fbdev/aty/atyfb_base.c
1541
union aty_pll pll;
drivers/video/fbdev/aty/atyfb_base.c
1544
memcpy(&pll, &par->pll, sizeof(pll));
drivers/video/fbdev/aty/atyfb_base.c
1558
var->bits_per_pixel, &pll);
drivers/video/fbdev/aty/atyfb_base.c
1569
var->pixclock = par->pll_ops->pll_to_var(info, &pll);
drivers/video/fbdev/aty/atyfb_base.c
1863
union aty_pll *pll = &par->pll;
drivers/video/fbdev/aty/atyfb_base.c
1864
u32 dsp_config = pll->ct.dsp_config;
drivers/video/fbdev/aty/atyfb_base.c
1865
u32 dsp_on_off = pll->ct.dsp_on_off;
drivers/video/fbdev/aty/atyfb_base.c
1867
clk.pll_ref_div = pll->ct.pll_ref_div;
drivers/video/fbdev/aty/atyfb_base.c
1868
clk.mclk_fb_div = pll->ct.mclk_fb_div;
drivers/video/fbdev/aty/atyfb_base.c
1869
clk.mclk_post_div = pll->ct.mclk_post_div_real;
drivers/video/fbdev/aty/atyfb_base.c
1870
clk.mclk_fb_mult = pll->ct.mclk_fb_mult;
drivers/video/fbdev/aty/atyfb_base.c
1871
clk.xclk_post_div = pll->ct.xclk_post_div_real;
drivers/video/fbdev/aty/atyfb_base.c
1872
clk.vclk_fb_div = pll->ct.vclk_fb_div;
drivers/video/fbdev/aty/atyfb_base.c
1873
clk.vclk_post_div = pll->ct.vclk_post_div_real;
drivers/video/fbdev/aty/atyfb_base.c
1888
union aty_pll *pll = &par->pll;
drivers/video/fbdev/aty/atyfb_base.c
1893
pll->ct.pll_ref_div = clk.pll_ref_div;
drivers/video/fbdev/aty/atyfb_base.c
1894
pll->ct.mclk_fb_div = clk.mclk_fb_div;
drivers/video/fbdev/aty/atyfb_base.c
1895
pll->ct.mclk_post_div_real = clk.mclk_post_div;
drivers/video/fbdev/aty/atyfb_base.c
1896
pll->ct.mclk_fb_mult = clk.mclk_fb_mult;
drivers/video/fbdev/aty/atyfb_base.c
1897
pll->ct.xclk_post_div_real = clk.xclk_post_div;
drivers/video/fbdev/aty/atyfb_base.c
1898
pll->ct.vclk_fb_div = clk.vclk_fb_div;
drivers/video/fbdev/aty/atyfb_base.c
1899
pll->ct.vclk_post_div_real = clk.vclk_post_div;
drivers/video/fbdev/aty/atyfb_base.c
1900
pll->ct.dsp_config = (clk.dsp_xclks_per_row & 0x3fff) |
drivers/video/fbdev/aty/atyfb_base.c
1903
pll->ct.dsp_on_off = (clk.dsp_off & 0x7ff) |
drivers/video/fbdev/aty/atyfb_base.c
1906
aty_set_pll_ct(info, pll);
drivers/video/fbdev/aty/atyfb_base.c
2136
par->pll_ops->resume_pll(info, &par->pll);
drivers/video/fbdev/aty/atyfb_base.c
2454
if (pll)
drivers/video/fbdev/aty/atyfb_base.c
2455
par->pll_limits.pll_max = pll;
drivers/video/fbdev/aty/atyfb_base.c
2616
ret = par->pll_ops->init_pll(info, &par->pll);
drivers/video/fbdev/aty/atyfb_base.c
2622
par->pll_ops->resume_pll(info, &par->pll);
drivers/video/fbdev/aty/atyfb_base.c
328
static int pll;
drivers/video/fbdev/aty/atyfb_base.c
3852
pll = simple_strtoul(this_opt + 4, NULL, 0);
drivers/video/fbdev/aty/atyfb_base.c
386
int pll, mclk, xclk, ecp_max;
drivers/video/fbdev/aty/atyfb_base.c
4012
module_param(pll, int, 0);
drivers/video/fbdev/aty/atyfb_base.c
4013
MODULE_PARM_DESC(pll, "int: override video clock");
drivers/video/fbdev/aty/atyfb_base.c
473
par->pll_limits.pll_max = aty_chips[i].pll;
drivers/video/fbdev/aty/atyfb_base.c
601
par->pll.ct.xres = 0;
drivers/video/fbdev/aty/atyfb_base.c
605
par->pll.ct.xres = var->xres;
drivers/video/fbdev/aty/mach64_ct.c
118
static int aty_dsp_gt(const struct fb_info *info, u32 bpp, struct pll_ct *pll)
drivers/video/fbdev/aty/mach64_ct.c
125
multiplier = ((u32)pll->mclk_fb_div) * pll->vclk_post_div_real;
drivers/video/fbdev/aty/mach64_ct.c
126
divider = ((u32)pll->vclk_fb_div) * pll->xclk_ref_div;
drivers/video/fbdev/aty/mach64_ct.c
128
ras_multiplier = pll->xclkmaxrasdelay;
drivers/video/fbdev/aty/mach64_ct.c
134
vshift = (6 - 2) - pll->xclk_post_div; /* FIFO is 64 bits wide in accelerator mode ... */
drivers/video/fbdev/aty/mach64_ct.c
140
if (pll->xres != 0) {
drivers/video/fbdev/aty/mach64_ct.c
144
divider = divider * pll->xres & ~7;
drivers/video/fbdev/aty/mach64_ct.c
147
ras_divider = ras_divider * pll->xres & ~7;
drivers/video/fbdev/aty/mach64_ct.c
158
tmp = ((multiplier * pll->fifo_size) << vshift) / divider;
drivers/video/fbdev/aty/mach64_ct.c
171
dsp_off = ((multiplier * (pll->fifo_size - 1)) << vshift) / divider -
drivers/video/fbdev/aty/mach64_ct.c
18
static int aty_valid_pll_ct (const struct fb_info *info, u32 vclk_per, struct pll_ct *pll);
drivers/video/fbdev/aty/mach64_ct.c
182
dsp_on = dsp_on + (tmp * 2) + (pll->xclkpagefaultdelay << xshift);
drivers/video/fbdev/aty/mach64_ct.c
19
static int aty_dsp_gt (const struct fb_info *info, u32 bpp, struct pll_ct *pll);
drivers/video/fbdev/aty/mach64_ct.c
198
pll->dsp_on_off = (dsp_on << 16) + dsp_off;
drivers/video/fbdev/aty/mach64_ct.c
199
pll->dsp_config = (dsp_precision << 20) | (pll->dsp_loop_latency << 16) | dsp_xclks;
drivers/video/fbdev/aty/mach64_ct.c
20
static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll);
drivers/video/fbdev/aty/mach64_ct.c
202
__func__, pll->dsp_config, pll->dsp_on_off);
drivers/video/fbdev/aty/mach64_ct.c
207
static int aty_valid_pll_ct(const struct fb_info *info, u32 vclk_per, struct pll_ct *pll)
drivers/video/fbdev/aty/mach64_ct.c
21
static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll);
drivers/video/fbdev/aty/mach64_ct.c
214
q = par->ref_clk_per * pll->pll_ref_div * 4 / vclk_per;
drivers/video/fbdev/aty/mach64_ct.c
219
pll->vclk_post_div = (q < 128*8);
drivers/video/fbdev/aty/mach64_ct.c
220
pll->vclk_post_div += (q < 64*8);
drivers/video/fbdev/aty/mach64_ct.c
221
pll->vclk_post_div += (q < 32*8);
drivers/video/fbdev/aty/mach64_ct.c
223
pll->vclk_post_div_real = aty_postdividers[pll->vclk_post_div];
drivers/video/fbdev/aty/mach64_ct.c
225
pll->vclk_fb_div = q * pll->vclk_post_div_real / 8;
drivers/video/fbdev/aty/mach64_ct.c
226
pllvclk = (1000000 * 2 * pll->vclk_fb_div) /
drivers/video/fbdev/aty/mach64_ct.c
227
(par->ref_clk_per * pll->pll_ref_div);
drivers/video/fbdev/aty/mach64_ct.c
230
__func__, pllvclk, pllvclk / pll->vclk_post_div_real);
drivers/video/fbdev/aty/mach64_ct.c
232
pll->pll_vclk_cntl = 0x03; /* VCLK = PLL_VCLK/VCLKx_POST */
drivers/video/fbdev/aty/mach64_ct.c
236
int ecp = pllvclk / pll->vclk_post_div_real;
drivers/video/fbdev/aty/mach64_ct.c
243
pll->pll_vclk_cntl |= ecp_div << 4;
drivers/video/fbdev/aty/mach64_ct.c
249
static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll)
drivers/video/fbdev/aty/mach64_ct.c
254
if ((err = aty_valid_pll_ct(info, vclk_per, &pll->ct)))
drivers/video/fbdev/aty/mach64_ct.c
256
if (M64_HAS(GTB_DSP) && (err = aty_dsp_gt(info, bpp, &pll->ct)))
drivers/video/fbdev/aty/mach64_ct.c
262
static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll)
drivers/video/fbdev/aty/mach64_ct.c
266
ret = par->ref_clk_per * pll->ct.pll_ref_div * pll->ct.vclk_post_div_real / pll->ct.vclk_fb_div / 2;
drivers/video/fbdev/aty/mach64_ct.c
268
if(pll->ct.xres > 0) {
drivers/video/fbdev/aty/mach64_ct.c
270
ret /= pll->ct.xres;
drivers/video/fbdev/aty/mach64_ct.c
279
void aty_set_pll_ct(const struct fb_info *info, const union aty_pll *pll)
drivers/video/fbdev/aty/mach64_ct.c
293
pll->ct.pll_ext_cntl, pll->ct.pll_gen_cntl, pll->ct.pll_vclk_cntl);
drivers/video/fbdev/aty/mach64_ct.c
297
par->clk_wr_offset, pll->ct.vclk_fb_div,
drivers/video/fbdev/aty/mach64_ct.c
298
pll->ct.pll_ref_div, pll->ct.vclk_post_div, pll->ct.vclk_post_div_real);
drivers/video/fbdev/aty/mach64_ct.c
315
aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, par);
drivers/video/fbdev/aty/mach64_ct.c
321
tmp |= ((pll->ct.vclk_post_div & 0x03U) << tmp2);
drivers/video/fbdev/aty/mach64_ct.c
328
tmp |= pll->ct.pll_ext_cntl;
drivers/video/fbdev/aty/mach64_ct.c
333
aty_st_pll_ct(tmp, (pll->ct.vclk_fb_div & 0xFFU), par);
drivers/video/fbdev/aty/mach64_ct.c
335
aty_st_pll_ct(PLL_GEN_CNTL, (pll->ct.pll_gen_cntl & (~(PLL_OVERRIDE | PLL_MCLK_RST))) | OSC_EN, par);
drivers/video/fbdev/aty/mach64_ct.c
338
aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl & ~(PLL_VCLK_RST), par);
drivers/video/fbdev/aty/mach64_ct.c
341
aty_st_pll_ct(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, par);
drivers/video/fbdev/aty/mach64_ct.c
342
aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, par);
drivers/video/fbdev/aty/mach64_ct.c
360
aty_st_le32(DSP_CONFIG, pll->ct.dsp_config, par);
drivers/video/fbdev/aty/mach64_ct.c
361
aty_st_le32(DSP_ON_OFF, pll->ct.dsp_on_off, par);
drivers/video/fbdev/aty/mach64_ct.c
378
static void aty_get_pll_ct(const struct fb_info *info, union aty_pll *pll)
drivers/video/fbdev/aty/mach64_ct.c
385
pll->ct.vclk_post_div = (aty_ld_pll_ct(VCLK_POST_DIV, par) >> tmp) & 0x03U;
drivers/video/fbdev/aty/mach64_ct.c
387
pll->ct.pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par) & 0x0FU;
drivers/video/fbdev/aty/mach64_ct.c
388
pll->ct.vclk_fb_div = aty_ld_pll_ct(VCLK0_FB_DIV + clock, par) & 0xFFU;
drivers/video/fbdev/aty/mach64_ct.c
389
pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
drivers/video/fbdev/aty/mach64_ct.c
390
pll->ct.mclk_fb_div = aty_ld_pll_ct(MCLK_FB_DIV, par);
drivers/video/fbdev/aty/mach64_ct.c
392
pll->ct.pll_gen_cntl = aty_ld_pll_ct(PLL_GEN_CNTL, par);
drivers/video/fbdev/aty/mach64_ct.c
393
pll->ct.pll_vclk_cntl = aty_ld_pll_ct(PLL_VCLK_CNTL, par);
drivers/video/fbdev/aty/mach64_ct.c
396
pll->ct.dsp_config = aty_ld_le32(DSP_CONFIG, par);
drivers/video/fbdev/aty/mach64_ct.c
397
pll->ct.dsp_on_off = aty_ld_le32(DSP_ON_OFF, par);
drivers/video/fbdev/aty/mach64_ct.c
401
static int aty_init_pll_ct(const struct fb_info *info, union aty_pll *pll)
drivers/video/fbdev/aty/mach64_ct.c
410
pll->ct.pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par);
drivers/video/fbdev/aty/mach64_ct.c
411
pll->ct.xclk_post_div = pll->ct.pll_ext_cntl & 0x07;
drivers/video/fbdev/aty/mach64_ct.c
412
pll->ct.xclk_ref_div = 1;
drivers/video/fbdev/aty/mach64_ct.c
413
switch (pll->ct.xclk_post_div) {
drivers/video/fbdev/aty/mach64_ct.c
418
pll->ct.xclk_ref_div = 3;
drivers/video/fbdev/aty/mach64_ct.c
419
pll->ct.xclk_post_div = 0;
drivers/video/fbdev/aty/mach64_ct.c
423
printk(KERN_CRIT "atyfb: Unsupported xclk source: %d.\n", pll->ct.xclk_post_div);
drivers/video/fbdev/aty/mach64_ct.c
426
pll->ct.mclk_fb_mult = 2;
drivers/video/fbdev/aty/mach64_ct.c
427
if(pll->ct.pll_ext_cntl & PLL_MFB_TIMES_4_2B) {
drivers/video/fbdev/aty/mach64_ct.c
428
pll->ct.mclk_fb_mult = 4;
drivers/video/fbdev/aty/mach64_ct.c
429
pll->ct.xclk_post_div -= 1;
drivers/video/fbdev/aty/mach64_ct.c
434
__func__, pll->ct.mclk_fb_mult, pll->ct.xclk_post_div);
drivers/video/fbdev/aty/mach64_ct.c
440
pll->ct.xclkpagefaultdelay = ((memcntl & 0xc00) >> 10) + ((memcntl & 0x1000) >> 12) + trp + 2;
drivers/video/fbdev/aty/mach64_ct.c
441
pll->ct.xclkmaxrasdelay = ((memcntl & 0x70000) >> 16) + trp + 2;
drivers/video/fbdev/aty/mach64_ct.c
444
pll->ct.fifo_size = 32;
drivers/video/fbdev/aty/mach64_ct.c
446
pll->ct.fifo_size = 24;
drivers/video/fbdev/aty/mach64_ct.c
447
pll->ct.xclkpagefaultdelay += 2;
drivers/video/fbdev/aty/mach64_ct.c
448
pll->ct.xclkmaxrasdelay += 3;
drivers/video/fbdev/aty/mach64_ct.c
454
pll->ct.dsp_loop_latency = 10;
drivers/video/fbdev/aty/mach64_ct.c
456
pll->ct.dsp_loop_latency = 8;
drivers/video/fbdev/aty/mach64_ct.c
457
pll->ct.xclkpagefaultdelay += 2;
drivers/video/fbdev/aty/mach64_ct.c
463
pll->ct.dsp_loop_latency = 9;
drivers/video/fbdev/aty/mach64_ct.c
465
pll->ct.dsp_loop_latency = 8;
drivers/video/fbdev/aty/mach64_ct.c
466
pll->ct.xclkpagefaultdelay += 1;
drivers/video/fbdev/aty/mach64_ct.c
471
pll->ct.dsp_loop_latency = 11;
drivers/video/fbdev/aty/mach64_ct.c
473
pll->ct.dsp_loop_latency = 10;
drivers/video/fbdev/aty/mach64_ct.c
474
pll->ct.xclkpagefaultdelay += 1;
drivers/video/fbdev/aty/mach64_ct.c
478
pll->ct.dsp_loop_latency = 8;
drivers/video/fbdev/aty/mach64_ct.c
479
pll->ct.xclkpagefaultdelay += 3;
drivers/video/fbdev/aty/mach64_ct.c
482
pll->ct.dsp_loop_latency = 11;
drivers/video/fbdev/aty/mach64_ct.c
483
pll->ct.xclkpagefaultdelay += 3;
drivers/video/fbdev/aty/mach64_ct.c
487
if (pll->ct.xclkmaxrasdelay <= pll->ct.xclkpagefaultdelay)
drivers/video/fbdev/aty/mach64_ct.c
488
pll->ct.xclkmaxrasdelay = pll->ct.xclkpagefaultdelay + 1;
drivers/video/fbdev/aty/mach64_ct.c
497
pll->ct.dsp_loop_latency = (dsp_config & DSP_LOOP_LATENCY) >> 16;
drivers/video/fbdev/aty/mach64_ct.c
506
pll->ct.fifo_size = 32;
drivers/video/fbdev/aty/mach64_ct.c
508
pll->ct.fifo_size = 24;
drivers/video/fbdev/aty/mach64_ct.c
515
pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
drivers/video/fbdev/aty/mach64_ct.c
517
pll->ct.xclk_post_div_real = aty_postdividers[pll_ext_cntl & 0x07];
drivers/video/fbdev/aty/mach64_ct.c
521
pll->ct.mclk_fb_div = mclk_fb_div;
drivers/video/fbdev/aty/mach64_ct.c
525
pll->ct.pll_ref_div = par->pll_per * 2 * 255 / par->ref_clk_per;
drivers/video/fbdev/aty/mach64_ct.c
528
q = par->ref_clk_per * pll->ct.pll_ref_div * 8 /
drivers/video/fbdev/aty/mach64_ct.c
529
(pll->ct.mclk_fb_mult * par->xclk_per);
drivers/video/fbdev/aty/mach64_ct.c
539
pll->ct.xclk_post_div_real = aty_postdividers[xpost_div];
drivers/video/fbdev/aty/mach64_ct.c
540
pll->ct.mclk_fb_div = q * pll->ct.xclk_post_div_real / 8;
drivers/video/fbdev/aty/mach64_ct.c
545
pll->ct.xclk_post_div = xpost_div;
drivers/video/fbdev/aty/mach64_ct.c
546
pll->ct.xclk_ref_div = 1;
drivers/video/fbdev/aty/mach64_ct.c
551
pllmclk = (1000000 * pll->ct.mclk_fb_mult * pll->ct.mclk_fb_div) /
drivers/video/fbdev/aty/mach64_ct.c
552
(par->ref_clk_per * pll->ct.pll_ref_div);
drivers/video/fbdev/aty/mach64_ct.c
554
__func__, pllmclk, pllmclk / pll->ct.xclk_post_div_real);
drivers/video/fbdev/aty/mach64_ct.c
558
pll->ct.pll_gen_cntl = OSC_EN;
drivers/video/fbdev/aty/mach64_ct.c
560
pll->ct.pll_gen_cntl = OSC_EN | DLL_PWDN /* | FORCE_DCLK_TRI_STATE */;
drivers/video/fbdev/aty/mach64_ct.c
563
pll->ct.pll_ext_cntl = 0;
drivers/video/fbdev/aty/mach64_ct.c
565
pll->ct.pll_ext_cntl = xpost_div;
drivers/video/fbdev/aty/mach64_ct.c
567
if (pll->ct.mclk_fb_mult == 4)
drivers/video/fbdev/aty/mach64_ct.c
568
pll->ct.pll_ext_cntl |= PLL_MFB_TIMES_4_2B;
drivers/video/fbdev/aty/mach64_ct.c
571
pll->ct.pll_gen_cntl |= (xpost_div << 4); /* mclk == xclk */
drivers/video/fbdev/aty/mach64_ct.c
577
pll->ct.pll_gen_cntl |= (6 << 4); /* mclk == sclk */
drivers/video/fbdev/aty/mach64_ct.c
579
q = par->ref_clk_per * pll->ct.pll_ref_div * 4 / par->mclk_per;
drivers/video/fbdev/aty/mach64_ct.c
589
pll->ct.sclk_fb_div = q * sclk_post_div_real / 8;
drivers/video/fbdev/aty/mach64_ct.c
590
pll->ct.spll_cntl2 = mpost_div << 4;
drivers/video/fbdev/aty/mach64_ct.c
592
pllsclk = (1000000 * 2 * pll->ct.sclk_fb_div) /
drivers/video/fbdev/aty/mach64_ct.c
593
(par->ref_clk_per * pll->ct.pll_ref_div);
drivers/video/fbdev/aty/mach64_ct.c
600
pll->ct.ext_vpll_cntl = aty_ld_pll_ct(EXT_VPLL_CNTL, par);
drivers/video/fbdev/aty/mach64_ct.c
601
pll->ct.ext_vpll_cntl &= ~(EXT_VPLL_EN | EXT_VPLL_VGA_EN | EXT_VPLL_INSYNC);
drivers/video/fbdev/aty/mach64_ct.c
607
union aty_pll *pll)
drivers/video/fbdev/aty/mach64_ct.c
619
aty_st_pll_ct(SCLK_FB_DIV, pll->ct.sclk_fb_div, par);
drivers/video/fbdev/aty/mach64_ct.c
620
aty_st_pll_ct(SPLL_CNTL2, pll->ct.spll_cntl2, par);
drivers/video/fbdev/aty/mach64_ct.c
628
aty_st_pll_ct(PLL_REF_DIV, pll->ct.pll_ref_div, par);
drivers/video/fbdev/aty/mach64_ct.c
629
aty_st_pll_ct(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, par);
drivers/video/fbdev/aty/mach64_ct.c
630
aty_st_pll_ct(MCLK_FB_DIV, pll->ct.mclk_fb_div, par);
drivers/video/fbdev/aty/mach64_ct.c
631
aty_st_pll_ct(PLL_EXT_CNTL, pll->ct.pll_ext_cntl, par);
drivers/video/fbdev/aty/mach64_ct.c
632
aty_st_pll_ct(EXT_VPLL_CNTL, pll->ct.ext_vpll_cntl, par);
drivers/video/fbdev/aty/mach64_gx.c
124
u32 bpp, union aty_pll *pll)
drivers/video/fbdev/aty/mach64_gx.c
154
pll->ibm514.m = RGB514_clocks[i].m;
drivers/video/fbdev/aty/mach64_gx.c
155
pll->ibm514.n = RGB514_clocks[i].n;
drivers/video/fbdev/aty/mach64_gx.c
162
const union aty_pll *pll)
drivers/video/fbdev/aty/mach64_gx.c
167
df = pll->ibm514.m >> 6;
drivers/video/fbdev/aty/mach64_gx.c
168
vco_div_count = pll->ibm514.m & 0x3f;
drivers/video/fbdev/aty/mach64_gx.c
169
ref_div_count = pll->ibm514.n;
drivers/video/fbdev/aty/mach64_gx.c
176
const union aty_pll *pll)
drivers/video/fbdev/aty/mach64_gx.c
186
aty_st_514(0x20, pll->ibm514.m, par); /* F0 / M0 */
drivers/video/fbdev/aty/mach64_gx.c
187
aty_st_514(0x21, pll->ibm514.n, par); /* F1 / N0 */
drivers/video/fbdev/aty/mach64_gx.c
206
const union aty_pll *pll, u32 bpp,
drivers/video/fbdev/aty/mach64_gx.c
289
const union aty_pll *pll, u32 bpp,
drivers/video/fbdev/aty/mach64_gx.c
297
dotClock = 100000000 / pll->ics2595.period_in_ps;
drivers/video/fbdev/aty/mach64_gx.c
342
u32 bpp, union aty_pll *pll)
drivers/video/fbdev/aty/mach64_gx.c
390
pll->ics2595.program_bits = program_bits;
drivers/video/fbdev/aty/mach64_gx.c
391
pll->ics2595.locationAddr = 0;
drivers/video/fbdev/aty/mach64_gx.c
392
pll->ics2595.post_divider = post_divider;
drivers/video/fbdev/aty/mach64_gx.c
393
pll->ics2595.period_in_ps = vclk_per;
drivers/video/fbdev/aty/mach64_gx.c
399
const union aty_pll *pll)
drivers/video/fbdev/aty/mach64_gx.c
401
return (pll->ics2595.period_in_ps); /* default for now */
drivers/video/fbdev/aty/mach64_gx.c
428
const union aty_pll *pll)
drivers/video/fbdev/aty/mach64_gx.c
448
program_bits = pll->ics2595.program_bits;
drivers/video/fbdev/aty/mach64_gx.c
449
locationAddr = pll->ics2595.locationAddr;
drivers/video/fbdev/aty/mach64_gx.c
480
((pll->ics2595.locationAddr & 0x0F) | CLOCK_STROBE), par);
drivers/video/fbdev/aty/mach64_gx.c
496
u32 bpp, union aty_pll *pll)
drivers/video/fbdev/aty/mach64_gx.c
556
pll->ics2595.program_bits = program_bits;
drivers/video/fbdev/aty/mach64_gx.c
557
pll->ics2595.locationAddr = 0;
drivers/video/fbdev/aty/mach64_gx.c
558
pll->ics2595.post_divider = divider; /* fuer nix */
drivers/video/fbdev/aty/mach64_gx.c
559
pll->ics2595.period_in_ps = vclk_per;
drivers/video/fbdev/aty/mach64_gx.c
565
const union aty_pll *pll)
drivers/video/fbdev/aty/mach64_gx.c
567
return (pll->ics2595.period_in_ps); /* default for now */
drivers/video/fbdev/aty/mach64_gx.c
571
const union aty_pll *pll)
drivers/video/fbdev/aty/mach64_gx.c
583
program_bits = pll->ics2595.program_bits;
drivers/video/fbdev/aty/mach64_gx.c
584
locationAddr = pll->ics2595.locationAddr;
drivers/video/fbdev/aty/mach64_gx.c
612
u32 bpp, union aty_pll *pll)
drivers/video/fbdev/aty/mach64_gx.c
674
pll->ics2595.program_bits = program_bits;
drivers/video/fbdev/aty/mach64_gx.c
675
pll->ics2595.locationAddr = 0;
drivers/video/fbdev/aty/mach64_gx.c
676
pll->ics2595.post_divider = 0;
drivers/video/fbdev/aty/mach64_gx.c
677
pll->ics2595.period_in_ps = vclk_per;
drivers/video/fbdev/aty/mach64_gx.c
683
const union aty_pll *pll)
drivers/video/fbdev/aty/mach64_gx.c
685
return (pll->ics2595.period_in_ps); /* default for now */
drivers/video/fbdev/aty/mach64_gx.c
689
const union aty_pll *pll)
drivers/video/fbdev/aty/mach64_gx.c
702
program_bits = pll->ics2595.program_bits;
drivers/video/fbdev/aty/mach64_gx.c
703
locationAddr = pll->ics2595.locationAddr;
drivers/video/fbdev/aty/mach64_gx.c
735
u32 bpp, union aty_pll *pll)
drivers/video/fbdev/aty/mach64_gx.c
792
pll->ics2595.program_bits = program_bits;
drivers/video/fbdev/aty/mach64_gx.c
793
pll->ics2595.locationAddr = 0;
drivers/video/fbdev/aty/mach64_gx.c
794
pll->ics2595.post_divider = divider; /* fuer nix */
drivers/video/fbdev/aty/mach64_gx.c
795
pll->ics2595.period_in_ps = vclk_per;
drivers/video/fbdev/aty/mach64_gx.c
801
const union aty_pll *pll)
drivers/video/fbdev/aty/mach64_gx.c
803
return (pll->ics2595.period_in_ps); /* default for now */
drivers/video/fbdev/aty/mach64_gx.c
807
const union aty_pll *pll)
drivers/video/fbdev/aty/mach64_gx.c
81
const union aty_pll *pll, u32 bpp, u32 accel)
drivers/video/fbdev/aty/mach64_gx.c
820
program_bits = pll->ics2595.program_bits;
drivers/video/fbdev/aty/mach64_gx.c
821
locationAddr = pll->ics2595.locationAddr;
drivers/video/fbdev/aty/mach64_gx.c
882
const union aty_pll *pll, u32 bpp,
drivers/video/fbdev/aty/radeon_base.c
1589
if (freq > rinfo->pll.ppll_max)
drivers/video/fbdev/aty/radeon_base.c
1590
freq = rinfo->pll.ppll_max;
drivers/video/fbdev/aty/radeon_base.c
1591
if (freq*12 < rinfo->pll.ppll_min)
drivers/video/fbdev/aty/radeon_base.c
1592
freq = rinfo->pll.ppll_min / 12;
drivers/video/fbdev/aty/radeon_base.c
1594
freq, rinfo->pll.ppll_min, rinfo->pll.ppll_max);
drivers/video/fbdev/aty/radeon_base.c
1603
if (pll_output_freq >= rinfo->pll.ppll_min &&
drivers/video/fbdev/aty/radeon_base.c
1604
pll_output_freq <= rinfo->pll.ppll_max)
drivers/video/fbdev/aty/radeon_base.c
1615
rinfo->pll.ref_div, rinfo->pll.ref_clk,
drivers/video/fbdev/aty/radeon_base.c
1625
rinfo->pll.ref_div, rinfo->pll.ref_clk,
drivers/video/fbdev/aty/radeon_base.c
1628
fb_div = round_div(rinfo->pll.ref_div*pll_output_freq,
drivers/video/fbdev/aty/radeon_base.c
1629
rinfo->pll.ref_clk);
drivers/video/fbdev/aty/radeon_base.c
1630
regs->ppll_ref_div = rinfo->pll.ref_div;
drivers/video/fbdev/aty/radeon_base.c
558
rinfo->pll.ref_clk = (*val) / 10;
drivers/video/fbdev/aty/radeon_base.c
562
rinfo->pll.sclk = (*val) / 10;
drivers/video/fbdev/aty/radeon_base.c
566
rinfo->pll.mclk = (*val) / 10;
drivers/video/fbdev/aty/radeon_base.c
698
rinfo->pll.ref_clk = xtal;
drivers/video/fbdev/aty/radeon_base.c
699
rinfo->pll.ref_div = ref_div;
drivers/video/fbdev/aty/radeon_base.c
700
rinfo->pll.sclk = sclk;
drivers/video/fbdev/aty/radeon_base.c
701
rinfo->pll.mclk = mclk;
drivers/video/fbdev/aty/radeon_base.c
719
rinfo->pll.ppll_max = 35000;
drivers/video/fbdev/aty/radeon_base.c
720
rinfo->pll.ppll_min = 12000;
drivers/video/fbdev/aty/radeon_base.c
721
rinfo->pll.mclk = 23000;
drivers/video/fbdev/aty/radeon_base.c
722
rinfo->pll.sclk = 23000;
drivers/video/fbdev/aty/radeon_base.c
723
rinfo->pll.ref_clk = 2700;
drivers/video/fbdev/aty/radeon_base.c
730
rinfo->pll.ppll_max = 35000;
drivers/video/fbdev/aty/radeon_base.c
731
rinfo->pll.ppll_min = 12000;
drivers/video/fbdev/aty/radeon_base.c
732
rinfo->pll.mclk = 27500;
drivers/video/fbdev/aty/radeon_base.c
733
rinfo->pll.sclk = 27500;
drivers/video/fbdev/aty/radeon_base.c
734
rinfo->pll.ref_clk = 2700;
drivers/video/fbdev/aty/radeon_base.c
740
rinfo->pll.ppll_max = 35000;
drivers/video/fbdev/aty/radeon_base.c
741
rinfo->pll.ppll_min = 12000;
drivers/video/fbdev/aty/radeon_base.c
742
rinfo->pll.mclk = 25000;
drivers/video/fbdev/aty/radeon_base.c
743
rinfo->pll.sclk = 25000;
drivers/video/fbdev/aty/radeon_base.c
744
rinfo->pll.ref_clk = 2700;
drivers/video/fbdev/aty/radeon_base.c
750
rinfo->pll.ppll_max = 40000;
drivers/video/fbdev/aty/radeon_base.c
751
rinfo->pll.ppll_min = 20000;
drivers/video/fbdev/aty/radeon_base.c
752
rinfo->pll.mclk = 27000;
drivers/video/fbdev/aty/radeon_base.c
753
rinfo->pll.sclk = 27000;
drivers/video/fbdev/aty/radeon_base.c
754
rinfo->pll.ref_clk = 2700;
drivers/video/fbdev/aty/radeon_base.c
761
rinfo->pll.ppll_max = 35000;
drivers/video/fbdev/aty/radeon_base.c
762
rinfo->pll.ppll_min = 12000;
drivers/video/fbdev/aty/radeon_base.c
763
rinfo->pll.mclk = 16600;
drivers/video/fbdev/aty/radeon_base.c
764
rinfo->pll.sclk = 16600;
drivers/video/fbdev/aty/radeon_base.c
765
rinfo->pll.ref_clk = 2700;
drivers/video/fbdev/aty/radeon_base.c
768
rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
drivers/video/fbdev/aty/radeon_base.c
788
rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08);
drivers/video/fbdev/aty/radeon_base.c
789
rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a);
drivers/video/fbdev/aty/radeon_base.c
790
rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e);
drivers/video/fbdev/aty/radeon_base.c
791
rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10);
drivers/video/fbdev/aty/radeon_base.c
792
rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12);
drivers/video/fbdev/aty/radeon_base.c
793
rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16);
drivers/video/fbdev/aty/radeon_base.c
819
if (rinfo->pll.mclk == 0)
drivers/video/fbdev/aty/radeon_base.c
820
rinfo->pll.mclk = 20000;
drivers/video/fbdev/aty/radeon_base.c
821
if (rinfo->pll.sclk == 0)
drivers/video/fbdev/aty/radeon_base.c
822
rinfo->pll.sclk = 20000;
drivers/video/fbdev/aty/radeon_base.c
825
rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100,
drivers/video/fbdev/aty/radeon_base.c
826
rinfo->pll.ref_div,
drivers/video/fbdev/aty/radeon_base.c
827
rinfo->pll.mclk / 100, rinfo->pll.mclk % 100,
drivers/video/fbdev/aty/radeon_base.c
828
rinfo->pll.sclk / 100, rinfo->pll.sclk % 100);
drivers/video/fbdev/aty/radeon_base.c
829
printk("radeonfb: PLL min %d max %d\n", rinfo->pll.ppll_min, rinfo->pll.ppll_max);
drivers/video/fbdev/aty/radeon_monitor.c
667
rinfo->panel_info.ref_divider = rinfo->pll.ref_div;
drivers/video/fbdev/aty/radeon_pm.c
1649
tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div;
drivers/video/fbdev/aty/radeon_pm.c
2194
OUTPLL(pllPPLL_REF_DIV, rinfo->pll.ref_div);
drivers/video/fbdev/aty/radeon_pm.c
2450
tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div;
drivers/video/fbdev/aty/radeonfb.h
342
struct pll_info pll;
drivers/video/fbdev/core/svgalib.c
380
int svga_compute_pll(const struct svga_pll *pll, u32 f_wanted, u16 *m, u16 *n, u16 *r, int node)
drivers/video/fbdev/core/svgalib.c
387
ar = pll->r_max;
drivers/video/fbdev/core/svgalib.c
397
while ((ar > pll->r_min) && (f_vco > pll->f_vco_max)) {
drivers/video/fbdev/core/svgalib.c
403
if ((f_vco < pll->f_vco_min) || (f_vco > pll->f_vco_max))
drivers/video/fbdev/core/svgalib.c
411
am = pll->m_min;
drivers/video/fbdev/core/svgalib.c
412
an = pll->n_min;
drivers/video/fbdev/core/svgalib.c
414
while ((am <= pll->m_max) && (an <= pll->n_max)) {
drivers/video/fbdev/core/svgalib.c
415
f_current = (pll->f_base * am) / an;
drivers/video/fbdev/core/svgalib.c
430
f_current = (pll->f_base * *m) / *n;
drivers/video/fbdev/matrox/g450_pll.c
101
n = ((tvco * (m+1) + minfo->features.pll.ref_freq) / (minfo->features.pll.ref_freq * 2)) - 2;
drivers/video/fbdev/matrox/g450_pll.c
139
unsigned int mnp, unsigned int pll)
drivers/video/fbdev/matrox/g450_pll.c
141
switch (pll) {
drivers/video/fbdev/matrox/g450_pll.c
176
unsigned int mnp, unsigned int pll)
drivers/video/fbdev/matrox/g450_pll.c
182
switch (pll) {
drivers/video/fbdev/matrox/g450_pll.c
232
unsigned int pll)
drivers/video/fbdev/matrox/g450_pll.c
234
return g450_isplllocked(minfo, g450_setpll(minfo, mnp, pll));
drivers/video/fbdev/matrox/g450_pll.c
237
static void updatehwstate_clk(struct matrox_hw_state* hw, unsigned int mnp, unsigned int pll) {
drivers/video/fbdev/matrox/g450_pll.c
238
switch (pll) {
drivers/video/fbdev/matrox/g450_pll.c
248
unsigned int pll)
drivers/video/fbdev/matrox/g450_pll.c
250
if (g450_cmppll(minfo, mnp, pll)) {
drivers/video/fbdev/matrox/g450_pll.c
251
g450_setpll(minfo, mnp, pll);
drivers/video/fbdev/matrox/g450_pll.c
256
unsigned int pll,
drivers/video/fbdev/matrox/g450_pll.c
283
if (g450_testpll(minfo, mnp - 0x0300, pll) &&
drivers/video/fbdev/matrox/g450_pll.c
284
g450_testpll(minfo, mnp + 0x0300, pll) &&
drivers/video/fbdev/matrox/g450_pll.c
285
g450_testpll(minfo, mnp - 0x0200, pll) &&
drivers/video/fbdev/matrox/g450_pll.c
286
g450_testpll(minfo, mnp + 0x0200, pll) &&
drivers/video/fbdev/matrox/g450_pll.c
287
g450_testpll(minfo, mnp - 0x0100, pll) &&
drivers/video/fbdev/matrox/g450_pll.c
288
g450_testpll(minfo, mnp + 0x0100, pll)) {
drivers/video/fbdev/matrox/g450_pll.c
289
if (g450_testpll(minfo, mnp, pll)) {
drivers/video/fbdev/matrox/g450_pll.c
292
} else if (!found && g450_testpll(minfo, mnp, pll)) {
drivers/video/fbdev/matrox/g450_pll.c
298
g450_setpll(minfo, mnpfound, pll);
drivers/video/fbdev/matrox/g450_pll.c
334
unsigned int pll, unsigned int *mnparray,
drivers/video/fbdev/matrox/g450_pll.c
341
switch (pll) {
drivers/video/fbdev/matrox/g450_pll.c
37
return (minfo->features.pll.ref_freq * n + (m >> 1)) / m;
drivers/video/fbdev/matrox/g450_pll.c
382
switch (pll) {
drivers/video/fbdev/matrox/g450_pll.c
481
matroxfb_g450_setpll_cond(minfo, mnp, pll);
drivers/video/fbdev/matrox/g450_pll.c
483
mnp = g450_findworkingpll(minfo, pll, mnparray, mnpcount);
drivers/video/fbdev/matrox/g450_pll.c
486
updatehwstate_clk(&minfo->hw, mnp, pll);
drivers/video/fbdev/matrox/g450_pll.c
497
unsigned int pll)
drivers/video/fbdev/matrox/g450_pll.c
505
r = __g450_setclk(minfo, fout, pll, arr, arr + MNP_TABLE_SIZE);
drivers/video/fbdev/matrox/g450_pll.h
11
unsigned int pll);
drivers/video/fbdev/matrox/g450_pll.h
8
unsigned int pll);
drivers/video/fbdev/matrox/matroxfb_DAC1064.c
182
} else if (minfo->crtc2.pixclock == minfo->features.pll.ref_freq) {
drivers/video/fbdev/matrox/matroxfb_DAC1064.c
590
minfo->features.pll.vco_freq_min = 62000;
drivers/video/fbdev/matrox/matroxfb_DAC1064.c
591
minfo->features.pll.ref_freq = 14318;
drivers/video/fbdev/matrox/matroxfb_DAC1064.c
592
minfo->features.pll.feed_div_min = 100;
drivers/video/fbdev/matrox/matroxfb_DAC1064.c
593
minfo->features.pll.feed_div_max = 127;
drivers/video/fbdev/matrox/matroxfb_DAC1064.c
594
minfo->features.pll.in_div_min = 1;
drivers/video/fbdev/matrox/matroxfb_DAC1064.c
595
minfo->features.pll.in_div_max = 31;
drivers/video/fbdev/matrox/matroxfb_DAC1064.c
596
minfo->features.pll.post_shift_max = 3;
drivers/video/fbdev/matrox/matroxfb_DAC1064.c
728
matroxfb_g450_setclk(minfo, minfo->values.pll.video, M_VIDEO_PLL);
drivers/video/fbdev/matrox/matroxfb_DAC1064.c
738
matroxfb_g450_setclk(minfo, minfo->values.pll.system, M_SYSTEM_PLL);
drivers/video/fbdev/matrox/matroxfb_DAC1064.c
855
minfo->features.pll.vco_freq_min = 130000; /* my sample: >118 */
drivers/video/fbdev/matrox/matroxfb_DAC1064.c
857
minfo->features.pll.vco_freq_min = 62000;
drivers/video/fbdev/matrox/matroxfb_DAC1064.c
859
if (!minfo->features.pll.ref_freq) {
drivers/video/fbdev/matrox/matroxfb_DAC1064.c
860
minfo->features.pll.ref_freq = 27000;
drivers/video/fbdev/matrox/matroxfb_DAC1064.c
862
minfo->features.pll.feed_div_min = 7;
drivers/video/fbdev/matrox/matroxfb_DAC1064.c
863
minfo->features.pll.feed_div_max = 127;
drivers/video/fbdev/matrox/matroxfb_DAC1064.c
864
minfo->features.pll.in_div_min = 1;
drivers/video/fbdev/matrox/matroxfb_DAC1064.c
865
minfo->features.pll.in_div_max = 31;
drivers/video/fbdev/matrox/matroxfb_DAC1064.c
866
minfo->features.pll.post_shift_max = 3;
drivers/video/fbdev/matrox/matroxfb_Ti3026.c
547
minfo->features.pll.vco_freq_min = 110000;
drivers/video/fbdev/matrox/matroxfb_Ti3026.c
548
minfo->features.pll.ref_freq = 114545;
drivers/video/fbdev/matrox/matroxfb_Ti3026.c
549
minfo->features.pll.feed_div_min = 2;
drivers/video/fbdev/matrox/matroxfb_Ti3026.c
550
minfo->features.pll.feed_div_max = 24;
drivers/video/fbdev/matrox/matroxfb_Ti3026.c
551
minfo->features.pll.in_div_min = 2;
drivers/video/fbdev/matrox/matroxfb_Ti3026.c
552
minfo->features.pll.in_div_max = 63;
drivers/video/fbdev/matrox/matroxfb_Ti3026.c
553
minfo->features.pll.post_shift_max = 3;
drivers/video/fbdev/matrox/matroxfb_base.h
410
struct matrox_pll_features pll;
drivers/video/fbdev/matrox/matroxfb_base.h
476
} pll;
drivers/video/fbdev/matrox/matroxfb_maven.c
224
static int matroxfb_PLL_mavenclock(const struct matrox_pll_features2* pll,
drivers/video/fbdev/matrox/matroxfb_maven.c
231
unsigned int fmin = pll->vco_freq_min / ctl->den;
drivers/video/fbdev/matrox/matroxfb_maven.c
241
fmax = pll->vco_freq_max / ctl->den;
drivers/video/fbdev/matrox/matroxfb_maven.c
245
for (p = 1; p <= pll->post_shift_max; p++) {
drivers/video/fbdev/matrox/matroxfb_maven.c
256
for (m = pll->in_div_min; m <= pll->in_div_max; m++) {
drivers/video/fbdev/matrox/matroxfb_maven.c
262
if (n < pll->feed_div_min)
drivers/video/fbdev/matrox/matroxfb_maven.c
264
if (n > pll->feed_div_max)
drivers/video/fbdev/matrox/matroxfb_misc.c
130
int matroxfb_PLL_calcclock(const struct matrox_pll_features* pll, unsigned int freq, unsigned int fmax,
drivers/video/fbdev/matrox/matroxfb_misc.c
134
unsigned int fxtal = pll->ref_freq;
drivers/video/fbdev/matrox/matroxfb_misc.c
143
printk(KERN_ERR "post_shift_max: %d\n", pll->post_shift_max);
drivers/video/fbdev/matrox/matroxfb_misc.c
144
printk(KERN_ERR "ref_freq: %d\n", pll->ref_freq);
drivers/video/fbdev/matrox/matroxfb_misc.c
146
printk(KERN_ERR "vco_freq_min: %d\n", pll->vco_freq_min);
drivers/video/fbdev/matrox/matroxfb_misc.c
147
printk(KERN_ERR "in_div_min: %d\n", pll->in_div_min);
drivers/video/fbdev/matrox/matroxfb_misc.c
148
printk(KERN_ERR "in_div_max: %d\n", pll->in_div_max);
drivers/video/fbdev/matrox/matroxfb_misc.c
149
printk(KERN_ERR "feed_div_min: %d\n", pll->feed_div_min);
drivers/video/fbdev/matrox/matroxfb_misc.c
150
printk(KERN_ERR "feed_div_max: %d\n", pll->feed_div_max);
drivers/video/fbdev/matrox/matroxfb_misc.c
153
for (p = 1; p <= pll->post_shift_max; p++) {
drivers/video/fbdev/matrox/matroxfb_misc.c
158
if (fwant < pll->vco_freq_min) fwant = pll->vco_freq_min;
drivers/video/fbdev/matrox/matroxfb_misc.c
163
if (fwant < pll->vco_freq_min) break;
drivers/video/fbdev/matrox/matroxfb_misc.c
164
for (m = pll->in_div_min; m <= pll->in_div_max; m++) {
drivers/video/fbdev/matrox/matroxfb_misc.c
169
if (n > pll->feed_div_max)
drivers/video/fbdev/matrox/matroxfb_misc.c
171
if (n < pll->feed_div_min)
drivers/video/fbdev/matrox/matroxfb_misc.c
172
n = pll->feed_div_min;
drivers/video/fbdev/matrox/matroxfb_misc.c
545
minfo->values.pll.system = get_unaligned_le16(bd->pins + 28) ?
drivers/video/fbdev/matrox/matroxfb_misc.c
548
minfo->features.pll.ref_freq = 14318;
drivers/video/fbdev/matrox/matroxfb_misc.c
557
minfo->values.pll.system = 50000;
drivers/video/fbdev/matrox/matroxfb_misc.c
558
minfo->features.pll.ref_freq = 14318;
drivers/video/fbdev/matrox/matroxfb_misc.c
571
minfo->values.pll.system = (bd->pins[43] == 0xFF) ? 50000 : ((bd->pins[43] + 100) * 1000);
drivers/video/fbdev/matrox/matroxfb_misc.c
572
minfo->features.pll.ref_freq = 14318;
drivers/video/fbdev/matrox/matroxfb_misc.c
582
minfo->values.pll.system = 50000;
drivers/video/fbdev/matrox/matroxfb_misc.c
583
minfo->features.pll.ref_freq = 14318;
drivers/video/fbdev/matrox/matroxfb_misc.c
600
minfo->features.pll.ref_freq = (bd->pins[52] & 0x20) ? 14318 : 27000;
drivers/video/fbdev/matrox/matroxfb_misc.c
613
minfo->features.pll.ref_freq = 27000;
drivers/video/fbdev/matrox/matroxfb_misc.c
630
minfo->values.pll.system = (bd->pins[ 65] == 0xFF) ? 200000 : bd->pins[ 65] * 4000;
drivers/video/fbdev/matrox/matroxfb_misc.c
631
minfo->features.pll.ref_freq = (bd->pins[ 92] & 0x01) ? 14318 : 27000;
drivers/video/fbdev/matrox/matroxfb_misc.c
644
minfo->values.pll.system = 200000;
drivers/video/fbdev/matrox/matroxfb_misc.c
645
minfo->features.pll.ref_freq = 27000;
drivers/video/fbdev/matrox/matroxfb_misc.c
661
minfo->values.pll.system =
drivers/video/fbdev/matrox/matroxfb_misc.c
662
minfo->values.pll.video = (bd->pins[ 92] == 0xFF) ? 284000 : bd->pins[ 92] * 4000;
drivers/video/fbdev/matrox/matroxfb_misc.c
669
minfo->features.pll.ref_freq = (bd->pins[110] & 0x01) ? 14318 : 27000;
drivers/video/fbdev/matrox/matroxfb_misc.c
697
minfo->values.pll.system =
drivers/video/fbdev/matrox/matroxfb_misc.c
698
minfo->values.pll.video = 284000;
drivers/video/fbdev/matrox/matroxfb_misc.c
706
minfo->features.pll.ref_freq = 27000;
drivers/video/fbdev/matrox/matroxfb_misc.h
15
return matroxfb_PLL_calcclock(&minfo->features.pll, freq, fmax, in, feed, post);
drivers/video/fbdev/matrox/matroxfb_misc.h
8
int matroxfb_PLL_calcclock(const struct matrox_pll_features* pll, unsigned int freq, unsigned int fmax,
drivers/video/fbdev/nvidia/nv_hw.c
144
unsigned int pll, N, M, MB, NB, P;
drivers/video/fbdev/nvidia/nv_hw.c
147
pll = NV_RD32(par->PMC, 0x4020);
drivers/video/fbdev/nvidia/nv_hw.c
148
P = (pll >> 16) & 0x07;
drivers/video/fbdev/nvidia/nv_hw.c
149
pll = NV_RD32(par->PMC, 0x4024);
drivers/video/fbdev/nvidia/nv_hw.c
150
M = pll & 0xFF;
drivers/video/fbdev/nvidia/nv_hw.c
151
N = (pll >> 8) & 0xFF;
drivers/video/fbdev/nvidia/nv_hw.c
157
MB = (pll >> 16) & 0xFF;
drivers/video/fbdev/nvidia/nv_hw.c
158
NB = (pll >> 24) & 0xFF;
drivers/video/fbdev/nvidia/nv_hw.c
162
pll = NV_RD32(par->PMC, 0x4000);
drivers/video/fbdev/nvidia/nv_hw.c
163
P = (pll >> 16) & 0x07;
drivers/video/fbdev/nvidia/nv_hw.c
164
pll = NV_RD32(par->PMC, 0x4004);
drivers/video/fbdev/nvidia/nv_hw.c
165
M = pll & 0xFF;
drivers/video/fbdev/nvidia/nv_hw.c
166
N = (pll >> 8) & 0xFF;
drivers/video/fbdev/nvidia/nv_hw.c
167
MB = (pll >> 16) & 0xFF;
drivers/video/fbdev/nvidia/nv_hw.c
168
NB = (pll >> 24) & 0xFF;
drivers/video/fbdev/nvidia/nv_hw.c
172
pll = NV_RD32(par->PRAMDAC0, 0x0504);
drivers/video/fbdev/nvidia/nv_hw.c
173
M = pll & 0xFF;
drivers/video/fbdev/nvidia/nv_hw.c
174
N = (pll >> 8) & 0xFF;
drivers/video/fbdev/nvidia/nv_hw.c
175
P = (pll >> 16) & 0x0F;
drivers/video/fbdev/nvidia/nv_hw.c
176
pll = NV_RD32(par->PRAMDAC0, 0x0574);
drivers/video/fbdev/nvidia/nv_hw.c
177
if (pll & 0x80000000) {
drivers/video/fbdev/nvidia/nv_hw.c
178
MB = pll & 0xFF;
drivers/video/fbdev/nvidia/nv_hw.c
179
NB = (pll >> 8) & 0xFF;
drivers/video/fbdev/nvidia/nv_hw.c
186
pll = NV_RD32(par->PRAMDAC0, 0x0500);
drivers/video/fbdev/nvidia/nv_hw.c
187
M = pll & 0xFF;
drivers/video/fbdev/nvidia/nv_hw.c
188
N = (pll >> 8) & 0xFF;
drivers/video/fbdev/nvidia/nv_hw.c
189
P = (pll >> 16) & 0x0F;
drivers/video/fbdev/nvidia/nv_hw.c
190
pll = NV_RD32(par->PRAMDAC0, 0x0570);
drivers/video/fbdev/nvidia/nv_hw.c
191
if (pll & 0x80000000) {
drivers/video/fbdev/nvidia/nv_hw.c
192
MB = pll & 0xFF;
drivers/video/fbdev/nvidia/nv_hw.c
193
NB = (pll >> 8) & 0xFF;
drivers/video/fbdev/nvidia/nv_hw.c
202
pll = NV_RD32(par->PRAMDAC0, 0x0504);
drivers/video/fbdev/nvidia/nv_hw.c
203
M = pll & 0x0F;
drivers/video/fbdev/nvidia/nv_hw.c
204
N = (pll >> 8) & 0xFF;
drivers/video/fbdev/nvidia/nv_hw.c
205
P = (pll >> 16) & 0x07;
drivers/video/fbdev/nvidia/nv_hw.c
206
if (pll & 0x00000080) {
drivers/video/fbdev/nvidia/nv_hw.c
207
MB = (pll >> 4) & 0x07;
drivers/video/fbdev/nvidia/nv_hw.c
208
NB = (pll >> 19) & 0x1f;
drivers/video/fbdev/nvidia/nv_hw.c
215
pll = NV_RD32(par->PRAMDAC0, 0x0500);
drivers/video/fbdev/nvidia/nv_hw.c
216
M = pll & 0x0F;
drivers/video/fbdev/nvidia/nv_hw.c
217
N = (pll >> 8) & 0xFF;
drivers/video/fbdev/nvidia/nv_hw.c
218
P = (pll >> 16) & 0x07;
drivers/video/fbdev/nvidia/nv_hw.c
219
if (pll & 0x00000080) {
drivers/video/fbdev/nvidia/nv_hw.c
220
MB = (pll >> 4) & 0x07;
drivers/video/fbdev/nvidia/nv_hw.c
221
NB = (pll >> 19) & 0x1f;
drivers/video/fbdev/nvidia/nv_hw.c
228
pll = NV_RD32(par->PRAMDAC0, 0x0504);
drivers/video/fbdev/nvidia/nv_hw.c
229
M = pll & 0xFF;
drivers/video/fbdev/nvidia/nv_hw.c
230
N = (pll >> 8) & 0xFF;
drivers/video/fbdev/nvidia/nv_hw.c
231
P = (pll >> 16) & 0x0F;
drivers/video/fbdev/nvidia/nv_hw.c
234
pll = NV_RD32(par->PRAMDAC0, 0x0500);
drivers/video/fbdev/nvidia/nv_hw.c
235
M = pll & 0xFF;
drivers/video/fbdev/nvidia/nv_hw.c
236
N = (pll >> 8) & 0xFF;
drivers/video/fbdev/nvidia/nv_hw.c
237
P = (pll >> 16) & 0x0F;
drivers/video/fbdev/nvidia/nv_hw.c
684
unsigned int M, N, P, pll, MClk, NVClk, memctrl;
drivers/video/fbdev/nvidia/nv_hw.c
703
pll = NV_RD32(par->PRAMDAC0, 0x0500);
drivers/video/fbdev/nvidia/nv_hw.c
704
M = (pll >> 0) & 0xFF;
drivers/video/fbdev/nvidia/nv_hw.c
705
N = (pll >> 8) & 0xFF;
drivers/video/fbdev/nvidia/nv_hw.c
706
P = (pll >> 16) & 0x0F;
drivers/video/fbdev/nvidia/nv_hw.c
874
CalcVClock2Stage(dotClock, &VClk, &state->pll, &state->pllB,
drivers/video/fbdev/nvidia/nv_hw.c
877
CalcVClock(dotClock, &VClk, &state->pll, par);
drivers/video/fbdev/nvidia/nv_type.h
69
u32 pll;
drivers/video/fbdev/nvidia/nvidia.c
435
state->vpll = state->pll;
drivers/video/fbdev/nvidia/nvidia.c
436
state->vpll2 = state->pll;
drivers/video/fbdev/omap2/omapfb/dss/dispc.c
3187
struct dss_pll *pll;
drivers/video/fbdev/omap2/omapfb/dss/dispc.c
3195
pll = dss_pll_find("dsi0");
drivers/video/fbdev/omap2/omapfb/dss/dispc.c
3196
if (!pll)
drivers/video/fbdev/omap2/omapfb/dss/dispc.c
3197
pll = dss_pll_find("video0");
drivers/video/fbdev/omap2/omapfb/dss/dispc.c
3199
r = pll->cinfo.clkout[0];
drivers/video/fbdev/omap2/omapfb/dss/dispc.c
3202
pll = dss_pll_find("dsi1");
drivers/video/fbdev/omap2/omapfb/dss/dispc.c
3203
if (!pll)
drivers/video/fbdev/omap2/omapfb/dss/dispc.c
3204
pll = dss_pll_find("video1");
drivers/video/fbdev/omap2/omapfb/dss/dispc.c
3206
r = pll->cinfo.clkout[0];
drivers/video/fbdev/omap2/omapfb/dss/dispc.c
3218
struct dss_pll *pll;
drivers/video/fbdev/omap2/omapfb/dss/dispc.c
3233
pll = dss_pll_find("dsi0");
drivers/video/fbdev/omap2/omapfb/dss/dispc.c
3234
if (!pll)
drivers/video/fbdev/omap2/omapfb/dss/dispc.c
3235
pll = dss_pll_find("video0");
drivers/video/fbdev/omap2/omapfb/dss/dispc.c
3237
r = pll->cinfo.clkout[0];
drivers/video/fbdev/omap2/omapfb/dss/dispc.c
3240
pll = dss_pll_find("dsi1");
drivers/video/fbdev/omap2/omapfb/dss/dispc.c
3241
if (!pll)
drivers/video/fbdev/omap2/omapfb/dss/dispc.c
3242
pll = dss_pll_find("video1");
drivers/video/fbdev/omap2/omapfb/dss/dispc.c
3244
r = pll->cinfo.clkout[0];
drivers/video/fbdev/omap2/omapfb/dss/dpi.c
132
struct dss_pll *pll;
drivers/video/fbdev/omap2/omapfb/dss/dpi.c
204
return dss_pll_hsdiv_calc(ctx->pll, clkdco,
drivers/video/fbdev/omap2/omapfb/dss/dpi.c
226
ctx->pll = dpi->pll;
drivers/video/fbdev/omap2/omapfb/dss/dpi.c
233
clkin = clk_get_rate(ctx->pll->clkin);
drivers/video/fbdev/omap2/omapfb/dss/dpi.c
235
return dss_pll_calc(ctx->pll, clkin,
drivers/video/fbdev/omap2/omapfb/dss/dpi.c
283
r = dss_pll_set_config(dpi->pll, &ctx.dsi_cinfo);
drivers/video/fbdev/omap2/omapfb/dss/dpi.c
333
if (dpi->pll)
drivers/video/fbdev/omap2/omapfb/dss/dpi.c
37
struct dss_pll *pll;
drivers/video/fbdev/omap2/omapfb/dss/dpi.c
407
if (dpi->pll) {
drivers/video/fbdev/omap2/omapfb/dss/dpi.c
408
r = dss_pll_enable(dpi->pll);
drivers/video/fbdev/omap2/omapfb/dss/dpi.c
431
if (dpi->pll)
drivers/video/fbdev/omap2/omapfb/dss/dpi.c
432
dss_pll_disable(dpi->pll);
drivers/video/fbdev/omap2/omapfb/dss/dpi.c
455
if (dpi->pll) {
drivers/video/fbdev/omap2/omapfb/dss/dpi.c
457
dss_pll_disable(dpi->pll);
drivers/video/fbdev/omap2/omapfb/dss/dpi.c
511
if (dpi->pll) {
drivers/video/fbdev/omap2/omapfb/dss/dpi.c
546
static int dpi_verify_dsi_pll(struct dss_pll *pll)
drivers/video/fbdev/omap2/omapfb/dss/dpi.c
552
r = dss_pll_enable(pll);
drivers/video/fbdev/omap2/omapfb/dss/dpi.c
556
dss_pll_disable(pll);
drivers/video/fbdev/omap2/omapfb/dss/dpi.c
585
struct dss_pll *pll;
drivers/video/fbdev/omap2/omapfb/dss/dpi.c
587
if (dpi->pll)
drivers/video/fbdev/omap2/omapfb/dss/dpi.c
590
pll = dpi_get_pll(dpi->output.dispc_channel);
drivers/video/fbdev/omap2/omapfb/dss/dpi.c
591
if (!pll)
drivers/video/fbdev/omap2/omapfb/dss/dpi.c
596
dss_ctrl_pll_set_control_mux(pll->id, dpi->output.dispc_channel);
drivers/video/fbdev/omap2/omapfb/dss/dpi.c
598
if (dpi_verify_dsi_pll(pll)) {
drivers/video/fbdev/omap2/omapfb/dss/dpi.c
603
dpi->pll = pll;
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
1232
return dsi->pll.cinfo.clkout[HSDIV_DISPC];
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
1239
return dsi->pll.cinfo.clkout[HSDIV_DSI];
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
1246
return dsi->pll.cinfo.clkdco / 16;
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
1376
static int dsi_pll_enable(struct dss_pll *pll)
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
1378
struct dsi_data *dsi = container_of(pll, struct dsi_data, pll);
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
1454
static void dsi_pll_disable(struct dss_pll *pll)
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
1456
struct dsi_data *dsi = container_of(pll, struct dsi_data, pll);
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
1466
struct dss_pll_clock_info *cinfo = &dsi->pll.cinfo;
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
1469
struct dss_pll *pll = &dsi->pll;
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
1479
seq_printf(s, "dsi pll clkin\t%lu\n", clk_get_rate(pll->clkin));
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
1860
unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4;
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
1868
unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4;
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
269
struct dss_pll *pll;
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
311
struct dss_pll pll;
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
4167
r = dss_pll_set_config(&dsi->pll, &cinfo);
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
4181
r = dss_pll_enable(&dsi->pll);
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
4225
dss_pll_disable(&dsi->pll);
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
4446
return dss_pll_hsdiv_calc(ctx->pll, clkdco, ctx->req_pck_min,
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
4460
clkin = clk_get_rate(dsi->pll.clkin);
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
4476
ctx->pll = &dsi->pll;
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
4485
return dss_pll_calc(ctx->pll, clkin,
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
4744
return dss_pll_hsdiv_calc(ctx->pll, clkdco, ctx->req_pck_min,
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
4761
clkin = clk_get_rate(dsi->pll.clkin);
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
4765
ctx->pll = &dsi->pll;
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
4786
return dss_pll_calc(ctx->pll, clkin,
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
5212
struct dss_pll *pll = &dsi->pll;
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
5222
pll->name = dsi->module_id == 0 ? "dsi0" : "dsi1";
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
5223
pll->id = dsi->module_id == 0 ? DSS_PLL_DSI1 : DSS_PLL_DSI2;
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
5224
pll->clkin = clk;
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
5225
pll->base = dsi->pll_base;
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
5232
pll->hw = &dss_omap3_dsi_pll_hw;
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
5238
pll->hw = &dss_omap4_dsi_pll_hw;
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
5242
pll->hw = &dss_omap5_dsi_pll_hw;
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
5249
pll->ops = &dsi_pll_ops;
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
5251
r = dss_pll_register(pll);
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
5477
dss_pll_unregister(&dsi->pll);
drivers/video/fbdev/omap2/omapfb/dss/dss.h
123
int (*enable)(struct dss_pll *pll);
drivers/video/fbdev/omap2/omapfb/dss/dss.h
124
void (*disable)(struct dss_pll *pll);
drivers/video/fbdev/omap2/omapfb/dss/dss.h
125
int (*set_config)(struct dss_pll *pll,
drivers/video/fbdev/omap2/omapfb/dss/dss.h
264
void dss_video_pll_uninit(struct dss_pll *pll);
drivers/video/fbdev/omap2/omapfb/dss/dss.h
459
int dss_pll_register(struct dss_pll *pll);
drivers/video/fbdev/omap2/omapfb/dss/dss.h
460
void dss_pll_unregister(struct dss_pll *pll);
drivers/video/fbdev/omap2/omapfb/dss/dss.h
462
int dss_pll_enable(struct dss_pll *pll);
drivers/video/fbdev/omap2/omapfb/dss/dss.h
463
void dss_pll_disable(struct dss_pll *pll);
drivers/video/fbdev/omap2/omapfb/dss/dss.h
464
int dss_pll_set_config(struct dss_pll *pll,
drivers/video/fbdev/omap2/omapfb/dss/dss.h
467
bool dss_pll_hsdiv_calc(const struct dss_pll *pll, unsigned long clkdco,
drivers/video/fbdev/omap2/omapfb/dss/dss.h
470
bool dss_pll_calc(const struct dss_pll *pll, unsigned long clkin,
drivers/video/fbdev/omap2/omapfb/dss/dss.h
473
int dss_pll_write_config_type_a(struct dss_pll *pll,
drivers/video/fbdev/omap2/omapfb/dss/dss.h
475
int dss_pll_write_config_type_b(struct dss_pll *pll,
drivers/video/fbdev/omap2/omapfb/dss/dss.h
477
int dss_pll_wait_reset_done(struct dss_pll *pll);
drivers/video/fbdev/omap2/omapfb/dss/hdmi.h
229
struct dss_pll pll;
drivers/video/fbdev/omap2/omapfb/dss/hdmi.h
298
void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s);
drivers/video/fbdev/omap2/omapfb/dss/hdmi.h
299
void hdmi_pll_compute(struct hdmi_pll_data *pll,
drivers/video/fbdev/omap2/omapfb/dss/hdmi.h
301
int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll,
drivers/video/fbdev/omap2/omapfb/dss/hdmi.h
335
struct hdmi_pll_data pll;
drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c
163
hdmi_pll_compute(&hdmi.pll, p->pixelclock, &hdmi_cinfo);
drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c
165
r = dss_pll_enable(&hdmi.pll.pll);
drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c
171
r = dss_pll_set_config(&hdmi.pll.pll, &hdmi_cinfo);
drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c
216
dss_pll_disable(&hdmi.pll.pll);
drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c
234
dss_pll_disable(&hdmi.pll.pll);
drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c
278
hdmi_pll_dump(&hdmi.pll, s);
drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c
689
r = hdmi_pll_init(pdev, &hdmi.pll, &hdmi.wp);
drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c
732
hdmi_pll_uninit(&hdmi.pll);
drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c
745
hdmi_pll_uninit(&hdmi.pll);
drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c
175
hdmi_pll_compute(&hdmi.pll, p->pixelclock, &hdmi_cinfo);
drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c
182
r = dss_pll_enable(&hdmi.pll.pll);
drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c
188
r = dss_pll_set_config(&hdmi.pll.pll, &hdmi_cinfo);
drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c
233
dss_pll_disable(&hdmi.pll.pll);
drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c
251
dss_pll_disable(&hdmi.pll.pll);
drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c
299
hdmi_pll_dump(&hdmi.pll, s);
drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c
730
r = hdmi_pll_init(pdev, &hdmi.pll, &hdmi.wp);
drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c
773
hdmi_pll_uninit(&hdmi.pll);
drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c
786
hdmi_pll_uninit(&hdmi.pll);
drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c
101
struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll);
drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c
102
struct hdmi_wp_data *wp = pll->wp;
drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c
111
struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll);
drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c
112
struct hdmi_wp_data *wp = pll->wp;
drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c
174
struct dss_pll *pll = &hpll->pll;
drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c
183
pll->name = "hdmi";
drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c
184
pll->id = DSS_PLL_HDMI;
drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c
185
pll->base = hpll->base;
drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c
186
pll->clkin = clk;
drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c
192
pll->hw = &dss_omap4_hdmi_pll_hw;
drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c
197
pll->hw = &dss_omap5_hdmi_pll_hw;
drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c
204
pll->ops = &dsi_pll_ops;
drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c
205
return dss_pll_register(pll);
drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c
208
int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll,
drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c
213
pll->wp = wp;
drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c
215
pll->base = devm_platform_ioremap_resource_byname(pdev, "pll");
drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c
216
if (IS_ERR(pll->base)) {
drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c
218
return PTR_ERR(pll->base);
drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c
221
r = dsi_init_pll_data(pdev, pll);
drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c
23
void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s)
drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c
232
struct dss_pll *pll = &hpll->pll;
drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c
234
dss_pll_unregister(pll);
drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c
26
hdmi_read_reg(pll->base, r))
drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c
39
void hdmi_pll_compute(struct hdmi_pll_data *pll,
drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c
47
const struct dss_pll_hw *hw = pll->pll.hw;
drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c
49
clkin = clk_get_rate(pll->pll.clkin);
drivers/video/fbdev/omap2/omapfb/dss/pll.c
100
if (pll->regulator)
drivers/video/fbdev/omap2/omapfb/dss/pll.c
101
regulator_disable(pll->regulator);
drivers/video/fbdev/omap2/omapfb/dss/pll.c
103
clk_disable_unprepare(pll->clkin);
drivers/video/fbdev/omap2/omapfb/dss/pll.c
105
memset(&pll->cinfo, 0, sizeof(pll->cinfo));
drivers/video/fbdev/omap2/omapfb/dss/pll.c
108
int dss_pll_set_config(struct dss_pll *pll, const struct dss_pll_clock_info *cinfo)
drivers/video/fbdev/omap2/omapfb/dss/pll.c
112
r = pll->ops->set_config(pll, cinfo);
drivers/video/fbdev/omap2/omapfb/dss/pll.c
116
pll->cinfo = *cinfo;
drivers/video/fbdev/omap2/omapfb/dss/pll.c
121
bool dss_pll_hsdiv_calc(const struct dss_pll *pll, unsigned long clkdco,
drivers/video/fbdev/omap2/omapfb/dss/pll.c
125
const struct dss_pll_hw *hw = pll->hw;
drivers/video/fbdev/omap2/omapfb/dss/pll.c
146
bool dss_pll_calc(const struct dss_pll *pll, unsigned long clkin,
drivers/video/fbdev/omap2/omapfb/dss/pll.c
150
const struct dss_pll_hw *hw = pll->hw;
drivers/video/fbdev/omap2/omapfb/dss/pll.c
214
int dss_pll_wait_reset_done(struct dss_pll *pll)
drivers/video/fbdev/omap2/omapfb/dss/pll.c
216
void __iomem *base = pll->base;
drivers/video/fbdev/omap2/omapfb/dss/pll.c
224
static int dss_wait_hsdiv_ack(struct dss_pll *pll, u32 hsdiv_ack_mask)
drivers/video/fbdev/omap2/omapfb/dss/pll.c
229
u32 v = readl_relaxed(pll->base + PLL_STATUS);
drivers/video/fbdev/omap2/omapfb/dss/pll.c
238
int dss_pll_write_config_type_a(struct dss_pll *pll,
drivers/video/fbdev/omap2/omapfb/dss/pll.c
241
const struct dss_pll_hw *hw = pll->hw;
drivers/video/fbdev/omap2/omapfb/dss/pll.c
242
void __iomem *base = pll->base;
drivers/video/fbdev/omap2/omapfb/dss/pll.c
30
int dss_pll_register(struct dss_pll *pll)
drivers/video/fbdev/omap2/omapfb/dss/pll.c
316
r = dss_wait_hsdiv_ack(pll,
drivers/video/fbdev/omap2/omapfb/dss/pll.c
330
int dss_pll_write_config_type_b(struct dss_pll *pll,
drivers/video/fbdev/omap2/omapfb/dss/pll.c
333
const struct dss_pll_hw *hw = pll->hw;
drivers/video/fbdev/omap2/omapfb/dss/pll.c
334
void __iomem *base = pll->base;
drivers/video/fbdev/omap2/omapfb/dss/pll.c
36
dss_plls[i] = pll;
drivers/video/fbdev/omap2/omapfb/dss/pll.c
44
void dss_pll_unregister(struct dss_pll *pll)
drivers/video/fbdev/omap2/omapfb/dss/pll.c
49
if (dss_plls[i] == pll) {
drivers/video/fbdev/omap2/omapfb/dss/pll.c
68
int dss_pll_enable(struct dss_pll *pll)
drivers/video/fbdev/omap2/omapfb/dss/pll.c
72
r = clk_prepare_enable(pll->clkin);
drivers/video/fbdev/omap2/omapfb/dss/pll.c
76
if (pll->regulator) {
drivers/video/fbdev/omap2/omapfb/dss/pll.c
77
r = regulator_enable(pll->regulator);
drivers/video/fbdev/omap2/omapfb/dss/pll.c
82
r = pll->ops->enable(pll);
drivers/video/fbdev/omap2/omapfb/dss/pll.c
89
if (pll->regulator)
drivers/video/fbdev/omap2/omapfb/dss/pll.c
90
regulator_disable(pll->regulator);
drivers/video/fbdev/omap2/omapfb/dss/pll.c
92
clk_disable_unprepare(pll->clkin);
drivers/video/fbdev/omap2/omapfb/dss/pll.c
96
void dss_pll_disable(struct dss_pll *pll)
drivers/video/fbdev/omap2/omapfb/dss/pll.c
98
pll->ops->disable(pll);
drivers/video/fbdev/omap2/omapfb/dss/video-pll.c
135
struct dss_pll *pll;
drivers/video/fbdev/omap2/omapfb/dss/video-pll.c
169
pll = &vpll->pll;
drivers/video/fbdev/omap2/omapfb/dss/video-pll.c
171
pll->name = id == 0 ? "video0" : "video1";
drivers/video/fbdev/omap2/omapfb/dss/video-pll.c
172
pll->id = id == 0 ? DSS_PLL_VIDEO1 : DSS_PLL_VIDEO2;
drivers/video/fbdev/omap2/omapfb/dss/video-pll.c
173
pll->clkin = clk;
drivers/video/fbdev/omap2/omapfb/dss/video-pll.c
174
pll->regulator = regulator;
drivers/video/fbdev/omap2/omapfb/dss/video-pll.c
175
pll->base = pll_base;
drivers/video/fbdev/omap2/omapfb/dss/video-pll.c
176
pll->hw = &dss_dra7_video_pll_hw;
drivers/video/fbdev/omap2/omapfb/dss/video-pll.c
177
pll->ops = &dss_pll_ops;
drivers/video/fbdev/omap2/omapfb/dss/video-pll.c
179
r = dss_pll_register(pll);
drivers/video/fbdev/omap2/omapfb/dss/video-pll.c
183
return pll;
drivers/video/fbdev/omap2/omapfb/dss/video-pll.c
186
void dss_video_pll_uninit(struct dss_pll *pll)
drivers/video/fbdev/omap2/omapfb/dss/video-pll.c
188
dss_pll_unregister(pll);
drivers/video/fbdev/omap2/omapfb/dss/video-pll.c
20
struct dss_pll pll;
drivers/video/fbdev/omap2/omapfb/dss/video-pll.c
56
static int dss_video_pll_enable(struct dss_pll *pll)
drivers/video/fbdev/omap2/omapfb/dss/video-pll.c
58
struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll);
drivers/video/fbdev/omap2/omapfb/dss/video-pll.c
65
dss_ctrl_pll_enable(pll->id, true);
drivers/video/fbdev/omap2/omapfb/dss/video-pll.c
69
r = dss_pll_wait_reset_done(pll);
drivers/video/fbdev/omap2/omapfb/dss/video-pll.c
79
dss_ctrl_pll_enable(pll->id, false);
drivers/video/fbdev/omap2/omapfb/dss/video-pll.c
85
static void dss_video_pll_disable(struct dss_pll *pll)
drivers/video/fbdev/omap2/omapfb/dss/video-pll.c
87
struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll);
drivers/video/fbdev/omap2/omapfb/dss/video-pll.c
93
dss_ctrl_pll_enable(pll->id, false);
drivers/video/fbdev/riva/riva_hw.c
1054
unsigned int M, N, P, pll, MClk, NVClk, cfg1;
drivers/video/fbdev/riva/riva_hw.c
1056
pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0);
drivers/video/fbdev/riva/riva_hw.c
1057
M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
drivers/video/fbdev/riva/riva_hw.c
1059
pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0);
drivers/video/fbdev/riva/riva_hw.c
1060
M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
drivers/video/fbdev/riva/riva_hw.c
1100
unsigned int M, N, P, pll, MClk, NVClk;
drivers/video/fbdev/riva/riva_hw.c
1113
pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0);
drivers/video/fbdev/riva/riva_hw.c
1114
M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
drivers/video/fbdev/riva/riva_hw.c
621
unsigned int M, N, P, pll, MClk;
drivers/video/fbdev/riva/riva_hw.c
623
pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0);
drivers/video/fbdev/riva/riva_hw.c
624
M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
drivers/video/fbdev/riva/riva_hw.c
805
unsigned int M, N, P, pll, MClk, NVClk, cfg1;
drivers/video/fbdev/riva/riva_hw.c
807
pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0);
drivers/video/fbdev/riva/riva_hw.c
808
M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
drivers/video/fbdev/riva/riva_hw.c
810
pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0);
drivers/video/fbdev/riva/riva_hw.c
811
M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
drivers/video/fbdev/sstfb.c
362
if (sst_calc_pll(PICOS2KHZ(var->pixclock), &freq, &par->pll)) {
drivers/video/fbdev/sstfb.c
494
sst_calc_pll(PICOS2KHZ(info->var.pixclock), &freq, &par->pll);
drivers/video/fbdev/sstfb.c
548
par->dac_sw.set_pll(info, &par->pll, VID_CLOCK);
drivers/video/fbdev/via/via_clock.c
21
static inline u32 cle266_encode_pll(struct via_pll_config pll)
drivers/video/fbdev/via/via_clock.c
23
return (pll.multiplier << 8)
drivers/video/fbdev/via/via_clock.c
24
| (pll.rshift << 6)
drivers/video/fbdev/via/via_clock.c
25
| pll.divisor;
drivers/video/fbdev/via/via_clock.c
28
static inline u32 k800_encode_pll(struct via_pll_config pll)
drivers/video/fbdev/via/via_clock.c
30
return ((pll.divisor - 2) << 16)
drivers/video/fbdev/via/via_clock.c
31
| (pll.rshift << 10)
drivers/video/fbdev/via/via_clock.c
32
| (pll.multiplier - 2);
drivers/video/fbdev/via/via_clock.c
35
static inline u32 vx855_encode_pll(struct via_pll_config pll)
drivers/video/fbdev/via/via_clock.c
37
return (pll.divisor << 16)
drivers/video/fbdev/via/via_clock.c
38
| (pll.rshift << 10)
drivers/video/fbdev/via/via_clock.c
39
| pll.multiplier;
drivers/video/fbdev/via/via_clock.h
48
struct via_pll_config pll)
drivers/video/fbdev/via/via_clock.h
50
return ref_freq / pll.divisor * pll.multiplier;
drivers/video/fbdev/via/via_clock.h
54
struct via_pll_config pll)
drivers/video/fbdev/via/via_clock.h
56
return get_pll_internal_frequency(ref_freq, pll) >> pll.rshift;
include/linux/clk/renesas.h
149
struct rzv2h_pll_pars pll;
include/linux/mfd/twl6040.h
198
int pll;
include/linux/svga.h
118
int svga_compute_pll(const struct svga_pll *pll, u32 f_wanted, u16 *m, u16 *n, u16 *r, int node);
include/video/sstfb.h
346
struct pll_timing pll;
sound/soc/codecs/adav80x.c
46
#define ADAV80X_PLL_CLK_SRC_PLL_XIN(pll) 0x00
sound/soc/codecs/adav80x.c
47
#define ADAV80X_PLL_CLK_SRC_PLL_MCLKI(pll) (0x40 << (pll))
sound/soc/codecs/adav80x.c
48
#define ADAV80X_PLL_CLK_SRC_PLL_MASK(pll) (0x40 << (pll))
sound/soc/codecs/adav80x.c
56
#define ADAV80X_PLL_CTRL1_PLLPD(pll) (0x04 << (pll))
sound/soc/codecs/adav80x.c
59
#define ADAV80X_PLL_CTRL2_FIELD(pll, x) ((x) << ((pll) * 4))
sound/soc/codecs/adav80x.c
61
#define ADAV80X_PLL_CTRL2_FS_48(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x00)
sound/soc/codecs/adav80x.c
62
#define ADAV80X_PLL_CTRL2_FS_32(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x08)
sound/soc/codecs/adav80x.c
63
#define ADAV80X_PLL_CTRL2_FS_44(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x0c)
sound/soc/codecs/adav80x.c
65
#define ADAV80X_PLL_CTRL2_SEL(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x02)
sound/soc/codecs/adav80x.c
66
#define ADAV80X_PLL_CTRL2_DOUB(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x01)
sound/soc/codecs/adav80x.c
67
#define ADAV80X_PLL_CTRL2_PLL_MASK(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x0f)
sound/soc/codecs/ak4642.c
340
u8 pll;
sound/soc/codecs/ak4642.c
345
pll = PLL2;
sound/soc/codecs/ak4642.c
348
pll = PLL2 | PLL0;
sound/soc/codecs/ak4642.c
351
pll = PLL2 | PLL1;
sound/soc/codecs/ak4642.c
354
pll = PLL2 | PLL1 | PLL0;
sound/soc/codecs/ak4642.c
357
pll = PLL3 | PLL2;
sound/soc/codecs/ak4642.c
360
pll = PLL3 | PLL2 | PLL0;
sound/soc/codecs/ak4642.c
363
pll = PLL3;
sound/soc/codecs/ak4642.c
367
pll = PLL3 | PLL2 | PLL1;
sound/soc/codecs/ak4642.c
371
pll = PLL3 | PLL2 | PLL1 | PLL0;
sound/soc/codecs/ak4642.c
381
snd_soc_component_update_bits(component, MD_CTL1, PLL_MASK, pll);
sound/soc/codecs/ak4671.c
472
u8 pll;
sound/soc/codecs/ak4671.c
474
pll = snd_soc_component_read(component, AK4671_PLL_MODE_SELECT0);
sound/soc/codecs/ak4671.c
475
pll &= ~AK4671_PLL;
sound/soc/codecs/ak4671.c
479
pll |= AK4671_PLL_11_2896MHZ;
sound/soc/codecs/ak4671.c
482
pll |= AK4671_PLL_12MHZ;
sound/soc/codecs/ak4671.c
485
pll |= AK4671_PLL_12_288MHZ;
sound/soc/codecs/ak4671.c
488
pll |= AK4671_PLL_13MHZ;
sound/soc/codecs/ak4671.c
491
pll |= AK4671_PLL_13_5MHZ;
sound/soc/codecs/ak4671.c
494
pll |= AK4671_PLL_19_2MHZ;
sound/soc/codecs/ak4671.c
497
pll |= AK4671_PLL_24MHZ;
sound/soc/codecs/ak4671.c
500
pll |= AK4671_PLL_26MHZ;
sound/soc/codecs/ak4671.c
503
pll |= AK4671_PLL_27MHZ;
sound/soc/codecs/ak4671.c
509
snd_soc_component_write(component, AK4671_PLL_MODE_SELECT0, pll);
sound/soc/codecs/max98090.c
2152
unsigned int pll;
sound/soc/codecs/max98090.c
2178
pll = snd_soc_component_read(
sound/soc/codecs/max98090.c
2180
if (!(pll & M98090_ULK_MASK))
sound/soc/codecs/nau8810.c
575
struct nau8810_pll *pll_param = &nau8810->pll;
sound/soc/codecs/nau8810.h
281
struct nau8810_pll pll;
sound/soc/codecs/nau8822.c
663
struct nau8822_pll *pll = &nau8822->pll;
sound/soc/codecs/nau8822.c
694
if (pll->mclk_scaler != div) {
sound/soc/codecs/nau8822.c
719
struct nau8822_pll *pll_param = &nau8822->pll;
sound/soc/codecs/nau8822.c
938
div = nau8822->pll.mclk_scaler;
sound/soc/codecs/nau8822.h
221
struct nau8822_pll pll;
sound/soc/codecs/tlv320aic32x4-clk.c
100
ret = regmap_read(pll->regmap, AIC32X4_PLLDLSB, &val);
sound/soc/codecs/tlv320aic32x4-clk.c
108
static int clk_aic32x4_pll_set_muldiv(struct clk_aic32x4 *pll,
sound/soc/codecs/tlv320aic32x4-clk.c
114
ret = regmap_update_bits(pll->regmap, AIC32X4_PLLPR,
sound/soc/codecs/tlv320aic32x4-clk.c
119
ret = regmap_update_bits(pll->regmap, AIC32X4_PLLPR,
sound/soc/codecs/tlv320aic32x4-clk.c
125
ret = regmap_write(pll->regmap, AIC32X4_PLLJ, settings->j);
sound/soc/codecs/tlv320aic32x4-clk.c
129
ret = regmap_write(pll->regmap, AIC32X4_PLLDMSB, (settings->d >> 8));
sound/soc/codecs/tlv320aic32x4-clk.c
132
ret = regmap_write(pll->regmap, AIC32X4_PLLDLSB, (settings->d & 0xff));
sound/soc/codecs/tlv320aic32x4-clk.c
196
struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
sound/soc/codecs/tlv320aic32x4-clk.c
200
ret = clk_aic32x4_pll_get_muldiv(pll, &settings);
sound/soc/codecs/tlv320aic32x4-clk.c
226
struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
sound/soc/codecs/tlv320aic32x4-clk.c
234
ret = clk_aic32x4_pll_set_muldiv(pll, &settings);
sound/soc/codecs/tlv320aic32x4-clk.c
246
struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
sound/soc/codecs/tlv320aic32x4-clk.c
248
return regmap_update_bits(pll->regmap,
sound/soc/codecs/tlv320aic32x4-clk.c
256
struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
sound/soc/codecs/tlv320aic32x4-clk.c
259
regmap_read(pll->regmap, AIC32X4_PLLPR, &val);
sound/soc/codecs/tlv320aic32x4-clk.c
49
struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
sound/soc/codecs/tlv320aic32x4-clk.c
51
return regmap_update_bits(pll->regmap, AIC32X4_PLLPR,
sound/soc/codecs/tlv320aic32x4-clk.c
57
struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
sound/soc/codecs/tlv320aic32x4-clk.c
59
regmap_update_bits(pll->regmap, AIC32X4_PLLPR,
sound/soc/codecs/tlv320aic32x4-clk.c
65
struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
sound/soc/codecs/tlv320aic32x4-clk.c
70
ret = regmap_read(pll->regmap, AIC32X4_PLLPR, &val);
sound/soc/codecs/tlv320aic32x4-clk.c
77
static int clk_aic32x4_pll_get_muldiv(struct clk_aic32x4 *pll,
sound/soc/codecs/tlv320aic32x4-clk.c
84
ret = regmap_read(pll->regmap, AIC32X4_PLLPR, &val);
sound/soc/codecs/tlv320aic32x4-clk.c
90
ret = regmap_read(pll->regmap, AIC32X4_PLLJ, &val);
sound/soc/codecs/tlv320aic32x4-clk.c
95
ret = regmap_read(pll->regmap, AIC32X4_PLLDMSB, &val);
sound/soc/codecs/tlv320aic32x4.c
601
struct clk *pll;
sound/soc/codecs/tlv320aic32x4.c
603
pll = devm_clk_get(component->dev, "pll");
sound/soc/codecs/tlv320aic32x4.c
604
if (IS_ERR(pll))
sound/soc/codecs/tlv320aic32x4.c
605
return PTR_ERR(pll);
sound/soc/codecs/tlv320aic32x4.c
607
mclk = clk_get_parent(pll);
sound/soc/codecs/tscs454.c
132
struct pll pll1;
sound/soc/codecs/tscs454.c
133
struct pll pll2;
sound/soc/codecs/tscs454.c
3184
aif->pll = &tscs454->pll1;
sound/soc/codecs/tscs454.c
3186
aif->pll = &tscs454->pll2;
sound/soc/codecs/tscs454.c
3189
aif->pll->id, aif->id);
sound/soc/codecs/tscs454.c
3191
reserve_pll(aif->pll);
sound/soc/codecs/tscs454.c
3197
tscs454->internal_rate.pll = &tscs454->pll1;
sound/soc/codecs/tscs454.c
3199
tscs454->internal_rate.pll = &tscs454->pll2;
sound/soc/codecs/tscs454.c
3202
tscs454->internal_rate.pll->id);
sound/soc/codecs/tscs454.c
3204
reserve_pll(tscs454->internal_rate.pll);
sound/soc/codecs/tscs454.c
49
static inline void pll_init(struct pll *pll, int id)
sound/soc/codecs/tscs454.c
51
pll->id = id;
sound/soc/codecs/tscs454.c
52
mutex_init(&pll->lock);
sound/soc/codecs/tscs454.c
56
struct pll *pll;
sound/soc/codecs/tscs454.c
62
struct pll *pll;
sound/soc/codecs/tscs454.c
659
static inline void reserve_pll(struct pll *pll)
sound/soc/codecs/tscs454.c
661
mutex_lock(&pll->lock);
sound/soc/codecs/tscs454.c
662
pll->users++;
sound/soc/codecs/tscs454.c
663
mutex_unlock(&pll->lock);
sound/soc/codecs/tscs454.c
666
static inline void free_pll(struct pll *pll)
sound/soc/codecs/tscs454.c
668
mutex_lock(&pll->lock);
sound/soc/codecs/tscs454.c
669
pll->users--;
sound/soc/codecs/tscs454.c
670
mutex_unlock(&pll->lock);
sound/soc/codecs/tscs454.c
822
aif->pll->id, aif->id);
sound/soc/codecs/tscs454.c
823
free_pll(aif->pll);
sound/soc/codecs/tscs454.c
828
tscs454->internal_rate.pll->id);
sound/soc/codecs/tscs454.c
829
free_pll(tscs454->internal_rate.pll);
sound/soc/codecs/twl6040.c
55
int pll;
sound/soc/codecs/twl6040.c
887
if (unlikely(priv->pll == TWL6040_SYSCLK_SEL_HPPLL)) {
sound/soc/codecs/twl6040.c
923
ret = twl6040_set_pll(twl6040, priv->pll, priv->clk_in, priv->sysclk);
sound/soc/codecs/twl6040.c
941
priv->pll = clk_id;
sound/soc/codecs/wm8955.c
144
int Fref, int Fout, struct pll_factors *pll)
sound/soc/codecs/wm8955.c
157
pll->outdiv = 1;
sound/soc/codecs/wm8955.c
160
pll->outdiv = 0;
sound/soc/codecs/wm8955.c
170
pll->n = Ndiv;
sound/soc/codecs/wm8955.c
185
pll->k = K / 10;
sound/soc/codecs/wm8955.c
187
dev_dbg(dev, "N=%x K=%x OUTDIV=%x\n", pll->n, pll->k, pll->outdiv);
sound/soc/codecs/wm8955.c
249
struct pll_factors pll;
sound/soc/codecs/wm8955.c
283
clock_cfgs[sr].mclk, &pll);
sound/soc/codecs/wm8955.c
293
(pll.n << WM8955_N_SHIFT) |
sound/soc/codecs/wm8955.c
294
pll.k >> 18);
sound/soc/codecs/wm8955.c
297
(pll.k >> 9) & WM8955_K_17_9_MASK);
sound/soc/codecs/wm8955.c
300
pll.k & WM8955_K_8_0_MASK);
sound/soc/codecs/wm8955.c
301
if (pll.k)
sound/soc/codecs/wm8955.c
308
if (pll.outdiv)
sound/soc/fsl/fsl_rpmsg.c
46
struct clk *p = rpmsg->mclk, *pll = NULL, *npll = NULL;
sound/soc/fsl/fsl_rpmsg.c
56
pll = pp;
sound/soc/fsl/fsl_rpmsg.c
63
if (pll) {
sound/soc/fsl/fsl_rpmsg.c
65
if (!clk_is_match(pll, npll)) {
sound/soc/fsl/fsl_utils.c
126
struct clk *p, *pll = NULL, *npll = NULL;
sound/soc/fsl/fsl_utils.c
139
pll = pp;
sound/soc/fsl/fsl_utils.c
146
reparent = (pll && !clk_is_match(pll, npll));
sound/soc/pxa/pxa-ssp.c
511
int pll;
sound/soc/pxa/pxa-ssp.c
517
{ .rate = 8000, .pll = 32842000, .acds = SSACD_ACDS_32, .scdb = SSACD_SCDB_4X },
sound/soc/pxa/pxa-ssp.c
518
{ .rate = 11025, .pll = 5622000, .acds = SSACD_ACDS_4, .scdb = SSACD_SCDB_4X },
sound/soc/pxa/pxa-ssp.c
519
{ .rate = 16000, .pll = 32842000, .acds = SSACD_ACDS_16, .scdb = SSACD_SCDB_4X },
sound/soc/pxa/pxa-ssp.c
520
{ .rate = 22050, .pll = 5622000, .acds = SSACD_ACDS_2, .scdb = SSACD_SCDB_4X },
sound/soc/pxa/pxa-ssp.c
521
{ .rate = 44100, .pll = 11345000, .acds = SSACD_ACDS_2, .scdb = SSACD_SCDB_4X },
sound/soc/pxa/pxa-ssp.c
522
{ .rate = 48000, .pll = 12235000, .acds = SSACD_ACDS_2, .scdb = SSACD_SCDB_4X },
sound/soc/pxa/pxa-ssp.c
523
{ .rate = 96000, .pll = 12235000, .acds = SSACD_ACDS_4, .scdb = SSACD_SCDB_1X },
sound/soc/ti/j721e-evm.c
556
struct clk *pll;
sound/soc/ti/j721e-evm.c
560
pll = clk_get_parent(domain_clocks->parent[J721E_CLK_PARENT_44100]);
sound/soc/ti/j721e-evm.c
561
if (IS_ERR_OR_NULL(pll)) {
sound/soc/ti/j721e-evm.c
565
priv->pll_rates[J721E_CLK_PARENT_44100] = clk_get_rate(pll);
sound/soc/ti/j721e-evm.c
566
clk_put(pll);
sound/soc/ti/j721e-evm.c
569
pll = clk_get_parent(domain_clocks->parent[J721E_CLK_PARENT_48000]);
sound/soc/ti/j721e-evm.c
570
if (IS_ERR_OR_NULL(pll)) {
sound/soc/ti/j721e-evm.c
574
priv->pll_rates[J721E_CLK_PARENT_48000] = clk_get_rate(pll);
sound/soc/ti/j721e-evm.c
575
clk_put(pll);
sound/soc/uniphier/aio-cpu.c
130
struct uniphier_aio_pll *pll;
sound/soc/uniphier/aio-cpu.c
138
pll = &aio->chip->plls[pll_id];
sound/soc/uniphier/aio-cpu.c
140
if (pll->freq * mul[i] / div[i] == freq)
