drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11303

wb_info->writeback_source_plane = pipe->plane_state;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11780

struct drm_plane_state *plane_state;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11813

plane_state = drm_atomic_get_plane_state(state, plane);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11816

if (IS_ERR(plane_state)) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11817

ret = PTR_ERR(plane_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12757

static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12760

switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12763

*src_w = plane_state->src_h >> 16;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12764

*src_h = plane_state->src_w >> 16;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12769

*src_w = plane_state->src_w >> 16;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12770

*src_h = plane_state->src_h >> 16;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12776

dm_get_plane_scale(struct drm_plane_state *plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12781

dm_get_oriented_plane_size(plane_state, &plane_src_w, &plane_src_h);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12782

*out_plane_scale_w = plane_src_w ? plane_state->crtc_w * 1000 / plane_src_w : 0;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12783

*out_plane_scale_h = plane_src_h ? plane_state->crtc_h * 1000 / plane_src_h : 0;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12947

struct drm_plane_state *old_plane_state, *plane_state, *cursor_state;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12980

for_each_oldnew_plane_in_state(state, plane, old_plane_state, plane_state, i) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12990

if (drm_atomic_plane_enabling(old_plane_state, plane_state) ||

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12991

drm_atomic_plane_disabling(old_plane_state, plane_state) ||

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12992

old_plane_state->fb->format != plane_state->fb->format) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12997

dm_get_plane_scale(plane_state, &new_scale_w, &new_scale_h);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13036

for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, plane_state) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13044

if (amdgpu_dm_plane_is_video_format(plane_state->fb->format->format)) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13055

dm_get_plane_scale(plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13068

if (plane_state->crtc_x <= 0 && plane_state->crtc_y <= 0 &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13069

plane_state->crtc_x + plane_state->crtc_w >= crtc_state->mode.hdisplay &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13070

plane_state->crtc_y + plane_state->crtc_h >= crtc_state->mode.vdisplay) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6338

fill_plane_color_attributes(const struct drm_plane_state *plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6347

if (plane_state->state && plane_state->state->plane_color_pipeline)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6354

full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6356

switch (plane_state->color_encoding) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6387

const struct drm_plane_state *plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6393

const struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6395

to_amdgpu_framebuffer(plane_state->fb);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6456

switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6478

plane_info->layer_index = plane_state->normalized_zpos;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6480

ret = fill_plane_color_attributes(plane_state, plane_info->format,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6495

plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6503

struct drm_plane_state *plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6507

struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6512

ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6521

ret = fill_dc_plane_info_and_addr(adev, plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6551

plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

1100

struct drm_plane_state *plane_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

1113

struct drm_plane_state *plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1141

struct drm_plane_state *plane_state)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1143

struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1456

__set_dm_plane_degamma(struct drm_plane_state *plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1460

struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1533

__set_dm_plane_colorop_degamma(struct drm_plane_state *plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1539

struct drm_atomic_commit *state = plane_state->state;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1560

__set_dm_plane_colorop_3x4_matrix(struct drm_plane_state *plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1566

struct drm_atomic_commit *state = plane_state->state;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1601

__set_dm_plane_colorop_multiplier(struct drm_plane_state *plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1607

struct drm_atomic_commit *state = plane_state->state;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1630

__set_dm_plane_colorop_shaper(struct drm_plane_state *plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1636

struct drm_atomic_commit *state = plane_state->state;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1738

__set_dm_plane_colorop_3dlut(struct drm_plane_state *plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1745

struct drm_atomic_commit *state = plane_state->state;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1794

__set_dm_plane_colorop_blend(struct drm_plane_state *plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1800

struct drm_atomic_commit *state = plane_state->state;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1861

amdgpu_dm_plane_set_color_properties(struct drm_plane_state *plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1864

struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1885

drm_dbg_kms(plane_state->plane->dev,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1887

plane_state->plane->index);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1900

drm_dbg_kms(plane_state->plane->dev,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1902

plane_state->plane->index);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1911

amdgpu_dm_plane_set_colorop_properties(struct drm_plane_state *plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1914

struct drm_colorop *colorop = plane_state->color_pipeline;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1915

struct drm_device *dev = plane_state->plane->dev;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1924

ret = __set_dm_plane_colorop_degamma(plane_state, dc_plane_state, colorop);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1935

ret = __set_dm_plane_colorop_multiplier(plane_state, dc_plane_state, colorop);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1946

ret = __set_dm_plane_colorop_3x4_matrix(plane_state, dc_plane_state, colorop);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1958

ret = __set_dm_plane_colorop_shaper(plane_state, dc_plane_state, colorop);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1974

ret = __set_dm_plane_colorop_3dlut(plane_state, dc_plane_state, colorop);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1986

ret = __set_dm_plane_colorop_blend(plane_state, dc_plane_state, colorop);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

2012

struct drm_plane_state *plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

2016

struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

2022

ret = amdgpu_dm_verify_lut3d_size(adev, plane_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

2038

ret = __set_dm_plane_degamma(plane_state, dc_plane_state, color_caps);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

2094

if (!amdgpu_dm_plane_set_colorop_properties(plane_state, dc_plane_state))

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

2097

return amdgpu_dm_plane_set_color_properties(plane_state, dc_plane_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1003

struct dc_plane_state *plane_state =

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1007

adev, afb, plane_state->format, plane_state->rotation,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1009

&plane_state->tiling_info, &plane_state->plane_size,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

101

void amdgpu_dm_plane_fill_blending_from_plane_state(const struct drm_plane_state *plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1010

&plane_state->dcc, &plane_state->address,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

111

if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI ||

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

112

plane_state->pixel_blend_mode == DRM_MODE_BLEND_COVERAGE) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

123

uint32_t format = plane_state->fb->format->format;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

133

if (*per_pixel_alpha && plane_state->pixel_blend_mode == DRM_MODE_BLEND_COVERAGE)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

137

if (plane_state->alpha < 0xffff) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

139

*global_alpha_value = plane_state->alpha >> 8;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h

63

void amdgpu_dm_plane_fill_blending_from_plane_state(const struct drm_plane_state *plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

231

__field(const struct drm_plane_state *, plane_state)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

260

__entry->plane_state = state;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

293

__entry->plane_id, __entry->plane_type, __entry->plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

385

TP_PROTO(int pipe_idx, const struct dc_plane_state *plane_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

389

TP_ARGS(pipe_idx, plane_state, stream, plane_res, update_flags),

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

428

__entry->dst_x = plane_state->dst_rect.x;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

429

__entry->dst_y = plane_state->dst_rect.y;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

430

__entry->dst_w = plane_state->dst_rect.width;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

431

__entry->dst_h = plane_state->dst_rect.height;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

432

__entry->src_x = plane_state->src_rect.x;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

433

__entry->src_y = plane_state->src_rect.y;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

434

__entry->src_w = plane_state->src_rect.width;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

435

__entry->src_h = plane_state->src_rect.height;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

436

__entry->clip_x = plane_state->clip_rect.x;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

437

__entry->clip_y = plane_state->clip_rect.y;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

438

__entry->clip_w = plane_state->clip_rect.width;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

439

__entry->clip_h = plane_state->clip_rect.height;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

448

__entry->flip_immediate = plane_state->flip_immediate;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

449

__entry->surface_pitch = plane_state->plane_size.surface_pitch;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

450

__entry->format = plane_state->format;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

451

__entry->swizzle = plane_state->tiling_info.gfx9.swizzle;

drivers/gpu/drm/amd/display/dc/basics/dc_common.c

55

if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)

drivers/gpu/drm/amd/display/dc/basics/dc_common.c

64

if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)

drivers/gpu/drm/amd/display/dc/basics/dc_common.c

73

if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)

drivers/gpu/drm/amd/display/dc/basics/dc_common.c

83

const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/basics/dc_common.c

85

if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN

drivers/gpu/drm/amd/display/dc/basics/dc_common.c

86

&& plane_state->format != SURFACE_PIXEL_FORMAT_INVALID

drivers/gpu/drm/amd/display/dc/basics/dc_common.c

87

&& plane_state->input_csc_color_matrix.enable_adjustment

drivers/gpu/drm/amd/display/dc/basics/dc_common.c

88

&& plane_state->coeff_reduction_factor.value != 0) {

drivers/gpu/drm/amd/display/dc/basics/dc_common.c

90

dc_fixpt_mul(plane_state->coeff_reduction_factor,

drivers/gpu/drm/amd/display/dc/basics/dc_common.h

40

const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

2806

ASSERT(pipe[i].plane_state);

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

2809

if (!pipe[i].plane_state->visible)

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

2814

if (!pipe[i].plane_state->visible)

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

2832

switch (pipe[i].plane_state->rotation) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

2848

switch (pipe[i].plane_state->format) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

2883

pipe[i].bottom_pipe->plane_state->plane_size.surface_pitch);

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

2890

switch (pipe[i].bottom_pipe->plane_state->rotation) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

2927

if (pipe[i].plane_state) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

2935

switch (pipe[i].plane_state->rotation) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

2951

switch (pipe[i].plane_state->format) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

166

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

113

if (pipe->stream && (pipe->stream->dpms_off || pipe->plane_state == NULL ||

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

505

int width = pipe->plane_state->src_rect.width;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

506

int height = pipe->plane_state->src_rect.height;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

510

pipe->plane_state->dst_rect.width == width &&

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

511

pipe->plane_state->dst_rect.height == height)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

596

if (curr_pipe_ctx->plane_state) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

598

disp_src_width_list[i] = curr_pipe_ctx->plane_state->src_rect.width;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

599

disp_src_height_list[i] = curr_pipe_ctx->plane_state->src_rect.height;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

399

int width = pipe->plane_state->src_rect.width;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

400

int height = pipe->plane_state->src_rect.height;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

404

pipe->plane_state->dst_rect.width == width &&

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

405

pipe->plane_state->dst_rect.height == height)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

488

if (curr_pipe_ctx->plane_state) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

490

disp_src_width_list[i] = curr_pipe_ctx->plane_state->src_rect.width;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

491

disp_src_height_list[i] = curr_pipe_ctx->plane_state->src_rect.height;

drivers/gpu/drm/amd/display/dc/core/dc.c

1167

(pipe_ctx->plane_state || old_pipe_ctx->plane_state))

drivers/gpu/drm/amd/display/dc/core/dc.c

1177

memcpy(&pipe_ctx->visual_confirm_color, &pipe_ctx->plane_state->visual_confirm_color,

drivers/gpu/drm/amd/display/dc/core/dc.c

1225

struct dc_plane_state *plane_state = NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

1246

plane_state = stream_status->plane_states[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

1248

if (!plane_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

1254

if (pipe->plane_state == plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc.c

1322

if (pipe->stream && pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc.c

1381

if (old_pipe->plane_state && !new_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

1409

if (pipe->stream && pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc.c

2091

struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

2093

return (pipe_ctx->plane_state == plane_state);

drivers/gpu/drm/amd/display/dc/core/dc.c

2618

if (!pipe->plane_state || (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM))

drivers/gpu/drm/amd/display/dc/core/dc.c

2622

pipe->plane_state->status.is_flip_pending = false;

drivers/gpu/drm/amd/display/dc/core/dc.c

2624

if (pipe->plane_state->status.is_flip_pending)

drivers/gpu/drm/amd/display/dc/core/dc.c

2674

context->res_ctx.pipe_ctx[i].plane_state == NULL) {

drivers/gpu/drm/amd/display/dc/core/dc.c

2750

const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

2757

if (plane_state == pipe_ctx->plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc.c

3774

if (pipe_ctx->plane_state != surface)

drivers/gpu/drm/amd/display/dc/core/dc.c

3887

!tmp_pipe->plane_state ||

drivers/gpu/drm/amd/display/dc/core/dc.c

4457

struct dc_plane_state *plane_state = srf_updates[i].surface;

drivers/gpu/drm/amd/display/dc/core/dc.c

4479

if (pipe_ctx->plane_state != plane_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

4519

struct dc_plane_state *plane_state = srf_updates[i].surface;

drivers/gpu/drm/amd/display/dc/core/dc.c

4541

if (pipe_ctx->plane_state != plane_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

4608

struct dc_plane_state *plane_state = srf_updates[i].surface;

drivers/gpu/drm/amd/display/dc/core/dc.c

4616

if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))

drivers/gpu/drm/amd/display/dc/core/dc.c

4620

if (pipe_ctx->plane_state->update_flags.bits.addr_update)

drivers/gpu/drm/amd/display/dc/core/dc.c

4685

if (pipe->stream && pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4695

struct dc_plane_state *plane_state = srf_updates[i].surface;

drivers/gpu/drm/amd/display/dc/core/dc.c

4700

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

4702

if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))

drivers/gpu/drm/amd/display/dc/core/dc.c

4705

pipe_ctx->plane_state->triplebuffer_flips = false;

drivers/gpu/drm/amd/display/dc/core/dc.c

4708

!pipe_ctx->plane_state->flip_immediate && dc->debug.enable_tri_buf) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4710

pipe_ctx->plane_state->triplebuffer_flips = true;

drivers/gpu/drm/amd/display/dc/core/dc.c

4787

if (pipe->stream && pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4936

pipe_ctx->stream && pipe_ctx->plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4948

struct dc_plane_state *plane_state = srf_updates[i].surface;

drivers/gpu/drm/amd/display/dc/core/dc.c

4953

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

4955

if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))

drivers/gpu/drm/amd/display/dc/core/dc.c

4957

pipe_ctx->plane_state->triplebuffer_flips = false;

drivers/gpu/drm/amd/display/dc/core/dc.c

4960

!pipe_ctx->plane_state->flip_immediate && dc->debug.enable_tri_buf) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4962

pipe_ctx->plane_state->triplebuffer_flips = true;

drivers/gpu/drm/amd/display/dc/core/dc.c

4967

plane_state->flip_immediate = false;

drivers/gpu/drm/amd/display/dc/core/dc.c

4968

plane_state->triplebuffer_flips = false;

drivers/gpu/drm/amd/display/dc/core/dc.c

4981

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

5000

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

5007

ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);

drivers/gpu/drm/amd/display/dc/core/dc.c

5011

dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);

drivers/gpu/drm/amd/display/dc/core/dc.c

5046

struct dc_plane_state *plane_state = srf_updates[i].surface;

drivers/gpu/drm/amd/display/dc/core/dc.c

5054

if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))

drivers/gpu/drm/amd/display/dc/core/dc.c

5059

pipe_ctx->plane_state->flip_immediate);

drivers/gpu/drm/amd/display/dc/core/dc.c

5065

struct dc_plane_state *plane_state = srf_updates[i].surface;

drivers/gpu/drm/amd/display/dc/core/dc.c

5073

if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))

drivers/gpu/drm/amd/display/dc/core/dc.c

5088

dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);

drivers/gpu/drm/amd/display/dc/core/dc.c

5090

if (pipe_ctx->plane_state->update_flags.bits.addr_update)

drivers/gpu/drm/amd/display/dc/core/dc.c

5176

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

5181

!pipe_ctx->plane_state->update_flags.bits.addr_update ||

drivers/gpu/drm/amd/display/dc/core/dc.c

5182

pipe_ctx->plane_state->skip_manual_trigger)

drivers/gpu/drm/amd/display/dc/core/dc.c

5377

if (pipe_ctx->plane_state && pipe_ctx->stream == stream)

drivers/gpu/drm/amd/display/dc/core/dc.c

5378

pipe_ctx->plane_state->force_full_update = false;

drivers/gpu/drm/amd/display/dc/core/dc.c

5556

if (pipe->plane_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

6197

if (!pipe_ctx->plane_state || !pipe_ctx->stream_res.tg)

drivers/gpu/drm/amd/display/dc/core/dc.c

7326

if (pipe_ctx->plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7328

state->hubp[i].surface_pixel_format = pipe_ctx->plane_state->format;

drivers/gpu/drm/amd/display/dc/core/dc.c

7329

state->hubp[i].rotation_angle = pipe_ctx->plane_state->rotation;

drivers/gpu/drm/amd/display/dc/core/dc.c

7330

state->hubp[i].h_mirror_en = pipe_ctx->plane_state->horizontal_mirror ? 1 : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7333

if (pipe_ctx->plane_state->plane_size.surface_size.width > 0) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7334

state->hubp[i].surface_size_width = pipe_ctx->plane_state->plane_size.surface_size.width;

drivers/gpu/drm/amd/display/dc/core/dc.c

7335

state->hubp[i].surface_size_height = pipe_ctx->plane_state->plane_size.surface_size.height;

drivers/gpu/drm/amd/display/dc/core/dc.c

7339

if (pipe_ctx->plane_state->src_rect.width > 0) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7340

state->hubp[i].pri_viewport_width = pipe_ctx->plane_state->src_rect.width;

drivers/gpu/drm/amd/display/dc/core/dc.c

7341

state->hubp[i].pri_viewport_height = pipe_ctx->plane_state->src_rect.height;

drivers/gpu/drm/amd/display/dc/core/dc.c

7342

state->hubp[i].pri_viewport_x_start = pipe_ctx->plane_state->src_rect.x;

drivers/gpu/drm/amd/display/dc/core/dc.c

7343

state->hubp[i].pri_viewport_y_start = pipe_ctx->plane_state->src_rect.y;

drivers/gpu/drm/amd/display/dc/core/dc.c

7347

state->hubp[i].surface_dcc_en = (pipe_ctx->plane_state->dcc.enable) ? 1 : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7348

state->hubp[i].surface_dcc_ind_64b_blk = pipe_ctx->plane_state->dcc.independent_64b_blks;

drivers/gpu/drm/amd/display/dc/core/dc.c

7349

state->hubp[i].surface_dcc_ind_128b_blk = pipe_ctx->plane_state->dcc.dcc_ind_blk;

drivers/gpu/drm/amd/display/dc/core/dc.c

7352

state->hubp[i].surface_pitch = pipe_ctx->plane_state->plane_size.surface_pitch;

drivers/gpu/drm/amd/display/dc/core/dc.c

7353

state->hubp[i].meta_pitch = pipe_ctx->plane_state->dcc.meta_pitch;

drivers/gpu/drm/amd/display/dc/core/dc.c

7354

state->hubp[i].chroma_pitch = pipe_ctx->plane_state->plane_size.chroma_pitch;

drivers/gpu/drm/amd/display/dc/core/dc.c

7355

state->hubp[i].meta_pitch_c = pipe_ctx->plane_state->dcc.meta_pitch_c;

drivers/gpu/drm/amd/display/dc/core/dc.c

7358

state->hubp[i].primary_surface_address_low = pipe_ctx->plane_state->address.grph.addr.low_part;

drivers/gpu/drm/amd/display/dc/core/dc.c

7359

state->hubp[i].primary_surface_address_high = pipe_ctx->plane_state->address.grph.addr.high_part;

drivers/gpu/drm/amd/display/dc/core/dc.c

7360

state->hubp[i].primary_meta_surface_address_low = pipe_ctx->plane_state->address.grph.meta_addr.low_part;

drivers/gpu/drm/amd/display/dc/core/dc.c

7361

state->hubp[i].primary_meta_surface_address_high = pipe_ctx->plane_state->address.grph.meta_addr.high_part;

drivers/gpu/drm/amd/display/dc/core/dc.c

7364

state->hubp[i].primary_surface_tmz = pipe_ctx->plane_state->address.tmz_surface;

drivers/gpu/drm/amd/display/dc/core/dc.c

7365

state->hubp[i].primary_meta_surface_tmz = pipe_ctx->plane_state->address.tmz_surface;

drivers/gpu/drm/amd/display/dc/core/dc.c

7369

if (pipe_ctx->plane_state->tiling_info.gfxversion >= DcGfxVersion9) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7371

state->hubp[i].sw_mode = pipe_ctx->plane_state->tiling_info.gfx9.swizzle;

drivers/gpu/drm/amd/display/dc/core/dc.c

7372

state->hubp[i].num_pipes = pipe_ctx->plane_state->tiling_info.gfx9.num_pipes;

drivers/gpu/drm/amd/display/dc/core/dc.c

7373

state->hubp[i].num_banks = pipe_ctx->plane_state->tiling_info.gfx9.num_banks;

drivers/gpu/drm/amd/display/dc/core/dc.c

7374

state->hubp[i].pipe_interleave = pipe_ctx->plane_state->tiling_info.gfx9.pipe_interleave;

drivers/gpu/drm/amd/display/dc/core/dc.c

7375

state->hubp[i].num_shader_engines = pipe_ctx->plane_state->tiling_info.gfx9.num_shader_engines;

drivers/gpu/drm/amd/display/dc/core/dc.c

7376

state->hubp[i].num_rb_per_se = pipe_ctx->plane_state->tiling_info.gfx9.num_rb_per_se;

drivers/gpu/drm/amd/display/dc/core/dc.c

7377

state->hubp[i].num_pkrs = pipe_ctx->plane_state->tiling_info.gfx9.num_pkrs;

drivers/gpu/drm/amd/display/dc/core/dc.c

7464

if (pipe_ctx->plane_state && pipe_ctx->plane_res.scl_data.recout.width > 0) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7586

if (pipe_ctx->plane_state && pipe_ctx->stream) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7587

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/core/dc.c

7590

state->mpc.mpcc_mode[i] = (plane_state->blend_tf.type != TF_TYPE_BYPASS) ? 1 : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7591

state->mpc.mpcc_alpha_blend_mode[i] = plane_state->per_pixel_alpha ? 1 : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7592

state->mpc.mpcc_alpha_multiplied_mode[i] = plane_state->pre_multiplied_alpha ? 1 : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7594

state->mpc.mpcc_global_alpha[i] = plane_state->global_alpha_value;

drivers/gpu/drm/amd/display/dc/core/dc.c

7595

state->mpc.mpcc_global_gain[i] = plane_state->global_alpha ? 255 : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7608

if (plane_state->gamma_correction.type != GAMMA_CS_TFM_1D && plane_state->gamma_correction.num_entries > 0) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1030

if (current_mpc_pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1031

if (dc->hwss.set_flip_control_gsl && current_mpc_pipe->plane_state->update_flags.raw) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1033

block_sequence[*num_steps].params.set_flip_control_gsl_params.flip_immediate = current_mpc_pipe->plane_state->flip_immediate;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1037

if (dc->hwss.program_triplebuffer && dc->debug.enable_tri_buf && current_mpc_pipe->plane_state->update_flags.raw) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1040

block_sequence[*num_steps].params.program_triplebuffer_params.enableTripleBuffer = current_mpc_pipe->plane_state->triplebuffer_flips;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1044

if (dc->hwss.update_plane_addr && current_mpc_pipe->plane_state->update_flags.bits.addr_update) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1048

block_sequence[*num_steps].params.subvp_save_surf_addr.addr = &current_mpc_pipe->plane_state->address;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1060

if (hws->funcs.set_input_transfer_func && current_mpc_pipe->plane_state->update_flags.bits.gamma_change) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1063

block_sequence[*num_steps].params.set_input_transfer_func_params.plane_state = current_mpc_pipe->plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1069

(current_mpc_pipe->plane_state->update_flags.bits.gamut_remap_change ||

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1075

if (current_mpc_pipe->plane_state->update_flags.bits.input_csc_change) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1080

if (current_mpc_pipe->plane_state->update_flags.bits.coeff_reduction_change) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1085

if (current_mpc_pipe->plane_state->update_flags.bits.cm_hist_change) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1089

= current_mpc_pipe->plane_state->cm_hist_control;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1091

= current_mpc_pipe->plane_state->color_space;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1098

current_mpc_pipe->plane_state->update_flags.bits.cursor_csc_color_matrix_change) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1100

block_sequence[*num_steps].params.dpp_set_cursor_matrix_params.color_space = current_mpc_pipe->plane_state->color_space;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1101

block_sequence[*num_steps].params.dpp_set_cursor_matrix_params.cursor_csc_color_matrix = &current_mpc_pipe->plane_state->cursor_csc_color_matrix;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1178

current_mpc_pipe->stream && current_mpc_pipe->plane_state &&

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1179

current_mpc_pipe->plane_state->update_flags.bits.addr_update &&

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1180

!current_mpc_pipe->plane_state->skip_manual_trigger) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1235

params->set_input_transfer_func_params.plane_state);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1748

struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1753

seq_state->steps[*seq_state->num_steps].params.set_input_transfer_func_params.plane_state = plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2326

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2328

if (!plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2334

plane_state->format,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2336

plane_state->input_csc_color_matrix,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2337

plane_state->color_space,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2346

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2347

struct dc_bias_and_scale bns_params = plane_state->bias_and_scale;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2455

switch (bottom_pipe_ctx->plane_state->tiling_info.gfx9.swizzle) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2523

if (!pipe->plane_state || dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2529

pipe->plane_state->status.is_flip_pending = false;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2531

if (!pipe->plane_state->status.is_flip_pending)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2536

ASSERT(!pipe->plane_state->status.is_flip_pending);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

350

if (pipe_ctx->plane_state->layer_index > 0) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

360

if (pipe_ctx->plane_state->layer_index > 0) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

379

if (pipe_ctx->plane_state->layer_index > 0) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

598

if (!pipe_ctx->plane_state->dcc.enable) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

740

struct dc_plane_state *plane = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

953

!current_pipe->plane_state ||

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1187

&pipe_ctx->plane_state->clip_rect);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1216

const struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1218

struct rect surf_src = plane_state->src_rect;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1225

if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1226

pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1231

plane_state->dst_rect.width);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1234

plane_state->dst_rect.height);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1332

const struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1334

struct rect src = plane_state->src_rect;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1347

pipe_ctx, &plane_state->dst_rect);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1362

plane_state->rotation,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1363

plane_state->horizontal_mirror,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1521

const struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1530

if (!plane_state ||

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1531

!plane_state->dst_rect.width ||

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1532

!plane_state->dst_rect.height ||

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1533

!plane_state->src_rect.width ||

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1534

!plane_state->src_rect.height) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1551

pipe_ctx->plane_state->format);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1558

if (plane_state->ctx->dce_version > DCE_VERSION_MAX)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1563

pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1579

if (!res && plane_state->is_phantom)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1600

if (plane_state->ctx->dce_version > DCE_VERSION_MAX)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1605

pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1615

pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1619

pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1627

pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1631

pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1642

&plane_state->scaling_quality);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1648

&plane_state->scaling_quality);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1652

if (!res && plane_state->is_phantom)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1666

if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state == plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1667

ASSERT(plane_state->rotation == ROTATION_ANGLE_0 ||

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1698

plane_state->src_rect.height,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1699

plane_state->src_rect.width,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1700

plane_state->src_rect.x,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1701

plane_state->src_rect.y,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1702

plane_state->dst_rect.height,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1703

plane_state->dst_rect.width,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1704

plane_state->dst_rect.x,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1705

plane_state->dst_rect.y,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1706

plane_state->clip_rect.height,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1707

plane_state->clip_rect.width,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1708

plane_state->clip_rect.x,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1709

plane_state->clip_rect.y);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1722

unsigned int cur_layer = pipe_ctx->plane_state->layer_index;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1738

if (!test_pipe->plane_state ||

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1739

!test_pipe->plane_state->visible ||

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1740

test_pipe->plane_state->layer_index == cur_layer)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1754

if (split_pipe->plane_state->layer_index == test_pipe->plane_state->layer_index) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1782

if (context->res_ctx.pipe_ctx[i].plane_state != NULL &&

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2023

return pipe_ctx->plane_state && pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2025

return !pipe_ctx->plane_state && !pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2098

if (pipe->plane_state == plane && pipe->prev_odm_pipe == NULL) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2100

pipe->top_pipe->plane_state != plane)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2112

while (pipe && pipe->plane_state == plane) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2147

pri_dpp_pipe->top_pipe->plane_state == pri_dpp_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2158

while (split_pipe && split_pipe->plane_state == pipe_ctx->plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2171

while (other_pipe && other_pipe->plane_state == pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2176

while (other_pipe && other_pipe->plane_state == pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2313

if (pipe_a->plane_state && !pipe_b->plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2315

else if (!pipe_a->plane_state && pipe_b->plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2321

if ((pipe_a->bottom_pipe->plane_state == pipe_a->plane_state) &&

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2322

(pipe_b->bottom_pipe->plane_state != pipe_b->plane_state))

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2324

else if ((pipe_a->bottom_pipe->plane_state != pipe_a->plane_state) &&

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2325

(pipe_b->bottom_pipe->plane_state == pipe_b->plane_state))

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2469

if (opp_heads[slice_idx]->plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2476

dpp_pipes[dpp_idx]->top_pipe->plane_state != dpp_pipes[dpp_idx]->plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2584

dpp_pipe->plane_state == dpp_pipe->bottom_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2600

if (pipe->stream == otg_master->stream && pipe->plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2623

if (pipe->plane_state == plane)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2640

split_pipe->top_pipe->plane_state == split_pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2645

if (split_pipe->top_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3150

ASSERT(otg_master->plane_state == NULL);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3222

struct dc_plane_state *plane_state,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3229

if (opp_head_pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3233

opp_head_pipe->plane_state = plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3273

struct dc_plane_state *plane_state,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3301

sec_pipe->plane_state = plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3324

struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3328

if (otg_master_pipe->plane_state == NULL)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3330

plane_state, new_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3333

otg_master_pipe, plane_state, new_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3338

plane_state, new_ctx, pool);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3341

pool, plane_state);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3350

const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3357

if (pipe_ctx->plane_state == plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3373

pipe_ctx->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3437

new_opp_head->plane_state = last_opp_head->plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3449

new_bottom_dpp_pipe->plane_state = last_bottom_dpp_pipe->plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3577

new_dpp_pipe->plane_state = last_dpp_pipe->plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3706

dpp_pipes[0]->plane_state, new_ctx, pool);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4731

pipe_ctx->plane_state &&

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4732

pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4733

result = dc->res_pool->funcs->patch_unknown_plane_state(pipe_ctx->plane_state);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5499

enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5504

if (plane_state->src_rect.width == 0 || plane_state->src_rect.height == 0 ||

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5505

plane_state->dst_rect.width == 0 || plane_state->dst_rect.height == 0)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5510

return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

6003

if (opp_heads[slice_idx]->plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc_state.c

501

struct dc_plane_state *plane_state,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

519

plane_state, MAX_SURFACES);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

526

dc->current_state, pool, otg_master_pipe, plane_state);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

536

otg_master_pipe, plane_state);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

549

otg_master_pipe, plane_state);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

557

plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_state.c

559

dc_plane_state_retain(plane_state);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

569

struct dc_plane_state *plane_state,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

576

if (!plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

591

state, pool, plane_state);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

594

if (stream_status->plane_states[i] == plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc_state.c

963

if (pipe->plane_state && pipe->stream && dc_state_get_pipe_subvp_type(state, pipe) == SUBVP_PHANTOM) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

469

!pipe_ctx->plane_state ||

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

562

if (pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

113

const struct dc_plane_state *plane_state,

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

120

if (!plane_state ||

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

121

!plane_state->ctx ||

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

122

!plane_state->ctx->dc) {

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

127

plane_status = &plane_state->status;

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

128

dc = plane_state->ctx->dc;

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

138

if (pipe_ctx->plane_state != plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

141

if (pipe_ctx->plane_state && flags.bits.address)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

142

pipe_ctx->plane_state->status.is_flip_pending = false;

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

143

if (pipe_ctx->plane_state && flags.bits.histogram)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

144

memset(&pipe_ctx->plane_state->status.cm_hist, 0,

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

145

sizeof(pipe_ctx->plane_state->status.cm_hist));

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

156

if (pipe_ctx->plane_state != plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

165

dpp->funcs->dpp_cm_hist_read(dpp, &pipe_ctx->plane_state->status.cm_hist);

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

172

void dc_plane_state_retain(struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

174

kref_get(&plane_state->refcount);

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

179

struct dc_plane_state *plane_state = container_of(kref, struct dc_plane_state, refcount);

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

180

dc_plane_destruct(plane_state);

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

181

kvfree(plane_state);

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

184

void dc_plane_state_release(struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

186

kref_put(&plane_state->refcount, dc_plane_state_free);

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

285

void dc_plane_force_dcc_and_tiling_disable(struct dc_plane_state *plane_state,

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

291

if (!plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

294

dc = plane_state->ctx->dc;

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

306

dc->hwss.clear_surface_dcc_and_tiling(pipe_ctx, plane_state, clear_tiling);

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

40

void dc_plane_construct(struct dc_context *ctx, struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

42

plane_state->ctx = ctx;

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

44

plane_state->gamma_correction.is_identity = true;

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

46

plane_state->in_transfer_func.type = TF_TYPE_BYPASS;

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

48

plane_state->in_shaper_func.type = TF_TYPE_BYPASS;

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

50

plane_state->lut3d_func.state.raw = 0;

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

52

plane_state->blend_tf.type = TF_TYPE_BYPASS;

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

54

plane_state->pre_multiplied_alpha = true;

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

58

void dc_plane_destruct(struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

60

(void)plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

69

uint8_t dc_plane_get_pipe_mask(struct dc_state *dc_state, const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

74

for (i = 0; i < plane_state->ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

77

if (pipe_ctx->plane_state == plane_state && pipe_ctx->plane_res.hubp)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

89

struct dc_plane_state *plane_state = kvzalloc_obj(*plane_state,

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

92

if (NULL == plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

95

kref_init(&plane_state->refcount);

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

96

dc_plane_construct(dc->ctx, plane_state);

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

98

return plane_state;

drivers/gpu/drm/amd/display/dc/dc.h

2075

enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1024

if (pipe_ctx->plane_state != NULL) {

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1025

if (pipe_ctx->plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE ||

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1971

struct dc_plane_state *plane_state;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1982

plane_state = srf_updates[plane_index].surface;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1983

address = &plane_state->address;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1999

cmds[num_cmds].fams2_flip.flip_info.pipe_mask = (uint8_t)dc_plane_get_pipe_mask(state, plane_state);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

2003

cmds[num_cmds].fams2_flip.flip_info.config.bits.is_immediate = plane_state->flip_immediate;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

827

reduce_fraction(subvp_pipe->plane_state->src_rect.height, subvp_pipe->plane_state->dst_rect.height,

drivers/gpu/drm/amd/display/dc/dc_plane.h

41

const struct dc_plane_state *plane_state,

drivers/gpu/drm/amd/display/dc/dc_plane.h

43

void dc_plane_state_retain(struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/dc_plane.h

44

void dc_plane_state_release(struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/dc_plane.h

46

void dc_plane_force_dcc_and_tiling_disable(struct dc_plane_state *plane_state,

drivers/gpu/drm/amd/display/dc/dc_plane_priv.h

31

void dc_plane_construct(struct dc_context *ctx, struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/dc_plane_priv.h

32

void dc_plane_destruct(struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/dc_plane_priv.h

33

uint8_t dc_plane_get_pipe_mask(struct dc_state *dc_state, const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

105

populate_splrect_from_rect(&spl_in->basic_in.clip_rect, &plane_state->clip_rect);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

111

spl_in->basic_in.rotation = (enum spl_rotation_angle)plane_state->rotation;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

113

populate_splrect_from_rect(&spl_in->basic_in.src_rect, &plane_state->src_rect);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

115

populate_splrect_from_rect(&spl_in->basic_in.dst_rect, &plane_state->dst_rect);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

117

spl_in->basic_in.horizontal_mirror = plane_state->horizontal_mirror;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

145

populate_spltaps_from_taps(&spl_in->scaling_quality, &plane_state->scaling_quality);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

165

spl_in->adaptive_sharpness.sharpness_range.sdr_rgb_min = plane_state->sharpness_range.sdr_rgb_min;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

166

spl_in->adaptive_sharpness.sharpness_range.sdr_rgb_max = plane_state->sharpness_range.sdr_rgb_max;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

167

spl_in->adaptive_sharpness.sharpness_range.sdr_rgb_mid = plane_state->sharpness_range.sdr_rgb_mid;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

168

spl_in->adaptive_sharpness.sharpness_range.sdr_yuv_min = plane_state->sharpness_range.sdr_yuv_min;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

169

spl_in->adaptive_sharpness.sharpness_range.sdr_yuv_max = plane_state->sharpness_range.sdr_yuv_max;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

170

spl_in->adaptive_sharpness.sharpness_range.sdr_yuv_mid = plane_state->sharpness_range.sdr_yuv_mid;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

171

spl_in->adaptive_sharpness.sharpness_range.hdr_rgb_min = plane_state->sharpness_range.hdr_rgb_min;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

172

spl_in->adaptive_sharpness.sharpness_range.hdr_rgb_max = plane_state->sharpness_range.hdr_rgb_max;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

173

spl_in->adaptive_sharpness.sharpness_range.hdr_rgb_mid = plane_state->sharpness_range.hdr_rgb_mid;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

180

} else if (!plane_state->adaptive_sharpness_en) {

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

185

spl_in->adaptive_sharpness.sharpness_level = plane_state->sharpness_level;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

192

spl_in->lls_pref = plane_state->linear_light_scaling;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

197

spl_in->basic_in.cositing = plane_state->cositing;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

199

spl_in->basic_in.tf_type = (enum spl_transfer_func_type) plane_state->in_transfer_func.type;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

200

spl_in->basic_in.tf_predefined_type = (enum spl_transfer_func_predefined) plane_state->in_transfer_func.tf;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

205

spl_in->sharpen_policy = (enum sharpen_policy)plane_state->adaptive_sharpness_policy;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

214

spl_in->sdr_white_level_nits = plane_state->sdr_white_level_nits;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

79

const struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

85

switch (plane_state->ctx->dce_version) {

drivers/gpu/drm/amd/display/dc/dc_state.h

53

struct dc_plane_state *plane_state,

drivers/gpu/drm/amd/display/dc/dc_state.h

59

struct dc_plane_state *plane_state,

drivers/gpu/drm/amd/display/dc/dc_trace.h

29

if (pipe_ctx->plane_state) \

drivers/gpu/drm/amd/display/dc/dc_trace.h

30

trace_amdgpu_dm_dc_pipe_state(pipe_ctx->pipe_idx, pipe_ctx->plane_state, \

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1007

pipe->plane_state->format, &bpe) ? dcn_bw_yes : dcn_bw_no;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1011

pipe->plane_state->format);

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1013

pipe->plane_state->tiling_info.gfx9.swizzle);

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1028

v->source_scan[input_idx] = (pipe->plane_state->rotation % 2) ? dcn_bw_vert : dcn_bw_hor;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1209

if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1237

if (pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1240

pipe->plane_state->update_flags.bits.full_update = 1;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1251

if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1270

} else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1275

hsplit_pipe->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

308

if (pipe->plane_state->stereo_format == PLANE_STEREO_FORMAT_SIDE_BY_SIDE ||

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

309

pipe->plane_state->stereo_format == PLANE_STEREO_FORMAT_TOP_AND_BOTTOM) {

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

312

} else if (pipe->top_pipe != NULL && pipe->top_pipe->plane_state == pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

314

} else if (pipe->bottom_pipe != NULL && pipe->bottom_pipe->plane_state == pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

323

input->src.dcc = pipe->plane_state->dcc.enable ? 1 : 0;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

334

dcc_support_pixel_format(pipe->plane_state->format, &bpe) ? 1 : 0;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

337

input->src.meta_pitch = pipe->plane_state->dcc.meta_pitch;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

339

input->src.sw_mode = pipe->plane_state->tiling_info.gfx9.swizzle;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

348

input->src.macro_tile_size = swizzle_mode_to_macro_tile_size(pipe->plane_state->tiling_info.gfx9.swizzle);

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

350

switch (pipe->plane_state->rotation) {

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

365

switch (pipe->plane_state->format) {

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

519

pipe->plane_state->flip_immediate);

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

531

if (!primary_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

719

if (pipe->plane_state &&

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

720

(pipe->plane_state->dst_rect.width <= 16 ||

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

721

pipe->plane_state->dst_rect.height <= 16 ||

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

722

pipe->plane_state->src_rect.width <= 16 ||

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

723

pipe->plane_state->src_rect.height <= 16)) {

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

902

if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

918

if (!pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

949

if (pipe->bottom_pipe && pipe->bottom_pipe->plane_state == pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

950

if (pipe->plane_state->rotation % 2 == 0) {

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

979

if (pipe->plane_state->rotation % 2 == 0) {

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

996

v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1067

if (context->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1186

if (context->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1432

if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1433

== res_ctx->pipe_ctx[i].plane_state) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1437

while (first_pipe->top_pipe && first_pipe->top_pipe->plane_state

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1438

== res_ctx->pipe_ctx[i].plane_state) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1547

if (res_ctx->pipe_ctx[i].plane_state &&

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1548

(res_ctx->pipe_ctx[i].plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE ||

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1557

if (!res_ctx->pipe_ctx[i].plane_state) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1598

struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1602

pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1603

|| (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1668

while (split_pipe && split_pipe->plane_state == pln) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1673

while (split_pipe && split_pipe->plane_state == pln) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2512

(wb_info->writeback_source_plane == res_ctx->pipe_ctx[i].plane_state)) {

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

209

(wb_info->writeback_source_plane == res_ctx->pipe_ctx[i].plane_state)) {

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

544

if (context->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

351

if (pipe->plane_state &&

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

352

(pipe->plane_state->src_rect.height < pipe->plane_state->dst_rect.height ||

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

353

pipe->plane_state->src_rect.width < pipe->plane_state->dst_rect.width))

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

395

if (pipe_cnt == 1 && pipe->plane_state

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

396

&& pipe->plane_state->rotation == ROTATION_ANGLE_0 && !dc->debug.disable_z9_mpc) {

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

397

if (!is_dual_plane(pipe->plane_state->format) && pipe->plane_state->src_rect.width <= 5120) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1003

if (pipe->plane_state && !pipe->top_pipe &&

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1058

if (pipe->plane_state && !pipe->top_pipe) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1195

if (dpp_pipes[j]->plane_state)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1197

dpp_pipes[j]->plane_state, 1);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1251

update_slice_table_for_plane(table, pipe, pipe->plane_state, -1);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1263

pipe->plane_state, split[dc_pipe_idx] - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1678

if (context->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1701

if (context->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1716

if (context->res_ctx.pipe_ctx[i].stream && context->res_ctx.pipe_ctx[i].plane_state &&

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1718

context->res_ctx.pipe_ctx[i].plane_state != context->res_ctx.pipe_ctx[i].top_pipe->plane_state) &&

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1833

if (odm && pri_pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1835

if (pri_pipe->plane_state->clip_rect.x + pri_pipe->plane_state->clip_rect.width <=

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1845

if (pri_pipe->plane_state->clip_rect.x >= pri_pipe->stream->src.x + pri_pipe->stream->src.width/2) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1901

ASSERT(pri_pipe->plane_state);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1972

pipe->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1982

} else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1992

pipe->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2016

if (!pipe->plane_state && !odm)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2027

old_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2030

old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2052

old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2071

old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2092

if (pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2199

&& pipe->plane_state && mpo_pipe

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2200

&& memcmp(&mpo_pipe->plane_state->clip_rect,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2203

ASSERT(mpo_pipe->plane_state != pipe->plane_state);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3437

pipe->plane_state && !(pipe->stream->vrr_active_variable || pipe->stream->vrr_active_fixed)) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

351

if (pipe->plane_state && dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3517

if (!pipe->stream || !pipe->plane_state)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

631

if (pipe->plane_state && !pipe->top_pipe && !pipe->prev_odm_pipe && !dcn32_is_center_timing(pipe) &&

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

638

!pipe->plane_state->address.tmz_surface &&

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

747

if (phantom && pipe->stream && pipe->plane_state && !pipe->top_pipe &&

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

488

if (pipe->plane_state &&

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

489

(pipe->plane_state->src_rect.height <

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

490

pipe->plane_state->dst_rect.height ||

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

491

pipe->plane_state->src_rect.width <

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

492

pipe->plane_state->dst_rect.width))

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

534

if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

535

if (!is_dual_plane(pipe->plane_state->format) &&

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

536

pipe->plane_state->src_rect.width <= 5120) {

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

584

if (context->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

520

if (pipe->plane_state &&

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

521

(pipe->plane_state->src_rect.height <

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

522

pipe->plane_state->dst_rect.height ||

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

523

pipe->plane_state->src_rect.width <

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

524

pipe->plane_state->dst_rect.width))

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

566

if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

567

if (!is_dual_plane(pipe->plane_state->format) &&

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

568

pipe->plane_state->src_rect.width <= 5120) {

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

613

if (context->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

455

const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

458

surface->plane0.pitch = plane_state->plane_size.surface_pitch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

459

surface->plane1.pitch = plane_state->plane_size.chroma_pitch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

460

surface->plane0.height = plane_state->plane_size.surface_size.height;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

461

surface->plane0.width = plane_state->plane_size.surface_size.width;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

462

surface->plane1.height = plane_state->plane_size.chroma_size.height;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

463

surface->plane1.width = plane_state->plane_size.chroma_size.width;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

464

surface->dcc.enable = plane_state->dcc.enable;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

467

surface->dcc.informative.fraction_of_zero_size_request_plane0 = plane_state->dcc.independent_64b_blks;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

468

surface->dcc.informative.fraction_of_zero_size_request_plane1 = plane_state->dcc.independent_64b_blks_c;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

469

surface->dcc.plane0.pitch = plane_state->dcc.meta_pitch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

470

surface->dcc.plane1.pitch = plane_state->dcc.meta_pitch_c;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

473

switch (plane_state->tiling_info.gfxversion) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

480

surface->tiling = gfx9_to_dml2_swizzle_mode(plane_state->tiling_info.gfx9.swizzle);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

483

surface->tiling = gfx_addr3_to_dml2_swizzle_mode(plane_state->tiling_info.gfx_addr3.swizzle);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

501

if (pipe->plane_state == in && !pipe->prev_odm_pipe) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

503

temp_pipe->plane_state = pipe->plane_state;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

519

struct dml2_plane_parameters *plane, const struct dc_plane_state *plane_state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

522

const struct scaler_data *scaler_data = get_scaler_data_for_plane(dml_ctx, plane_state, context);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

529

switch (plane_state->format) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

578

} else if ((plane_state->ctx->dc->config.use_spl == true) &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

590

if (plane_state->ctx->dc->debug.always_scale == true) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

624

if (plane_state->mcm_luts.lut3d_data.lut3d_src == DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

627

switch (plane_state->mcm_luts.lut3d_data.gpu_mem_params.layout) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

637

switch (plane_state->mcm_luts.lut3d_data.gpu_mem_params.size) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

655

if (plane_state->cm.flags.bits.lut3d_dma_enable) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

658

switch (plane_state->cm.lut3d_dma.swizzle) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

668

switch (plane_state->cm.lut3d_dma.size) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

693

plane->composition.scaler_info.rect_out_width = plane_state->dst_rect.width;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

694

plane->composition.rotation_angle = (enum dml2_rotation_angle) plane_state->rotation;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

704

plane_state->dst_rect.height >= stream->src.height &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

171

if (dc_pipe->stream && dc_pipe->plane_state &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

173

dc_pipe->plane_state != dc_pipe->top_pipe->plane_state) &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

436

context->res_ctx.pipe_ctx[dc_pipe_idx].plane_state == context->stream_status[dc_stream_idx].plane_states[dc_plane_idx]) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

475

context->res_ctx.pipe_ctx[dc_pipe_idx].plane_state == phantom_status->plane_states[dc_plane_idx]) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

79

if (pipe->plane_state)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c

312

dc_main_pipes[0]->plane_state == NULL)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c

325

dc_phantom_pipes[0]->plane_state) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c

353

dc_main_pipes[0]->plane_state == NULL)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c

370

dc_phantom_pipes[0]->plane_state) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1175

if (pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

130

if (state->res_ctx.pipe_ctx[i].plane_state && get_plane_id(ctx, state, state->res_ctx.pipe_ctx[i].plane_state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

151

if (!pipe->plane_state || !pipe->stream)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

154

get_plane_id(ctx, state, pipe->plane_state, pipe->stream->stream_id,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

158

&& (!pipe->top_pipe || pipe->top_pipe->plane_state != pipe->plane_state)) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

167

if (mpc_pipe->plane_state != pipe->plane_state)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

233

if (pipe->plane_state)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

241

if (!pipe->plane_state && !pipe->stream)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

721

if (state->res_ctx.pipe_ctx[i].plane_state == plane &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

121

pipe->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

129

} else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

139

pipe->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

157

if (!pipe->plane_state)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

256

if (pipe->plane_state && !pipe->top_pipe &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

378

if (pipe->stream && pipe->plane_state && !pipe->top_pipe &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

462

if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

54

if (pipe->stream && pipe->plane_state && !pipe->top_pipe && !pipe->prev_odm_pipe &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

553

if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

56

bytes_per_pixel = pipe->plane_state->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

641

if (pipe->plane_state && !pipe->top_pipe &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

769

if (curr_pipe->top_pipe && curr_pipe->top_pipe->plane_state == curr_pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

775

curr_pipe->plane_state);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

786

memcpy(&phantom_plane->address, &curr_pipe->plane_state->address, sizeof(phantom_plane->address));

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

787

memcpy(&phantom_plane->scaling_quality, &curr_pipe->plane_state->scaling_quality,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

789

memcpy(&phantom_plane->src_rect, &curr_pipe->plane_state->src_rect, sizeof(phantom_plane->src_rect));

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

790

memcpy(&phantom_plane->dst_rect, &curr_pipe->plane_state->dst_rect, sizeof(phantom_plane->dst_rect));

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

791

memcpy(&phantom_plane->clip_rect, &curr_pipe->plane_state->clip_rect, sizeof(phantom_plane->clip_rect));

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

792

memcpy(&phantom_plane->plane_size, &curr_pipe->plane_state->plane_size,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

794

memcpy(&phantom_plane->tiling_info, &curr_pipe->plane_state->tiling_info,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

796

memcpy(&phantom_plane->dcc, &curr_pipe->plane_state->dcc, sizeof(phantom_plane->dcc));

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

798

phantom_plane->format = curr_pipe->plane_state->format;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

799

phantom_plane->rotation = curr_pipe->plane_state->rotation;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

800

phantom_plane->visible = curr_pipe->plane_state->visible;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

830

if (pipe->plane_state && pipe->stream && pipe->stream == phantom_stream &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

833

pipe->plane_state->flip_immediate = false;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

87

if (pipe->plane_state->dcc.enable)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

880

if (pipe->plane_state && pipe->stream && ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(state, pipe) == SUBVP_PHANTOM) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

890

if (pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

891

pipe->plane_state->is_phantom = false;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

929

if (!pipe_ctx->plane_state || !pipe_ctx->stream)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1000

if (pipe->plane_state == in && !pipe->prev_odm_pipe) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1002

temp_pipe->plane_state = pipe->plane_state;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1220

if (!pipe || !pipe->stream || !pipe->plane_state)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

308

if (get_plane_id(in_ctx, context, context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

350

if (context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream && context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_state &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

352

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_state != context->res_ctx.pipe_ctx[dc_pipe_ctx_index].top_pipe->plane_state) &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

526

if (get_plane_id(in_ctx, display_state, display_state->res_ctx.pipe_ctx[i].plane_state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

127

bool (*add_phantom_plane)(const struct dc *dc, struct dc_stream_state *stream, struct dc_plane_state *plane_state, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

130

struct dc_plane_state *plane_state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

184

if (pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

292

if (pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

155

struct dc_plane_state *plane_state,

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

169

&plane_state->address,

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.h

50

struct dc_plane_state *plane_state,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2406

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2410

if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

258

const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

262

switch (plane_state->format) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2762

default_adjust.in_color_space = pipe_ctx->plane_state->color_space;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2809

if (pipe_ctx->bottom_pipe->plane_state->visible) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2810

if (pipe_ctx->plane_state->visible)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2815

} else if (!pipe_ctx->plane_state->visible)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2818

} else if (!pipe_ctx->plane_state->visible)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2848

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2850

if (plane_state == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2855

&plane_state->address,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2856

plane_state->flip_immediate);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2858

plane_state->status.requested_address = plane_state->address;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2863

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2865

if (plane_state == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2868

plane_state->status.is_flip_pending =

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

287

const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2872

if (plane_state->status.is_flip_pending && !plane_state->visible)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2875

plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2878

plane_state->status.is_right_eye =\

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

298

tf = &plane_state->in_transfer_func;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

300

dce110_prescale_params(&prescale_params, plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

303

if (!plane_state->gamma_correction.is_identity &&

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

304

dce_use_lut(plane_state->format))

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

305

ipp->funcs->ipp_program_input_lut(ipp, &plane_state->gamma_correction);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3128

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3171

plane_state->format,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3172

&plane_state->tiling_info,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3173

&plane_state->plane_size,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3174

plane_state->rotation,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3178

mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3183

plane_state->format,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3184

&plane_state->tiling_info,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3185

plane_state->rotation);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3188

if (pipe_ctx->plane_state->update_flags.bits.full_update ||

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3189

pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3190

pipe_ctx->plane_state->update_flags.bits.gamma_change)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3191

hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3193

if (pipe_ctx->plane_state->update_flags.bits.full_update)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3203

(void *) pipe_ctx->plane_state,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3204

pipe_ctx->plane_state->address.grph.addr.high_part,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3205

pipe_ctx->plane_state->address.grph.addr.low_part,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3206

pipe_ctx->plane_state->src_rect.x,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3207

pipe_ctx->plane_state->src_rect.y,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3208

pipe_ctx->plane_state->src_rect.width,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3209

pipe_ctx->plane_state->src_rect.height,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3210

pipe_ctx->plane_state->dst_rect.x,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3211

pipe_ctx->plane_state->dst_rect.y,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3212

pipe_ctx->plane_state->dst_rect.width,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3213

pipe_ctx->plane_state->dst_rect.height,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3214

pipe_ctx->plane_state->clip_rect.x,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3215

pipe_ctx->plane_state->clip_rect.y,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3216

pipe_ctx->plane_state->clip_rect.width,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3217

pipe_ctx->plane_state->clip_rect.height);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3348

.rotation = pipe_ctx->plane_state->rotation,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3349

.mirror = pipe_ctx->plane_state->horizontal_mirror

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3365

pos_cpy.x += pipe_ctx->plane_state->src_rect.x;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3366

pos_cpy.y += pipe_ctx->plane_state->src_rect.y;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3369

if (pipe_ctx->plane_state->address.type

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3373

if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

101

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

105

if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

148

default_adjust.in_color_space = pipe_ctx->plane_state->color_space;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

188

if (!pipe_ctx->plane_state->visible)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

274

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

318

plane_state->format,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

319

&plane_state->tiling_info,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

320

&plane_state->plane_size,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

321

plane_state->rotation,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

325

mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

330

plane_state->format,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

331

&plane_state->tiling_info,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

332

plane_state->rotation);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

335

if (pipe_ctx->plane_state->update_flags.bits.full_update ||

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

336

pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

337

pipe_ctx->plane_state->update_flags.bits.gamma_change)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

338

hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

340

if (pipe_ctx->plane_state->update_flags.bits.full_update)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

350

(void *) pipe_ctx->plane_state,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

351

pipe_ctx->plane_state->address.grph.addr.high_part,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

352

pipe_ctx->plane_state->address.grph.addr.low_part,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

353

pipe_ctx->plane_state->src_rect.x,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

354

pipe_ctx->plane_state->src_rect.y,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

355

pipe_ctx->plane_state->src_rect.width,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

356

pipe_ctx->plane_state->src_rect.height,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

357

pipe_ctx->plane_state->dst_rect.x,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

358

pipe_ctx->plane_state->dst_rect.y,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

359

pipe_ctx->plane_state->dst_rect.width,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

360

pipe_ctx->plane_state->dst_rect.height,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

361

pipe_ctx->plane_state->clip_rect.x,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

362

pipe_ctx->plane_state->clip_rect.y,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

363

pipe_ctx->plane_state->clip_rect.width,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

364

pipe_ctx->plane_state->clip_rect.height);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1595

pipe_ctx->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2027

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2029

pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2030

if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2035

*addr = plane_state->address.grph_stereo.left_addr;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2036

plane_state->address.grph_stereo.left_addr =

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2037

plane_state->address.grph_stereo.right_addr;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2041

plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2042

plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2043

plane_state->address.grph_stereo.right_addr =

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2044

plane_state->address.grph_stereo.left_addr;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2045

plane_state->address.grph_stereo.right_meta_addr =

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2046

plane_state->address.grph_stereo.left_meta_addr;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2057

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2059

if (plane_state == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2066

&plane_state->address,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2067

plane_state->flip_immediate);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2069

plane_state->status.requested_address = plane_state->address;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2071

if (plane_state->flip_immediate)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2072

plane_state->status.current_address = plane_state->address;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2075

pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2079

const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2089

tf = &plane_state->in_transfer_func;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2092

&& !plane_state->gamma_correction.is_identity

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2093

&& dce_use_lut(plane_state->format))

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2094

dpp_base->funcs->dpp_program_input_lut(dpp_base, &plane_state->gamma_correction);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

243

(!pipe_ctx->plane_state && !old_pipe_ctx->plane_state) ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2810

&& pipe_ctx->plane_state

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2811

&& pipe_ctx->plane_state->flip_int_enabled

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2830

} else if (pipe_ctx->plane_state &&

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2831

pipe_ctx->plane_state->gamut_remap_matrix.enable_remap == true) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2835

pipe_ctx->plane_state->gamut_remap_matrix.matrix[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2844

if (pipe_ctx->plane_state && pipe_ctx->plane_state->layer_index > 0 && is_rgb_cspace(colorspace)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2850

if (top->plane_state && top->plane_state->layer_index == 0 && !top->plane_state->global_alpha)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2908

static void dcn10_update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2914

plane_state->format,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2916

plane_state->input_csc_color_matrix,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2917

plane_state->color_space,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2921

build_prescale_params(&bns_params, plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2941

bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2956

&& pipe_ctx->plane_state->pre_multiplied_alpha);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2957

if (pipe_ctx->plane_state->global_alpha) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2959

blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2968

if (pipe_ctx->plane_state->global_alpha)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2969

blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2984

if (!pipe_ctx->plane_state->update_flags.bits.full_update) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3018

pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3035

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3036

struct plane_size size = plane_state->plane_size;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3044

if (plane_state->update_flags.bits.full_update) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3099

if (plane_state->update_flags.bits.full_update) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3116

if (plane_state->update_flags.bits.full_update ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3117

plane_state->update_flags.bits.bpp_change)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3118

dcn10_update_dpp(dpp, plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3120

if (plane_state->update_flags.bits.full_update ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3121

plane_state->update_flags.bits.per_pixel_alpha_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3122

plane_state->update_flags.bits.global_alpha_change)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3125

if (plane_state->update_flags.bits.full_update ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3126

plane_state->update_flags.bits.per_pixel_alpha_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3127

plane_state->update_flags.bits.global_alpha_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3128

plane_state->update_flags.bits.scaling_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3129

plane_state->update_flags.bits.position_change) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3133

if (plane_state->update_flags.bits.full_update ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3134

plane_state->update_flags.bits.scaling_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3135

plane_state->update_flags.bits.position_change) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3153

if (plane_state->update_flags.bits.full_update) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3164

if (plane_state->update_flags.bits.full_update ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3165

plane_state->update_flags.bits.pixel_format_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3166

plane_state->update_flags.bits.horizontal_mirror_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3167

plane_state->update_flags.bits.rotation_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3168

plane_state->update_flags.bits.swizzle_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3169

plane_state->update_flags.bits.dcc_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3170

plane_state->update_flags.bits.bpp_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3171

plane_state->update_flags.bits.scaling_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3172

plane_state->update_flags.bits.plane_size_change) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3175

plane_state->format,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3176

&plane_state->tiling_info,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3178

plane_state->rotation,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3179

&plane_state->dcc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3180

plane_state->horizontal_mirror,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3238

struct fixed31_32 multiplier = pipe_ctx->plane_state->hdr_mult;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3281

if (pipe_ctx->plane_state->update_flags.bits.full_update)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3288

if (pipe_ctx->plane_state->update_flags.bits.full_update ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3289

pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3290

pipe_ctx->plane_state->update_flags.bits.gamma_change)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3291

hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3299

if (pipe_ctx->plane_state->update_flags.bits.full_update)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3319

!pipe_ctx->stream || !pipe_ctx->plane_state ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3656

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3661

if (plane_state == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3667

plane_state->status.is_flip_pending = plane_state->status.is_flip_pending || flip_pending;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3670

plane_state->status.current_address = plane_state->status.requested_address;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3672

if (plane_state->status.current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3674

plane_state->status.is_right_eye =

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3711

.rotation = pipe_ctx->plane_state->rotation,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3712

.mirror = pipe_ctx->plane_state->horizontal_mirror,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3719

int x_plane = pipe_ctx->plane_state->dst_rect.x;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3720

int y_plane = pipe_ctx->plane_state->dst_rect.y;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3723

bool is_primary_plane = (pipe_ctx->plane_state->layer_index == 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3727

? param.viewport.x : pipe_ctx->plane_state->clip_rect.x;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3728

int clip_width = pipe_ctx->plane_state->clip_rect.width;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3731

if ((pipe_ctx->plane_state->src_rect.width != pipe_ctx->plane_res.scl_data.viewport.width) ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3732

(pipe_ctx->plane_state->src_rect.height != pipe_ctx->plane_res.scl_data.viewport.height)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3755

x_pos = (x_pos - x_plane) * pipe_ctx->plane_state->src_rect.height /

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3756

pipe_ctx->plane_state->dst_rect.width;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3757

y_pos = (y_pos - y_plane) * pipe_ctx->plane_state->src_rect.width /

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3758

pipe_ctx->plane_state->dst_rect.height;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3760

x_pos = (x_pos - x_plane) * pipe_ctx->plane_state->src_rect.width /

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3761

pipe_ctx->plane_state->dst_rect.width;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3762

y_pos = (y_pos - y_plane) * pipe_ctx->plane_state->src_rect.height /

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3763

pipe_ctx->plane_state->dst_rect.height;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3764

clip_x = (clip_x - x_plane) * pipe_ctx->plane_state->src_rect.width /

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3765

pipe_ctx->plane_state->dst_rect.width;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3766

clip_width = clip_width * pipe_ctx->plane_state->src_rect.width /

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3767

pipe_ctx->plane_state->dst_rect.width;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3783

x_pos += pipe_ctx->plane_state->src_rect.x;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3784

y_pos += pipe_ctx->plane_state->src_rect.y;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3805

if (pipe_ctx->plane_state->address.type

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4190

struct dc_plane_state *plane_state,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4204

&plane_state->address,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

218

struct dc_plane_state *plane_state,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

79

const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1063

struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1069

if (plane_state->blend_tf.type == TF_TYPE_HWPWL)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1070

blend_lut = &plane_state->blend_tf.pwl;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1071

else if (plane_state->blend_tf.type == TF_TYPE_DISTRIBUTED_POINTS) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1072

cm_helper_translate_curve_to_hw_format(plane_state->ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1073

&plane_state->blend_tf,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1083

struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1089

if (plane_state->in_shaper_func.type == TF_TYPE_HWPWL)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1090

shaper_lut = &plane_state->in_shaper_func.pwl;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1091

else if (plane_state->in_shaper_func.type == TF_TYPE_DISTRIBUTED_POINTS) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1092

cm_helper_translate_curve_to_hw_format(plane_state->ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1093

&plane_state->in_shaper_func,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1099

if (plane_state->lut3d_func.state.bits.initialized == 1)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1101

&plane_state->lut3d_func.lut_3d);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1110

const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1118

if (dpp_base == NULL || plane_state == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1121

hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1122

hws->funcs.set_blend_lut(pipe_ctx, plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1124

tf = &plane_state->in_transfer_func;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1377

&& pipe_ctx->plane_state

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1378

&& pipe_ctx->plane_state->flip_int_enabled

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1401

if (pipe->plane_state != NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1402

flip_immediate = pipe->plane_state->flip_immediate;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1407

if (temp_pipe->plane_state != NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1408

flip_immediate = temp_pipe->plane_state->flip_immediate;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1420

if (temp_pipe->plane_state && temp_pipe->plane_state->flip_immediate) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1442

if (pipe->plane_state != NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1443

flip_immediate = pipe->plane_state->flip_immediate;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1447

if (temp_pipe->plane_state != NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1448

flip_immediate = temp_pipe->plane_state->flip_immediate;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1452

if (!lock && pipe->stream_res.gsl_group > 0 && pipe->plane_state &&

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1463

if (pipe->plane_state != NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1464

hw_locks.bits.triple_buffer_lock = pipe->plane_state->triplebuffer_flips;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1470

} else if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1504

if (old_pipe->plane_state && !old_is_phantom &&

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1505

new_pipe->plane_state && new_is_phantom) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1516

if (!old_pipe->plane_state && !new_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1519

if (!old_pipe->plane_state && new_pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1552

if (old_pipe->plane_state && old_is_phantom &&

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1553

new_pipe->plane_state && !new_is_phantom)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1556

if (old_pipe->plane_state && !new_pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1562

if (old_pipe->plane_state != new_pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1683

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1736

plane_state->update_flags.bits.bpp_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1737

plane_state->update_flags.bits.input_csc_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1738

plane_state->update_flags.bits.color_space_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1739

plane_state->update_flags.bits.coeff_reduction_change) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1740

struct dc_bias_and_scale bns_params = plane_state->bias_and_scale;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1744

plane_state->format,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1746

plane_state->input_csc_color_matrix,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1747

plane_state->color_space,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1752

plane_state->color_space,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1753

plane_state->cursor_csc_color_matrix);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1763

|| plane_state->update_flags.bits.global_alpha_change

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1764

|| plane_state->update_flags.bits.per_pixel_alpha_change) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1770

plane_state->update_flags.bits.scaling_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1771

plane_state->update_flags.bits.position_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1772

plane_state->update_flags.bits.per_pixel_alpha_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1774

pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1782

(context == dc->current_state && plane_state->update_flags.bits.position_change) ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1783

(context == dc->current_state && plane_state->update_flags.bits.scaling_change) ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1815

|| plane_state->update_flags.bits.gamut_remap_change

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1831

plane_state->update_flags.bits.pixel_format_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1832

plane_state->update_flags.bits.horizontal_mirror_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1833

plane_state->update_flags.bits.rotation_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1834

plane_state->update_flags.bits.swizzle_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1835

plane_state->update_flags.bits.dcc_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1836

plane_state->update_flags.bits.bpp_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1837

plane_state->update_flags.bits.scaling_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1838

plane_state->update_flags.bits.plane_size_change) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1839

struct plane_size size = plane_state->plane_size;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1844

plane_state->format,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1845

&plane_state->tiling_info,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1847

plane_state->rotation,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1848

&plane_state->dcc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1849

plane_state->horizontal_mirror,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1856

plane_state->update_flags.bits.addr_update) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1862

params.subvp_save_surf_addr.addr = &pipe_ctx->plane_state->address;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1939

!pipe_ctx->plane_state ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1940

!pipe_ctx->plane_state->visible);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1971

if (pipe_ctx->plane_state && (pipe_ctx->update_flags.raw ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1972

pipe_ctx->plane_state->update_flags.raw ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1976

if (pipe_ctx->plane_state && (pipe_ctx->update_flags.bits.enable ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1977

pipe_ctx->plane_state->update_flags.bits.hdr_mult))

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1980

if (pipe_ctx->plane_state &&

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1981

(pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1982

pipe_ctx->plane_state->update_flags.bits.gamma_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1983

pipe_ctx->plane_state->update_flags.bits.lut_3d ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1985

hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2017

if ((pipe_ctx->plane_state && pipe_ctx->plane_state->visible)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2062

if (pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2063

ASSERT(!pipe->plane_state->triplebuffer_flips);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2066

dc, pipe, pipe->plane_state->triplebuffer_flips);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2072

if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2074

if (context->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2131

(context->res_ctx.pipe_ctx[i].plane_state &&

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2163

if (pipe->plane_state && !pipe->top_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2189

&& (pipe->update_flags.raw || (pipe->plane_state && pipe->plane_state->update_flags.raw)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2272

if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable &&

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2312

if (pipe->plane_state && !pipe->top_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2504

if (pipe_ctx->plane_state == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2708

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2710

pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2711

if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2716

*addr = plane_state->address.grph_stereo.left_addr;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2717

plane_state->address.grph_stereo.left_addr =

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2718

plane_state->address.grph_stereo.right_addr;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2723

plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2724

plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2725

plane_state->address.grph_stereo.right_addr =

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2726

plane_state->address.grph_stereo.left_addr;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2727

plane_state->address.grph_stereo.right_meta_addr =

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2728

plane_state->address.grph_stereo.left_meta_addr;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2737

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2739

if (plane_state == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2745

vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2750

&plane_state->address,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2751

plane_state->flip_immediate);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2753

plane_state->status.requested_address = plane_state->address;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2755

if (plane_state->flip_immediate)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2756

plane_state->status.current_address = plane_state->address;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2759

pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2953

bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2963

blnd_cfg.pre_multiplied_alpha = pipe_ctx->plane_state->pre_multiplied_alpha;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2964

if (pipe_ctx->plane_state->global_alpha) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2966

blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2975

if (pipe_ctx->plane_state->global_alpha)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2976

blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2986

if (pipe_ctx->plane_state->format

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3001

if (!pipe_ctx->plane_state->update_flags.bits.full_update &&

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3098

if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

734

pipe_ctx->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

34

struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

36

struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

46

const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

140

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

144

if (plane_state == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

147

uma = plane_state->address;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

155

plane_state->flip_immediate);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

157

plane_state->status.requested_address = plane_state->address;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

159

if (plane_state->flip_immediate)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

160

plane_state->status.current_address = plane_state->address;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

163

pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

429

bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

455

if (pipe_ctx->plane_state->global_alpha_value)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

456

blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

488

if (!pipe_ctx->plane_state->update_flags.bits.full_update) {

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

543

if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) {

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

62

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

64

pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

66

if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

71

*addr = plane_state->address.grph_stereo.left_addr;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

72

plane_state->address.grph_stereo.left_addr =

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

73

plane_state->address.grph_stereo.right_addr;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

77

plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

78

plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

79

plane_state->address.grph_stereo.right_addr =

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

80

plane_state->address.grph_stereo.left_addr;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

81

plane_state->address.grph_stereo.right_meta_addr =

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

82

plane_state->address.grph_stereo.left_meta_addr;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1283

if (tg->funcs->get_pipe_update_pending && pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

236

struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

242

if (plane_state->blend_tf.type == TF_TYPE_HWPWL)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

243

blend_lut = &plane_state->blend_tf.pwl;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

244

else if (plane_state->blend_tf.type == TF_TYPE_DISTRIBUTED_POINTS) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

245

result = cm3_helper_translate_curve_to_hw_format(plane_state->ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

246

&plane_state->blend_tf, &dpp_base->regamma_params, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

319

const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

327

if (dpp_base == NULL || plane_state == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

332

if (plane_state->in_transfer_func.type == TF_TYPE_PREDEFINED)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

333

tf = plane_state->in_transfer_func.tf;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

337

if (plane_state->in_transfer_func.type == TF_TYPE_HWPWL)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

338

params = &plane_state->in_transfer_func.pwl;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

339

else if (plane_state->in_transfer_func.type == TF_TYPE_DISTRIBUTED_POINTS &&

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

340

cm3_helper_translate_curve_to_hw_format(plane_state->ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

341

&plane_state->in_transfer_func,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

349

hws->funcs.set_blend_lut(pipe_ctx, plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

352

hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

369

if (pipe_ctx->plane_state &&

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

370

pipe_ctx->plane_state->gamut_remap_matrix.enable_remap == true) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

374

pipe_ctx->plane_state->gamut_remap_matrix.matrix[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

611

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

614

if (pipe_ctx->plane_state == wb_info.writeback_source_plane) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

60

const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

64

const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

651

if (!pipe_ctx_old->plane_state &&

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1459

struct dc_plane_state *phantom_plane = phantom_pipe->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1466

if (pipe->plane_state && pipe->plane_state->update_flags.bits.position_change) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1468

phantom_plane->src_rect.x = pipe->plane_state->src_rect.x;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1469

phantom_plane->src_rect.y = pipe->plane_state->src_rect.y;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1470

phantom_plane->clip_rect.x = pipe->plane_state->clip_rect.x;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1471

phantom_plane->dst_rect.x = pipe->plane_state->dst_rect.x;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1472

phantom_plane->dst_rect.y = pipe->plane_state->dst_rect.y;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1474

phantom_pipe->plane_state->update_flags.bits.position_change = 1;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

241

if (!pipe->stream || !pipe->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

395

if (pipe->stream && pipe->plane_state && pipe_mall_type == SUBVP_MAIN) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

401

if (top_pipe_to_program && top_pipe_to_program->stream && top_pipe_to_program->plane_state) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

403

top_pipe_to_program->plane_state->flip_immediate)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

414

if (pipe->stream && pipe->plane_state && pipe_mall_type == SUBVP_MAIN &&

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

484

struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

493

if (plane_state->blend_tf.type == TF_TYPE_HWPWL)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

494

lut_params = &plane_state->blend_tf.pwl;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

495

else if (plane_state->blend_tf.type == TF_TYPE_DISTRIBUTED_POINTS) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

496

result = cm3_helper_translate_curve_to_hw_format(plane_state->ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

497

&plane_state->blend_tf,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

508

if (plane_state->in_shaper_func.type == TF_TYPE_HWPWL)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

509

lut_params = &plane_state->in_shaper_func.pwl;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

510

else if (plane_state->in_shaper_func.type == TF_TYPE_DISTRIBUTED_POINTS) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

512

rval = cm3_helper_translate_curve_to_hw_format(plane_state->ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

513

&plane_state->in_shaper_func,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

521

if (plane_state->lut3d_func.state.bits.initialized == 1)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

522

result = mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func.lut_3d, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

531

const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

541

if (mpc == NULL || plane_state == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

546

if (plane_state->in_transfer_func.type == TF_TYPE_PREDEFINED)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

547

tf = plane_state->in_transfer_func.tf;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

551

if (plane_state->in_transfer_func.type == TF_TYPE_HWPWL)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

552

params = &plane_state->in_transfer_func.pwl;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

553

else if (plane_state->in_transfer_func.type == TF_TYPE_DISTRIBUTED_POINTS &&

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

554

cm3_helper_translate_curve_to_hw_format(plane_state->ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

555

&plane_state->in_transfer_func,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

564

result = hws->funcs.set_mcm_luts(pipe_ctx, plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

685

if (pipe->stream && pipe->plane_state && hubp && hubp->funcs->hubp_update_mall_sel) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

715

pipe->plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO &&

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

716

!pipe->plane_state->address.tmz_surface ? 2 : 0,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

51

const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

55

const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1077

if ((!cur_pipe->plane_state && new_pipe->plane_state) ||

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1103

} else if (cur_pipe->plane_state == new_pipe->plane_state ||

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

866

&& pipe_ctx->plane_state

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

867

&& pipe_ctx->plane_state->flip_int_enabled

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

908

pipe_ctx->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

100

if (pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

101

ASSERT(pipe_ctx->plane_state->mcm_location == MPCC_MOVABLE_CM_LOCATION_BEFORE);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1044

if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

108

if (pipe_ctx->plane_state &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

109

pipe_ctx->plane_state->gamut_remap_matrix.enable_remap == true) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

113

pipe_ctx->plane_state->gamut_remap_matrix.matrix[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1137

.rotation = pipe_ctx->plane_state->rotation,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1138

.mirror = pipe_ctx->plane_state->horizontal_mirror,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1155

if ((pipe_ctx->plane_state->src_rect.width != pipe_ctx->plane_res.scl_data.viewport.width) ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1156

(pipe_ctx->plane_state->src_rect.height != pipe_ctx->plane_res.scl_data.viewport.height)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1198

x_pos += pipe_ctx->plane_state->src_rect.x;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1199

y_pos += pipe_ctx->plane_state->src_rect.y;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1328

if (!pipe->stream || !pipe->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1428

if (pipe_ctx->plane_state &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1429

pipe_ctx->plane_state->dcc.enable &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1430

pipe_ctx->plane_state->flip_immediate &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1431

pipe_ctx->plane_state->update_flags.bits.addr_update) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1910

if (opp_heads[slice_idx]->plane_state) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2002

if (mpc_pipe->plane_state && mpc_pipe->plane_state->mcm_luts.lut3d_data.lut3d_src

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2004

&& mpc_pipe->plane_state->mcm_shaper_3dlut_setting

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2247

!pipe_ctx->plane_state ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2248

!pipe_ctx->plane_state->visible);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2278

if (pipe_ctx->plane_state && (pipe_ctx->update_flags.raw ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2279

pipe_ctx->plane_state->update_flags.raw ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2283

if (pipe_ctx->plane_state && (pipe_ctx->update_flags.bits.enable ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2284

pipe_ctx->plane_state->update_flags.bits.hdr_mult))

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2287

if (pipe_ctx->plane_state &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2288

(pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2289

pipe_ctx->plane_state->update_flags.bits.gamma_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2290

pipe_ctx->plane_state->update_flags.bits.lut_3d ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2292

hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2324

if ((pipe_ctx->plane_state && pipe_ctx->plane_state->visible)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2348

if (pipe_ctx->plane_state

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2349

&& pipe_ctx->plane_state->update_flags.bits.cm_hist_change

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2351

hws->funcs.program_cm_hist(dc, pipe_ctx, pipe_ctx->plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2378

!pipe_ctx->plane_state || !pipe_ctx->plane_state->visible,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2429

if (pipe_ctx->plane_state && (pipe_ctx->update_flags.raw ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2430

pipe_ctx->plane_state->update_flags.raw ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2437

if (pipe_ctx->plane_state && (pipe_ctx->update_flags.bits.enable ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2438

pipe_ctx->plane_state->update_flags.bits.hdr_mult)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2443

if (pipe_ctx->plane_state &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2444

(pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2445

pipe_ctx->plane_state->update_flags.bits.gamma_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2446

pipe_ctx->plane_state->update_flags.bits.lut_3d ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2449

hwss_add_dpp_set_input_transfer_func(seq_state, dc, pipe_ctx, pipe_ctx->plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2478

if ((pipe_ctx->plane_state && pipe_ctx->plane_state->visible)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2503

if (pipe_ctx->plane_state

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2504

&& pipe_ctx->plane_state->update_flags.bits.cm_hist_change

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2508

pipe_ctx->plane_state->cm_hist_control, pipe_ctx->plane_state->color_space);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2529

if (pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2530

if (pipe->plane_state->triplebuffer_flips)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2535

dc, pipe, pipe->plane_state->triplebuffer_flips);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2541

if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2543

if (context->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2600

(context->res_ctx.pipe_ctx[i].plane_state &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2632

if (pipe->plane_state && !pipe->top_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2658

&& (pipe->update_flags.raw || (pipe->plane_state && pipe->plane_state->update_flags.raw)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2704

if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2745

if (pipe->plane_state && !pipe->top_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2825

if (pipe_ctx->plane_state == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2886

if (old_pipe->plane_state && !old_is_phantom &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2887

new_pipe->plane_state && new_is_phantom) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2898

if (!old_pipe->plane_state && !new_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2901

if (!old_pipe->plane_state && new_pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2934

if (old_pipe->plane_state && old_is_phantom &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2935

new_pipe->plane_state && !new_is_phantom)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2938

if (old_pipe->plane_state && !new_pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2944

if (old_pipe->plane_state != new_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3329

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3332

if (pipe_ctx->plane_state == wb_info->writeback_source_plane) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3577

pipe_ctx->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3684

&& pipe_ctx->plane_state

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3685

&& pipe_ctx->plane_state->flip_int_enabled

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3699

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3704

if (!hubp || !dpp || !plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3744

plane_state->update_flags.bits.bpp_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3745

plane_state->update_flags.bits.input_csc_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3746

plane_state->update_flags.bits.color_space_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3747

plane_state->update_flags.bits.coeff_reduction_change) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3752

hwss_add_dpp_set_cursor_matrix(seq_state, dpp, plane_state->color_space,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3753

&plane_state->cursor_csc_color_matrix);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3764

plane_state->update_flags.bits.global_alpha_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3765

plane_state->update_flags.bits.per_pixel_alpha_change) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3774

plane_state->update_flags.bits.scaling_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3775

plane_state->update_flags.bits.position_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3776

plane_state->update_flags.bits.per_pixel_alpha_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3778

pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3785

(context == dc->current_state && plane_state->update_flags.bits.position_change) ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3786

(context == dc->current_state && plane_state->update_flags.bits.scaling_change) ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3818

plane_state->update_flags.bits.gamut_remap_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3833

plane_state->update_flags.bits.pixel_format_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3834

plane_state->update_flags.bits.horizontal_mirror_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3835

plane_state->update_flags.bits.rotation_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3836

plane_state->update_flags.bits.swizzle_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3837

plane_state->update_flags.bits.dcc_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3838

plane_state->update_flags.bits.bpp_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3839

plane_state->update_flags.bits.scaling_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3840

plane_state->update_flags.bits.plane_size_change) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3841

struct plane_size size = plane_state->plane_size;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3845

plane_state->format, &plane_state->tiling_info, size,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3846

plane_state->rotation, &plane_state->dcc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3847

plane_state->horizontal_mirror, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3854

plane_state->update_flags.bits.addr_update) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3859

&pipe_ctx->plane_state->address, pipe_ctx->subvp_index);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3887

if (!hubp || !pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3890

per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3897

blnd_cfg.pre_multiplied_alpha = pipe_ctx->plane_state->pre_multiplied_alpha;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3898

if (pipe_ctx->plane_state->global_alpha) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3900

blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3909

if (pipe_ctx->plane_state->global_alpha)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3910

blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3920

if (pipe_ctx->plane_state->format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3927

if (!pipe_ctx->plane_state->update_flags.bits.full_update &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4021

struct fixed31_32 multiplier = pipe_ctx->plane_state->hdr_mult;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4049

if (pipe->stream && pipe->plane_state && hubp && hubp->funcs->hubp_update_mall_sel) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4078

pipe->plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4079

!pipe->plane_state->address.tmz_surface) ? 2 : 0;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

418

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

420

shaper_3dlut_setting = pipe_ctx->plane_state->mcm_shaper_3dlut_setting;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

421

lut1d_enable = pipe_ctx->plane_state->mcm_lut1d_enable;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

423

pipe_ctx->plane_state->mcm_location = MPCC_MOVABLE_CM_LOCATION_BEFORE;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

653

const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

663

if (plane_state->mcm_luts.lut3d_data.lut3d_src == DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

664

dcn401_populate_mcm_luts(dc, pipe_ctx, plane_state->mcm_luts, plane_state->lut_bank_a);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

669

pipe_ctx->plane_state->mcm_location = MPCC_MOVABLE_CM_LOCATION_BEFORE;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

671

if (plane_state->blend_tf.type == TF_TYPE_HWPWL)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

672

lut_params = &plane_state->blend_tf.pwl;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

673

else if (plane_state->blend_tf.type == TF_TYPE_DISTRIBUTED_POINTS) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

674

rval = cm3_helper_translate_curve_to_hw_format(plane_state->ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

675

&plane_state->blend_tf,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

683

if (plane_state->in_shaper_func.type == TF_TYPE_HWPWL)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

684

lut_params = &plane_state->in_shaper_func.pwl;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

685

else if (plane_state->in_shaper_func.type == TF_TYPE_DISTRIBUTED_POINTS) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

687

rval = cm3_helper_translate_curve_to_hw_format(plane_state->ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

688

&plane_state->in_shaper_func,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

696

if (plane_state->lut3d_func.state.bits.initialized == 1)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

697

result &= mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func.lut_3d, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

40

const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1124

if ((!cur_pipe->plane_state && new_pipe->plane_state) ||

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1150

} else if (cur_pipe->plane_state == new_pipe->plane_state ||

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

302

bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

313

blnd_cfg.pre_multiplied_alpha = pipe_ctx->plane_state->pre_multiplied_alpha;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

314

if (pipe_ctx->plane_state->global_alpha) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

316

blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

325

if (pipe_ctx->plane_state->global_alpha)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

326

blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

336

if (pipe_ctx->plane_state->format

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

351

if (!pipe_ctx->plane_state->update_flags.bits.full_update &&

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

386

const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

393

plane_state->cm_hist_control, plane_state->color_space);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

484

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

488

pipe_ctx->plane_state->mcm_location = (bPostBlend) ?

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

503

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

505

shaper_3dlut_setting = pipe_ctx->plane_state->mcm_shaper_3dlut_setting;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

506

lut1d_enable = pipe_ctx->plane_state->mcm_lut1d_enable;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

508

pipe_ctx->plane_state->mcm_location = MPCC_MOVABLE_CM_LOCATION_BEFORE;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

894

const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

904

if (plane_state->mcm_luts.lut3d_data.lut3d_src == DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

905

dcn42_populate_mcm_luts(dc, pipe_ctx, plane_state->mcm_luts, plane_state->lut_bank_a);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

910

pipe_ctx->plane_state->mcm_location = MPCC_MOVABLE_CM_LOCATION_BEFORE;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

912

if (plane_state->blend_tf.type == TF_TYPE_HWPWL)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

913

lut_params = &plane_state->blend_tf.pwl;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

914

else if (plane_state->blend_tf.type == TF_TYPE_DISTRIBUTED_POINTS) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

915

rval = cm3_helper_translate_curve_to_hw_format(plane_state->ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

916

&plane_state->blend_tf,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

924

if (plane_state->in_shaper_func.type == TF_TYPE_HWPWL)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

925

lut_params = &plane_state->in_shaper_func.pwl;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

926

else if (plane_state->in_shaper_func.type == TF_TYPE_DISTRIBUTED_POINTS) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

928

rval = cm3_helper_translate_curve_to_hw_format(plane_state->ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

929

&plane_state->in_shaper_func,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

937

if (plane_state->lut3d_func.state.bits.initialized == 1)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

938

result &= mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func.lut_3d, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h

16

const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h

19

const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1273

void (*clear_surface_dcc_and_tiling)(struct pipe_ctx *pipe_ctx, struct dc_plane_state *plane_state, bool clear_tiling);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1932

struct dc *dc, struct pipe_ctx *pipe_ctx, struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

94

struct dc_plane_state *plane_state;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

191

const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

193

const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

195

const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

230

const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

93

const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/inc/core_types.h

160

const struct dc_plane_state *plane_state,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

174

struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/inc/core_types.h

459

struct dc_plane_state *plane_state;

drivers/gpu/drm/amd/display/dc/inc/resource.h

166

struct dc_plane_state *const *plane_state,

drivers/gpu/drm/amd/display/dc/inc/resource.h

324

struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/inc/resource.h

334

const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

565

if (pipe_ctx->plane_state == NULL)

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

966

enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps)

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

970

if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.h

42

enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps);

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1045

static enum dc_status dce110_validate_plane(const struct dc_plane_state *plane_state,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1049

if (((plane_state->dst_rect.width * 2) < plane_state->src_rect.width) ||

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1050

((plane_state->dst_rect.height * 2) < plane_state->src_rect.height))

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

940

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

942

if (pipe_ctx->plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1180

static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1182

if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1184

&& plane_state->src_rect.width > 0

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1185

&& (unsigned int)plane_state->src_rect.width > caps->max_video_width)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1249

static enum dc_status dcn10_patch_unknown_plane_state(struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1251

enum surface_pixel_format surf_pix_format = plane_state->format;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1261

plane_state->tiling_info.gfx9.swizzle = swizzle;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1549

if (prev_odm_pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1599

ASSERT(primary_pipe->plane_state);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1815

odm_pipe->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1828

if (pipe->plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1837

if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1843

hsplit_pipe->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1851

if (pipe->plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1890

if (pipe->plane_state &&

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1891

(pipe->plane_state->dst_rect.width <= 16 ||

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1892

pipe->plane_state->dst_rect.height <= 16 ||

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1893

pipe->plane_state->src_rect.width <= 16 ||

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1894

pipe->plane_state->src_rect.height <= 16))

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1899

(!pipe->top_pipe || pipe->top_pipe->plane_state != pipe->plane_state))

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1951

&& pipe->plane_state && is_dual_plane(pipe->plane_state->format)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1952

&& pipe->plane_state->src_rect.width <= 1920

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1953

&& pipe->plane_state->src_rect.height <= 1080)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1996

else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2004

pipe->top_pipe->plane_state == pipe->plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2038

if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2107

if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2118

if (!pipe->plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2121

if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2125

if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2130

if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2155

} else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2253

enum dc_status dcn20_patch_unknown_plane_state(struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2255

enum surface_pixel_format surf_pix_format = plane_state->format;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2258

plane_state->tiling_info.gfx9.swizzle = DC_SW_64KB_S;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2260

plane_state->tiling_info.gfx9.swizzle = DC_SW_64KB_D;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

167

enum dc_status dcn20_patch_unknown_plane_state(struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1387

static enum dc_status dcn21_patch_unknown_plane_state(struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1389

if (plane_state->ctx->dc->debug.disable_dcc == DCC_ENABLE) {

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1390

plane_state->dcc.enable = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1392

plane_state->dcc.meta_pitch = ((plane_state->src_rect.width + 1023) / 1024) * 1024;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1395

return dcn20_patch_unknown_plane_state(plane_state);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

865

&& pipe->plane_state && mpo_pipe

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

866

&& memcmp(&mpo_pipe->plane_state->clip_rect,

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

869

ASSERT(mpo_pipe->plane_state != pipe->plane_state);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

888

if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

899

if (!pipe->plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

902

if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

906

if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

931

} else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1735

ASSERT(pri_pipe->plane_state);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1871

&& pipe->plane_state && mpo_pipe

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1872

&& memcmp(&mpo_pipe->plane_state->clip_rect,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1875

ASSERT(mpo_pipe->plane_state != pipe->plane_state);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1899

pipe->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1908

} else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1918

pipe->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1941

if (!pipe->plane_state && !odm)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1952

old_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1955

old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1977

old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1996

old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2017

if (pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1818

if (pipe->plane_state &&

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1819

(pipe->plane_state->src_rect.height < pipe->plane_state->dst_rect.height ||

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1820

pipe->plane_state->src_rect.width < pipe->plane_state->dst_rect.width))

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1860

if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1861

if (!is_dual_plane(pipe->plane_state->format) && pipe->plane_state->src_rect.width <= 5120) {

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1810

(res_ctx->pipe_ctx[i].plane_state && (res_ctx->pipe_ctx[i].plane_state->src_rect.width

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1811

!= res_ctx->pipe_ctx[i].plane_state->dst_rect.width ||

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1812

res_ctx->pipe_ctx[i].plane_state->src_rect.height

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1813

!= res_ctx->pipe_ctx[i].plane_state->dst_rect.height)))

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1816

if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state != res_ctx->pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1869

split_required = split_required || (pipe->plane_state && pipe->plane_state->src_rect.width > 5120);

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1918

|| (pipe->plane_state && pipe->plane_state->src_rect.width > 5120);

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1947

if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1948

if (is_dual_plane(pipe->plane_state->format)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1949

&& pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) {

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1952

} else if (!is_dual_plane(pipe->plane_state->format)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1953

&& pipe->plane_state->src_rect.width <= 5120

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1829

if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1830

if (is_dual_plane(pipe->plane_state->format)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1831

&& pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) {

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1834

} else if (!is_dual_plane(pipe->plane_state->format)) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1817

if (curr_pipe->top_pipe && curr_pipe->top_pipe->plane_state == curr_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1821

dc_state_create_phantom_plane(dc, context, curr_pipe->plane_state));

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1826

memcpy(&phantom_plane->address, &curr_pipe->plane_state->address, sizeof(phantom_plane->address));

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1827

memcpy(&phantom_plane->scaling_quality, &curr_pipe->plane_state->scaling_quality,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1829

memcpy(&phantom_plane->src_rect, &curr_pipe->plane_state->src_rect, sizeof(phantom_plane->src_rect));

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1830

memcpy(&phantom_plane->dst_rect, &curr_pipe->plane_state->dst_rect, sizeof(phantom_plane->dst_rect));

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1831

memcpy(&phantom_plane->clip_rect, &curr_pipe->plane_state->clip_rect, sizeof(phantom_plane->clip_rect));

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1832

memcpy(&phantom_plane->plane_size, &curr_pipe->plane_state->plane_size,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1834

memcpy(&phantom_plane->tiling_info, &curr_pipe->plane_state->tiling_info,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1836

memcpy(&phantom_plane->dcc, &curr_pipe->plane_state->dcc, sizeof(phantom_plane->dcc));

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1837

phantom_plane->format = curr_pipe->plane_state->format;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1838

phantom_plane->rotation = curr_pipe->plane_state->rotation;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1839

phantom_plane->visible = curr_pipe->plane_state->visible;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1903

if (pipe->plane_state && pipe->stream && pipe->stream == phantom_stream &&

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1906

pipe->plane_state->flip_immediate = false;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

128

pipe->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

136

} else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

146

pipe->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

165

if (!pipe->plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

207

if (pipe->plane_state && pipe->plane_state->rotation != ROTATION_ANGLE_0)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

223

if (pipe->plane_state) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

224

if (pipe->stream->timing.v_addressable != pipe->plane_state->dst_rect.height &&

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

225

pipe->stream->timing.v_addressable != pipe->plane_state->src_rect.height) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

263

if (pipe_ctx->stream && pipe_ctx->plane_state && dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

278

if (pipe_ctx->stream && pipe_ctx->plane_state && dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

349

current_plane = context->res_ctx.pipe_ctx[j].plane_state;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

352

context->res_ctx.pipe_ctx[k].plane_state == current_plane) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

361

context->res_ctx.pipe_ctx[k].plane_state == current_plane) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

406

if (pipe->plane_state && !disable_unbounded_requesting && pipe->plane_state->tiling_info.gfx9.swizzle != DC_SW_LINEAR) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

407

if (!is_dual_plane(pipe->plane_state->format)) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

410

if (pipe->plane_state->src_rect.width >= 5120 &&

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

411

pipe->plane_state->src_rect.height >= 2880)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

599

pipe->plane_state->src_rect.width == width &&

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

600

pipe->plane_state->src_rect.height == height &&

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

601

pipe->plane_state->dst_rect.width == width &&

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

602

pipe->plane_state->dst_rect.height == height)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1910

enum dc_status dcn35_patch_unknown_plane_state(struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1912

plane_state->tiling_info.gfxversion = DcGfxVersion9;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1913

dcn20_patch_unknown_plane_state(plane_state);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

38

enum dc_status dcn35_patch_unknown_plane_state(struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1788

enum dc_status dcn401_patch_unknown_plane_state(struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1790

plane_state->tiling_info.gfxversion = DcGfxAddr3;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1791

plane_state->tiling_info.gfx_addr3.swizzle = DC_ADDR3_SW_64KB_2D;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

23

enum dc_status dcn401_patch_unknown_plane_state(struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c

22

if (context->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/armada/armada_overlay.c

266

struct drm_plane_state *plane_state;

drivers/gpu/drm/armada/armada_overlay.c

278

plane_state = drm_atomic_get_plane_state(state, plane);

drivers/gpu/drm/armada/armada_overlay.c

279

if (IS_ERR(plane_state)) {

drivers/gpu/drm/armada/armada_overlay.c

280

ret = PTR_ERR(plane_state);

drivers/gpu/drm/armada/armada_overlay.c

284

ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);

drivers/gpu/drm/armada/armada_overlay.c

288

drm_atomic_set_fb_for_plane(plane_state, fb);

drivers/gpu/drm/armada/armada_overlay.c

289

plane_state->crtc_x = crtc_x;

drivers/gpu/drm/armada/armada_overlay.c

290

plane_state->crtc_y = crtc_y;

drivers/gpu/drm/armada/armada_overlay.c

291

plane_state->crtc_h = crtc_h;

drivers/gpu/drm/armada/armada_overlay.c

292

plane_state->crtc_w = crtc_w;

drivers/gpu/drm/armada/armada_overlay.c

293

plane_state->src_x = src_x;

drivers/gpu/drm/armada/armada_overlay.c

294

plane_state->src_y = src_y;

drivers/gpu/drm/armada/armada_overlay.c

295

plane_state->src_h = src_h;

drivers/gpu/drm/armada/armada_overlay.c

296

plane_state->src_w = src_w;

drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c

144

struct drm_plane_state *plane_state)

drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c

164

struct drm_plane_state *plane_state)

drivers/gpu/drm/ast/ast_cursor.c

194

struct drm_plane_state *plane_state = &shadow_plane_state->base;

drivers/gpu/drm/ast/ast_cursor.c

195

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/ast/ast_cursor.c

251

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/ast/ast_cursor.c

252

struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/ast/ast_cursor.c

253

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/ast/ast_cursor.c

269

if (drm_atomic_helper_damage_merged(old_plane_state, plane_state, &damage)) {

drivers/gpu/drm/ast/ast_cursor.c

284

writel(plane_state->crtc_x, sig + AST_HWC_SIGNATURE_X);

drivers/gpu/drm/ast/ast_cursor.c

285

writel(plane_state->crtc_y, sig + AST_HWC_SIGNATURE_Y);

drivers/gpu/drm/ast/ast_cursor.c

290

if (plane_state->crtc_x < 0) {

drivers/gpu/drm/ast/ast_cursor.c

291

x_offset = (-plane_state->crtc_x) + offset_x;

drivers/gpu/drm/ast/ast_cursor.c

295

x = plane_state->crtc_x;

drivers/gpu/drm/ast/ast_cursor.c

297

if (plane_state->crtc_y < 0) {

drivers/gpu/drm/ast/ast_cursor.c

298

y_offset = (-plane_state->crtc_y) + offset_y;

drivers/gpu/drm/ast/ast_cursor.c

302

y = plane_state->crtc_y;

drivers/gpu/drm/ast/ast_mode.c

562

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/ast/ast_mode.c

563

struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/ast/ast_mode.c

564

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/ast/ast_mode.c

568

struct drm_crtc *crtc = plane_state->crtc;

drivers/gpu/drm/ast/ast_mode.c

582

drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

613

struct atmel_hlcdc_plane_state *plane_state;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

622

plane_state =

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

625

pixels = (plane_state->src_w * plane_state->src_h) -

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

626

(plane_state->disc_w * plane_state->disc_h);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

628

for (i = 0; i < plane_state->nplanes; i++)

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

629

load += pixels * plane_state->bpp[i];

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

632

plane_state->ahb_id = 0;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

634

plane_state->ahb_id = 1;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

636

ahb_load[plane_state->ahb_id] += load;

drivers/gpu/drm/drm_atomic.c

1588

struct drm_plane_state *plane_state =

drivers/gpu/drm/drm_atomic.c

1591

if (IS_ERR(plane_state))

drivers/gpu/drm/drm_atomic.c

1592

return PTR_ERR(plane_state);

drivers/gpu/drm/drm_atomic.c

1594

if (plane_state->color_pipeline) {

drivers/gpu/drm/drm_atomic.c

1824

struct drm_plane_state *plane_state)

drivers/gpu/drm/drm_atomic.c

1828

ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);

drivers/gpu/drm/drm_atomic.c

1832

drm_atomic_set_fb_for_plane(plane_state, NULL);

drivers/gpu/drm/drm_atomic.c

1833

plane_state->crtc_x = 0;

drivers/gpu/drm/drm_atomic.c

1834

plane_state->crtc_y = 0;

drivers/gpu/drm/drm_atomic.c

1835

plane_state->crtc_w = 0;

drivers/gpu/drm/drm_atomic.c

1836

plane_state->crtc_h = 0;

drivers/gpu/drm/drm_atomic.c

1837

plane_state->src_x = 0;

drivers/gpu/drm/drm_atomic.c

1838

plane_state->src_y = 0;

drivers/gpu/drm/drm_atomic.c

1839

plane_state->src_w = 0;

drivers/gpu/drm/drm_atomic.c

1840

plane_state->src_h = 0;

drivers/gpu/drm/drm_atomic.c

2014

struct drm_plane_state *plane_state;

drivers/gpu/drm/drm_atomic.c

2030

for_each_new_plane_in_state(state, plane, plane_state, i)

drivers/gpu/drm/drm_atomic.c

2031

drm_atomic_plane_print_state(p, plane_state);

drivers/gpu/drm/drm_atomic.c

551

struct drm_plane_state *plane_state;

drivers/gpu/drm/drm_atomic.c

561

plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/drm_atomic.c

562

if (plane_state)

drivers/gpu/drm/drm_atomic.c

563

return plane_state;

drivers/gpu/drm/drm_atomic.c

569

plane_state = plane->funcs->atomic_duplicate_state(plane);

drivers/gpu/drm/drm_atomic.c

570

if (!plane_state)

drivers/gpu/drm/drm_atomic.c

573

state->planes[index].state_to_destroy = plane_state;

drivers/gpu/drm/drm_atomic.c

576

state->planes[index].new_state = plane_state;

drivers/gpu/drm/drm_atomic.c

577

plane_state->state = state;

drivers/gpu/drm/drm_atomic.c

580

plane->base.id, plane->name, plane_state, state);

drivers/gpu/drm/drm_atomic.c

582

if (plane_state->crtc) {

drivers/gpu/drm/drm_atomic.c

586

plane_state->crtc);

drivers/gpu/drm/drm_atomic.c

591

return plane_state;

drivers/gpu/drm/drm_atomic_helper.c

2196

struct drm_plane_state *plane_state;

drivers/gpu/drm/drm_atomic_helper.c

2200

for_each_new_plane_in_state(state, plane, plane_state, i) {

drivers/gpu/drm/drm_atomic_helper.c

2201

struct drm_framebuffer *new_fb = plane_state->fb;

drivers/gpu/drm/drm_atomic_helper.c

2213

WARN_ON_ONCE(plane->state->crtc_x != plane_state->crtc_x);

drivers/gpu/drm/drm_atomic_helper.c

2214

WARN_ON_ONCE(plane->state->crtc_y != plane_state->crtc_y);

drivers/gpu/drm/drm_atomic_helper.c

2215

WARN_ON_ONCE(plane->state->src_x != plane_state->src_x);

drivers/gpu/drm/drm_atomic_helper.c

2216

WARN_ON_ONCE(plane->state->src_y != plane_state->src_y);

drivers/gpu/drm/drm_atomic_helper.c

2222

WARN_ON_ONCE(plane_state->fb != old_fb);

drivers/gpu/drm/drm_atomic_helper.c

3408

struct drm_plane_state *plane_state;

drivers/gpu/drm/drm_atomic_helper.c

3416

plane_state = drm_atomic_get_plane_state(state, plane);

drivers/gpu/drm/drm_atomic_helper.c

3417

if (IS_ERR(plane_state)) {

drivers/gpu/drm/drm_atomic_helper.c

3418

ret = PTR_ERR(plane_state);

drivers/gpu/drm/drm_atomic_helper.c

3422

ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);

drivers/gpu/drm/drm_atomic_helper.c

3425

drm_atomic_set_fb_for_plane(plane_state, fb);

drivers/gpu/drm/drm_atomic_helper.c

3426

plane_state->crtc_x = crtc_x;

drivers/gpu/drm/drm_atomic_helper.c

3427

plane_state->crtc_y = crtc_y;

drivers/gpu/drm/drm_atomic_helper.c

3428

plane_state->crtc_w = crtc_w;

drivers/gpu/drm/drm_atomic_helper.c

3429

plane_state->crtc_h = crtc_h;

drivers/gpu/drm/drm_atomic_helper.c

3430

plane_state->src_x = src_x;

drivers/gpu/drm/drm_atomic_helper.c

3431

plane_state->src_y = src_y;

drivers/gpu/drm/drm_atomic_helper.c

3432

plane_state->src_w = src_w;

drivers/gpu/drm/drm_atomic_helper.c

3433

plane_state->src_h = src_h;

drivers/gpu/drm/drm_atomic_helper.c

3459

struct drm_plane_state *plane_state;

drivers/gpu/drm/drm_atomic_helper.c

3467

plane_state = drm_atomic_get_plane_state(state, plane);

drivers/gpu/drm/drm_atomic_helper.c

3468

if (IS_ERR(plane_state)) {

drivers/gpu/drm/drm_atomic_helper.c

3469

ret = PTR_ERR(plane_state);

drivers/gpu/drm/drm_atomic_helper.c

3473

if (plane_state->crtc && plane_state->crtc->cursor == plane)

drivers/gpu/drm/drm_atomic_helper.c

3474

plane_state->state->legacy_cursor_update = true;

drivers/gpu/drm/drm_atomic_helper.c

3476

ret = __drm_atomic_helper_disable_plane(plane, plane_state);

drivers/gpu/drm/drm_atomic_helper.c

3560

struct drm_plane_state *plane_state;

drivers/gpu/drm/drm_atomic_helper.c

3600

for_each_new_plane_in_state(state, plane, plane_state, i) {

drivers/gpu/drm/drm_atomic_helper.c

3601

ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);

drivers/gpu/drm/drm_atomic_helper.c

3605

drm_atomic_set_fb_for_plane(plane_state, NULL);

drivers/gpu/drm/drm_atomic_helper.c

3747

struct drm_plane_state *plane_state;

drivers/gpu/drm/drm_atomic_helper.c

3749

plane_state = drm_atomic_get_plane_state(state, plane);

drivers/gpu/drm/drm_atomic_helper.c

3750

if (IS_ERR(plane_state)) {

drivers/gpu/drm/drm_atomic_helper.c

3751

err = PTR_ERR(plane_state);

drivers/gpu/drm/drm_atomic_helper.c

3755

if (plane_state->color_pipeline) {

drivers/gpu/drm/drm_atomic_helper.c

3937

struct drm_plane_state *plane_state;

drivers/gpu/drm/drm_atomic_helper.c

3948

plane_state = drm_atomic_get_plane_state(state, plane);

drivers/gpu/drm/drm_atomic_helper.c

3949

if (IS_ERR(plane_state))

drivers/gpu/drm/drm_atomic_helper.c

3950

return PTR_ERR(plane_state);

drivers/gpu/drm/drm_atomic_helper.c

3952

ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);

drivers/gpu/drm/drm_atomic_helper.c

3955

drm_atomic_set_fb_for_plane(plane_state, fb);

drivers/gpu/drm/drm_atomic_helper.c

82

struct drm_plane_state *plane_state,

drivers/gpu/drm/drm_atomic_helper.c

893

int drm_atomic_helper_check_plane_state(struct drm_plane_state *plane_state,

drivers/gpu/drm/drm_atomic_helper.c

900

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/drm_atomic_helper.c

901

struct drm_rect *src = &plane_state->src;

drivers/gpu/drm/drm_atomic_helper.c

902

struct drm_rect *dst = &plane_state->dst;

drivers/gpu/drm/drm_atomic_helper.c

903

unsigned int rotation = plane_state->rotation;

drivers/gpu/drm/drm_atomic_helper.c

907

WARN_ON(plane_state->crtc && plane_state->crtc != crtc_state->crtc);

drivers/gpu/drm/drm_atomic_helper.c

909

*src = drm_plane_state_src(plane_state);

drivers/gpu/drm/drm_atomic_helper.c

910

*dst = drm_plane_state_dest(plane_state);

drivers/gpu/drm/drm_atomic_helper.c

913

plane_state->visible = false;

drivers/gpu/drm/drm_atomic_helper.c

918

if (WARN_ON(!plane_state->crtc)) {

drivers/gpu/drm/drm_atomic_helper.c

919

plane_state->visible = false;

drivers/gpu/drm/drm_atomic_helper.c

924

drm_dbg_kms(plane_state->plane->dev,

drivers/gpu/drm/drm_atomic_helper.c

935

drm_dbg_kms(plane_state->plane->dev,

drivers/gpu/drm/drm_atomic_helper.c

937

drm_rect_debug_print("src: ", &plane_state->src, true);

drivers/gpu/drm/drm_atomic_helper.c

938

drm_rect_debug_print("dst: ", &plane_state->dst, false);

drivers/gpu/drm/drm_atomic_helper.c

945

plane_state->visible = drm_rect_clip_scaled(src, dst, &clip);

drivers/gpu/drm/drm_atomic_helper.c

949

if (!plane_state->visible)

drivers/gpu/drm/drm_atomic_helper.c

960

drm_dbg_kms(plane_state->plane->dev,

drivers/gpu/drm/drm_atomic_helper.c

97

if (plane_state->crtc) {

drivers/gpu/drm/drm_atomic_helper.c

98

crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);

drivers/gpu/drm/drm_atomic_state_helper.c

247

void __drm_atomic_helper_plane_state_reset(struct drm_plane_state *plane_state,

drivers/gpu/drm/drm_atomic_state_helper.c

252

plane_state->plane = plane;

drivers/gpu/drm/drm_atomic_state_helper.c

253

plane_state->rotation = DRM_MODE_ROTATE_0;

drivers/gpu/drm/drm_atomic_state_helper.c

255

plane_state->alpha = DRM_BLEND_ALPHA_OPAQUE;

drivers/gpu/drm/drm_atomic_state_helper.c

256

plane_state->pixel_blend_mode = DRM_MODE_BLEND_PREMULTI;

drivers/gpu/drm/drm_atomic_state_helper.c

262

plane_state->color_encoding = val;

drivers/gpu/drm/drm_atomic_state_helper.c

269

plane_state->color_range = val;

drivers/gpu/drm/drm_atomic_state_helper.c

274

plane_state->color_pipeline = NULL;

drivers/gpu/drm/drm_atomic_state_helper.c

281

plane_state->zpos = val;

drivers/gpu/drm/drm_atomic_state_helper.c

282

plane_state->normalized_zpos = val;

drivers/gpu/drm/drm_atomic_state_helper.c

290

plane_state->hotspot_x = val;

drivers/gpu/drm/drm_atomic_state_helper.c

297

plane_state->hotspot_y = val;

drivers/gpu/drm/drm_atomic_state_helper.c

315

struct drm_plane_state *plane_state)

drivers/gpu/drm/drm_atomic_state_helper.c

317

if (plane_state)

drivers/gpu/drm/drm_atomic_state_helper.c

318

__drm_atomic_helper_plane_state_reset(plane_state, plane);

drivers/gpu/drm/drm_atomic_state_helper.c

320

plane->state = plane_state;

drivers/gpu/drm/drm_atomic_uapi.c

1259

struct drm_plane_state *plane_state;

drivers/gpu/drm/drm_atomic_uapi.c

1263

plane_state = drm_atomic_get_plane_state(state, plane);

drivers/gpu/drm/drm_atomic_uapi.c

1264

if (IS_ERR(plane_state)) {

drivers/gpu/drm/drm_atomic_uapi.c

1265

ret = PTR_ERR(plane_state);

drivers/gpu/drm/drm_atomic_uapi.c

1271

ret = drm_atomic_plane_get_property(plane, plane_state,

drivers/gpu/drm/drm_atomic_uapi.c

1297

plane_state, file_priv,

drivers/gpu/drm/drm_atomic_uapi.c

1303

struct drm_plane_state *plane_state;

drivers/gpu/drm/drm_atomic_uapi.c

1320

plane_state = drm_atomic_get_plane_state(state, colorop->plane);

drivers/gpu/drm/drm_atomic_uapi.c

1321

if (IS_ERR(plane_state)) {

drivers/gpu/drm/drm_atomic_uapi.c

1322

ret = PTR_ERR(plane_state);

drivers/gpu/drm/drm_atomic_uapi.c

1325

plane_state->color_mgmt_changed |= replaced;

drivers/gpu/drm/drm_atomic_uapi.c

190

drm_atomic_set_crtc_for_plane(struct drm_plane_state *plane_state,

drivers/gpu/drm/drm_atomic_uapi.c

193

struct drm_plane *plane = plane_state->plane;

drivers/gpu/drm/drm_atomic_uapi.c

196

if (plane_state->crtc == crtc)

drivers/gpu/drm/drm_atomic_uapi.c

198

if (plane_state->crtc) {

drivers/gpu/drm/drm_atomic_uapi.c

199

crtc_state = drm_atomic_get_crtc_state(plane_state->state,

drivers/gpu/drm/drm_atomic_uapi.c

200

plane_state->crtc);

drivers/gpu/drm/drm_atomic_uapi.c

207

plane_state->crtc = crtc;

drivers/gpu/drm/drm_atomic_uapi.c

210

crtc_state = drm_atomic_get_crtc_state(plane_state->state,

drivers/gpu/drm/drm_atomic_uapi.c

220

plane->base.id, plane->name, plane_state,

drivers/gpu/drm/drm_atomic_uapi.c

225

plane->base.id, plane->name, plane_state);

drivers/gpu/drm/drm_atomic_uapi.c

242

drm_atomic_set_fb_for_plane(struct drm_plane_state *plane_state,

drivers/gpu/drm/drm_atomic_uapi.c

245

struct drm_plane *plane = plane_state->plane;

drivers/gpu/drm/drm_atomic_uapi.c

251

plane_state);

drivers/gpu/drm/drm_atomic_uapi.c

255

plane->base.id, plane->name, plane_state);

drivers/gpu/drm/drm_atomic_uapi.c

257

drm_framebuffer_assign(&plane_state->fb, fb);

drivers/gpu/drm/drm_atomic_uapi.c

272

drm_atomic_set_colorop_for_plane(struct drm_plane_state *plane_state,

drivers/gpu/drm/drm_atomic_uapi.c

275

struct drm_plane *plane = plane_state->plane;

drivers/gpu/drm/drm_atomic_uapi.c

278

if (plane_state->color_pipeline == colorop)

drivers/gpu/drm/drm_atomic_uapi.c

285

plane_state);

drivers/gpu/drm/drm_atomic_uapi.c

289

plane->base.id, plane->name, plane_state);

drivers/gpu/drm/drm_atomic_uapi.c

291

plane_state->color_pipeline = colorop;

drivers/gpu/drm/drm_blend.c

486

struct drm_plane_state *plane_state =

drivers/gpu/drm/drm_blend.c

488

if (IS_ERR(plane_state)) {

drivers/gpu/drm/drm_blend.c

489

ret = PTR_ERR(plane_state);

drivers/gpu/drm/drm_blend.c

492

states[n++] = plane_state;

drivers/gpu/drm/drm_blend.c

494

plane->base.id, plane->name, plane_state->zpos);

drivers/gpu/drm/drm_client_modeset.c

1054

struct drm_plane_state *plane_state;

drivers/gpu/drm/drm_client_modeset.c

1056

plane_state = drm_atomic_get_plane_state(state, plane);

drivers/gpu/drm/drm_client_modeset.c

1057

if (IS_ERR(plane_state)) {

drivers/gpu/drm/drm_client_modeset.c

1058

ret = PTR_ERR(plane_state);

drivers/gpu/drm/drm_client_modeset.c

1062

plane_state->rotation = DRM_MODE_ROTATE_0;

drivers/gpu/drm/drm_client_modeset.c

1068

ret = __drm_atomic_helper_disable_plane(plane, plane_state);

drivers/gpu/drm/drm_client_modeset.c

1078

struct drm_plane_state *plane_state;

drivers/gpu/drm/drm_client_modeset.c

1081

plane_state = drm_atomic_get_new_plane_state(state, primary);

drivers/gpu/drm/drm_client_modeset.c

1082

plane_state->rotation = rotation;

drivers/gpu/drm/drm_crtc_internal.h

249

struct drm_plane_state *plane_state);

drivers/gpu/drm/drm_damage_helper.c

162

struct drm_plane_state *plane_state;

drivers/gpu/drm/drm_damage_helper.c

173

plane_state = drm_atomic_get_plane_state(state, plane);

drivers/gpu/drm/drm_damage_helper.c

174

if (IS_ERR(plane_state)) {

drivers/gpu/drm/drm_damage_helper.c

175

ret = PTR_ERR(plane_state);

drivers/gpu/drm/drm_damage_helper.c

179

drm_property_replace_blob(&plane_state->fb_damage_clips,

drivers/gpu/drm/drm_damage_helper.c

70

struct drm_plane_state *plane_state)

drivers/gpu/drm/drm_damage_helper.c

74

if (plane_state->crtc) {

drivers/gpu/drm/drm_damage_helper.c

76

plane_state->crtc);

drivers/gpu/drm/drm_damage_helper.c

82

drm_property_blob_put(plane_state->fb_damage_clips);

drivers/gpu/drm/drm_damage_helper.c

83

plane_state->fb_damage_clips = NULL;

drivers/gpu/drm/drm_fb_helper.c

240

const struct drm_plane_state *plane_state;

drivers/gpu/drm/drm_fb_helper.c

248

plane_state = plane->state;

drivers/gpu/drm/drm_fb_helper.c

250

if (plane_state->fb == helper->fb && plane_state->crtc) {

drivers/gpu/drm/drm_fb_helper.c

251

struct drm_crtc *crtc = plane_state->crtc;

drivers/gpu/drm/drm_framebuffer.c

1028

struct drm_plane_state *plane_state;

drivers/gpu/drm/drm_framebuffer.c

1037

plane_state = drm_atomic_get_plane_state(state, plane);

drivers/gpu/drm/drm_framebuffer.c

1038

if (IS_ERR(plane_state)) {

drivers/gpu/drm/drm_framebuffer.c

1039

ret = PTR_ERR(plane_state);

drivers/gpu/drm/drm_framebuffer.c

1043

if (disable_crtcs && plane_state->crtc->primary == plane) {

drivers/gpu/drm/drm_framebuffer.c

1048

plane_state->crtc->base.id,

drivers/gpu/drm/drm_framebuffer.c

1049

plane_state->crtc->name, fb->base.id);

drivers/gpu/drm/drm_framebuffer.c

1051

crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);

drivers/gpu/drm/drm_framebuffer.c

1053

ret = drm_atomic_add_affected_connectors(state, plane_state->crtc);

drivers/gpu/drm/drm_framebuffer.c

1063

drm_atomic_set_fb_for_plane(plane_state, NULL);

drivers/gpu/drm/drm_framebuffer.c

1064

ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);

drivers/gpu/drm/drm_gem_atomic_helper.c

200

struct drm_plane_state *plane_state = plane->state;

drivers/gpu/drm/drm_gem_atomic_helper.c

202

to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/drm_gem_atomic_helper.c

231

struct drm_plane_state *plane_state = plane->state;

drivers/gpu/drm/drm_gem_atomic_helper.c

234

if (!plane_state)

drivers/gpu/drm/drm_gem_atomic_helper.c

270

struct drm_plane_state *plane_state)

drivers/gpu/drm/drm_gem_atomic_helper.c

273

to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/drm_gem_atomic_helper.c

338

int drm_gem_begin_shadow_fb_access(struct drm_plane *plane, struct drm_plane_state *plane_state)

drivers/gpu/drm/drm_gem_atomic_helper.c

340

struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/drm_gem_atomic_helper.c

341

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/drm_gem_atomic_helper.c

360

void drm_gem_end_shadow_fb_access(struct drm_plane *plane, struct drm_plane_state *plane_state)

drivers/gpu/drm/drm_gem_atomic_helper.c

362

struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/drm_gem_atomic_helper.c

363

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/drm_gem_atomic_helper.c

386

struct drm_plane_state *plane_state)

drivers/gpu/drm/drm_gem_atomic_helper.c

388

return drm_gem_begin_shadow_fb_access(&pipe->plane, plane_state);

drivers/gpu/drm/drm_gem_atomic_helper.c

404

struct drm_plane_state *plane_state)

drivers/gpu/drm/drm_gem_atomic_helper.c

406

drm_gem_end_shadow_fb_access(&pipe->plane, plane_state);

drivers/gpu/drm/drm_gem_atomic_helper.c

452

struct drm_plane_state *plane_state)

drivers/gpu/drm/drm_gem_atomic_helper.c

454

drm_gem_destroy_shadow_plane_state(&pipe->plane, plane_state);

drivers/gpu/drm/drm_mipi_dbi.c

380

struct drm_plane_state *plane_state = plane->state;

drivers/gpu/drm/drm_mipi_dbi.c

381

struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/drm_mipi_dbi.c

382

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/drm_mipi_dbi.c

391

if (drm_atomic_helper_damage_merged(old_plane_state, plane_state, &rect))

drivers/gpu/drm/drm_plane_helper.c

107

struct drm_plane_state plane_state = {

drivers/gpu/drm/drm_plane_helper.c

128

ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state,

drivers/gpu/drm/drm_plane_helper.c

135

*src = plane_state.src;

drivers/gpu/drm/drm_plane_helper.c

136

*dst = plane_state.dst;

drivers/gpu/drm/drm_plane_helper.c

137

*visible = plane_state.visible;

drivers/gpu/drm/drm_simple_kms_helper.c

174

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state,

drivers/gpu/drm/drm_simple_kms_helper.c

184

ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state,

drivers/gpu/drm/drm_simple_kms_helper.c

191

if (!plane_state->visible)

drivers/gpu/drm/drm_simple_kms_helper.c

197

return pipe->funcs->check(pipe, plane_state, crtc_state);

drivers/gpu/drm/hyperv/hyperv_drm_modeset.c

109

struct drm_plane_state *plane_state = plane->state;

drivers/gpu/drm/hyperv/hyperv_drm_modeset.c

116

plane_state->fb->pitches[0]);

drivers/gpu/drm/hyperv/hyperv_drm_modeset.c

141

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/hyperv/hyperv_drm_modeset.c

143

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/hyperv/hyperv_drm_modeset.c

144

struct drm_crtc *crtc = plane_state->crtc;

drivers/gpu/drm/hyperv/hyperv_drm_modeset.c

151

ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state,

drivers/gpu/drm/hyperv/hyperv_drm_modeset.c

158

if (!plane_state->visible)

drivers/gpu/drm/i915/display/i9xx_plane.c

1251

const struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/i9xx_plane.c

1255

if (!plane_state->uapi.visible)

drivers/gpu/drm/i915/display/i9xx_plane.c

1262

if (plane_config->base == plane_state->surf)

drivers/gpu/drm/i915/display/i9xx_plane.c

1266

intel_de_write(display, DSPSURF(display, i9xx_plane), plane_state->surf);

drivers/gpu/drm/i915/display/i9xx_plane.c

1268

intel_de_write(display, DSPADDR(display, i9xx_plane), plane_state->surf);

drivers/gpu/drm/i915/display/i9xx_plane.c

156

static u32 i9xx_plane_ctl(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/i9xx_plane.c

158

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/i9xx_plane.c

159

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/i9xx_plane.c

160

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/i9xx_plane.c

227

int i9xx_check_plane_surface(struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/i9xx_plane.c

229

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/i9xx_plane.c

230

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/i9xx_plane.c

231

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/i9xx_plane.c

236

ret = intel_plane_compute_gtt(plane_state);

drivers/gpu/drm/i915/display/i9xx_plane.c

240

if (!plane_state->uapi.visible)

drivers/gpu/drm/i915/display/i9xx_plane.c

243

src_w = drm_rect_width(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/i9xx_plane.c

244

src_x = plane_state->uapi.src.x1 >> 16;

drivers/gpu/drm/i915/display/i9xx_plane.c

245

src_y = plane_state->uapi.src.y1 >> 16;

drivers/gpu/drm/i915/display/i9xx_plane.c

255

intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);

drivers/gpu/drm/i915/display/i9xx_plane.c

259

plane_state, 0);

drivers/gpu/drm/i915/display/i9xx_plane.c

278

while ((src_x + src_w) * cpp > plane_state->view.color_plane[0].mapping_stride) {

drivers/gpu/drm/i915/display/i9xx_plane.c

286

offset = intel_plane_adjust_aligned_offset(&src_x, &src_y, plane_state, 0,

drivers/gpu/drm/i915/display/i9xx_plane.c

295

drm_rect_translate_to(&plane_state->uapi.src,

drivers/gpu/drm/i915/display/i9xx_plane.c

300

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/i9xx_plane.c

301

int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/i9xx_plane.c

302

int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/i9xx_plane.c

319

plane_state->view.color_plane[0].offset = offset;

drivers/gpu/drm/i915/display/i9xx_plane.c

320

plane_state->view.color_plane[0].x = src_x;

drivers/gpu/drm/i915/display/i9xx_plane.c

321

plane_state->view.color_plane[0].y = src_y;

drivers/gpu/drm/i915/display/i9xx_plane.c

328

struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/i9xx_plane.c

330

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/i9xx_plane.c

333

ret = chv_plane_check_rotation(plane_state);

drivers/gpu/drm/i915/display/i9xx_plane.c

337

ret = intel_plane_check_clipping(plane_state, crtc_state,

drivers/gpu/drm/i915/display/i9xx_plane.c

344

ret = i9xx_check_plane_surface(plane_state);

drivers/gpu/drm/i915/display/i9xx_plane.c

348

if (!plane_state->uapi.visible)

drivers/gpu/drm/i915/display/i9xx_plane.c

351

ret = intel_plane_check_src_coordinates(plane_state);

drivers/gpu/drm/i915/display/i9xx_plane.c

355

plane_state->ctl = i9xx_plane_ctl(plane_state);

drivers/gpu/drm/i915/display/i9xx_plane.c

360

static u32 i8xx_plane_surf_offset(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/i9xx_plane.c

362

int x = plane_state->view.color_plane[0].x;

drivers/gpu/drm/i915/display/i9xx_plane.c

363

int y = plane_state->view.color_plane[0].y;

drivers/gpu/drm/i915/display/i9xx_plane.c

365

return intel_fb_xy_to_linear(x, y, plane_state, 0);

drivers/gpu/drm/i915/display/i9xx_plane.c

368

u32 i965_plane_surf_offset(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/i9xx_plane.c

370

return plane_state->view.color_plane[0].offset;

drivers/gpu/drm/i915/display/i9xx_plane.c

392

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/i9xx_plane.c

395

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/i9xx_plane.c

415

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/i9xx_plane.c

429

i9xx_plane_ratio(crtc_state, plane_state, &num, &den);

drivers/gpu/drm/i915/display/i9xx_plane.c

441

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/i9xx_plane.c

447

plane_state->view.color_plane[0].mapping_stride);

drivers/gpu/drm/i915/display/i9xx_plane.c

450

int crtc_x = plane_state->uapi.dst.x1;

drivers/gpu/drm/i915/display/i9xx_plane.c

451

int crtc_y = plane_state->uapi.dst.y1;

drivers/gpu/drm/i915/display/i9xx_plane.c

452

int crtc_w = drm_rect_width(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/i9xx_plane.c

453

int crtc_h = drm_rect_height(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/i9xx_plane.c

470

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/i9xx_plane.c

474

int x = plane_state->view.color_plane[0].x;

drivers/gpu/drm/i915/display/i9xx_plane.c

475

int y = plane_state->view.color_plane[0].y;

drivers/gpu/drm/i915/display/i9xx_plane.c

478

dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);

drivers/gpu/drm/i915/display/i9xx_plane.c

486

int crtc_x = plane_state->uapi.dst.x1;

drivers/gpu/drm/i915/display/i9xx_plane.c

487

int crtc_y = plane_state->uapi.dst.y1;

drivers/gpu/drm/i915/display/i9xx_plane.c

488

int crtc_w = drm_rect_width(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/i9xx_plane.c

489

int crtc_h = drm_rect_height(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/i9xx_plane.c

504

intel_fb_xy_to_linear(x, y, plane_state, 0));

drivers/gpu/drm/i915/display/i9xx_plane.c

517

intel_de_write_fw(display, DSPSURF(display, i9xx_plane), plane_state->surf);

drivers/gpu/drm/i915/display/i9xx_plane.c

519

intel_de_write_fw(display, DSPADDR(display, i9xx_plane), plane_state->surf);

drivers/gpu/drm/i915/display/i9xx_plane.c

525

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/i9xx_plane.c

533

i9xx_plane_update_noarm(dsb, plane, crtc_state, plane_state);

drivers/gpu/drm/i915/display/i9xx_plane.c

534

i9xx_plane_update_arm(dsb, plane, crtc_state, plane_state);

drivers/gpu/drm/i915/display/i9xx_plane.c

603

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/i9xx_plane.c

607

u32 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);

drivers/gpu/drm/i915/display/i9xx_plane.c

614

intel_de_write_fw(display, DSPSURF(display, i9xx_plane), plane_state->surf);

drivers/gpu/drm/i915/display/i9xx_plane.c

621

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/i9xx_plane.c

627

intel_de_write_fw(display, DSPADDR_VLV(display, i9xx_plane), plane_state->surf);

drivers/gpu/drm/i915/display/i9xx_plane.h

27

int i9xx_check_plane_surface(struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/i9xx_plane.h

28

u32 i965_plane_surf_offset(const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/i9xx_plane.h

44

static inline int i9xx_check_plane_surface(struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/i9xx_wm.c

1000

width = drm_rect_width(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/i9xx_wm.c

1060

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/i9xx_wm.c

1064

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/i9xx_wm.c

1067

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/i9xx_wm.c

1072

if (!intel_wm_plane_visible(crtc_state, plane_state)) {

drivers/gpu/drm/i915/display/i9xx_wm.c

1083

wm = g4x_compute_wm(crtc_state, plane_state, level);

drivers/gpu/drm/i915/display/i9xx_wm.c

1096

wm = ilk_compute_fbc_wm(crtc_state, plane_state,

drivers/gpu/drm/i915/display/i9xx_wm.c

1512

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/i9xx_wm.c

1515

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/i9xx_wm.c

1516

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/i9xx_wm.c

1524

if (!intel_wm_plane_visible(crtc_state, plane_state))

drivers/gpu/drm/i915/display/i9xx_wm.c

1527

cpp = plane_state->hw.fb->format->cpp[0];

drivers/gpu/drm/i915/display/i9xx_wm.c

1530

width = drm_rect_width(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/i9xx_wm.c

1683

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/i9xx_wm.c

1686

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/i9xx_wm.c

1691

if (!intel_wm_plane_visible(crtc_state, plane_state)) {

drivers/gpu/drm/i915/display/i9xx_wm.c

1698

int wm = vlv_compute_wm_level(crtc_state, plane_state, level);

drivers/gpu/drm/i915/display/i9xx_wm.c

2447

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/i9xx_wm.c

2456

if (!intel_wm_plane_visible(crtc_state, plane_state))

drivers/gpu/drm/i915/display/i9xx_wm.c

2459

cpp = plane_state->hw.fb->format->cpp[0];

drivers/gpu/drm/i915/display/i9xx_wm.c

2468

drm_rect_width(&plane_state->uapi.src) >> 16,

drivers/gpu/drm/i915/display/i9xx_wm.c

2479

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/i9xx_wm.c

2488

if (!intel_wm_plane_visible(crtc_state, plane_state))

drivers/gpu/drm/i915/display/i9xx_wm.c

2491

cpp = plane_state->hw.fb->format->cpp[0];

drivers/gpu/drm/i915/display/i9xx_wm.c

2496

drm_rect_width(&plane_state->uapi.src) >> 16,

drivers/gpu/drm/i915/display/i9xx_wm.c

2506

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/i9xx_wm.c

2514

if (!intel_wm_plane_visible(crtc_state, plane_state))

drivers/gpu/drm/i915/display/i9xx_wm.c

2517

cpp = plane_state->hw.fb->format->cpp[0];

drivers/gpu/drm/i915/display/i9xx_wm.c

2521

drm_rect_width(&plane_state->uapi.src) >> 16,

drivers/gpu/drm/i915/display/i9xx_wm.c

2527

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/i9xx_wm.c

2532

if (!intel_wm_plane_visible(crtc_state, plane_state))

drivers/gpu/drm/i915/display/i9xx_wm.c

2535

cpp = plane_state->hw.fb->format->cpp[0];

drivers/gpu/drm/i915/display/i9xx_wm.c

2537

return ilk_wm_fbc(pri_val, drm_rect_width(&plane_state->uapi.src) >> 16,

drivers/gpu/drm/i915/display/i9xx_wm.c

2926

const struct intel_plane_state *plane_state;

drivers/gpu/drm/i915/display/i9xx_wm.c

2935

intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {

drivers/gpu/drm/i915/display/i9xx_wm.c

2937

pristate = plane_state;

drivers/gpu/drm/i915/display/i9xx_wm.c

2939

sprstate = plane_state;

drivers/gpu/drm/i915/display/i9xx_wm.c

2941

curstate = plane_state;

drivers/gpu/drm/i915/display/i9xx_wm.c

3557

struct drm_plane_state *plane_state;

drivers/gpu/drm/i915/display/i9xx_wm.c

3559

plane_state = drm_atomic_get_plane_state(state, plane);

drivers/gpu/drm/i915/display/i9xx_wm.c

3560

if (IS_ERR(plane_state))

drivers/gpu/drm/i915/display/i9xx_wm.c

3561

return PTR_ERR(plane_state);

drivers/gpu/drm/i915/display/i9xx_wm.c

3868

struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/i9xx_wm.c

3873

if (plane_state->uapi.visible)

drivers/gpu/drm/i915/display/i9xx_wm.c

4020

struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/i9xx_wm.c

4025

if (plane_state->uapi.visible)

drivers/gpu/drm/i915/display/i9xx_wm.c

969

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/i9xx_wm.c

972

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/i9xx_wm.c

973

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/i9xx_wm.c

982

if (!intel_wm_plane_visible(crtc_state, plane_state))

drivers/gpu/drm/i915/display/i9xx_wm.c

985

cpp = plane_state->hw.fb->format->cpp[0];

drivers/gpu/drm/i915/display/intel_color.c

2198

struct intel_plane_state *plane_state;

drivers/gpu/drm/i915/display/intel_color.c

2203

plane_state = intel_atomic_get_plane_state(state, plane);

drivers/gpu/drm/i915/display/intel_color.c

2204

if (IS_ERR(plane_state))

drivers/gpu/drm/i915/display/intel_color.c

2205

return PTR_ERR(plane_state);

drivers/gpu/drm/i915/display/intel_color.c

3868

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_color.c

3870

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_color.c

3871

const struct drm_plane_state *state = &plane_state->uapi;

drivers/gpu/drm/i915/display/intel_color.c

3874

const struct drm_property_blob *blob = plane_state->hw.ctm;

drivers/gpu/drm/i915/display/intel_color.c

3963

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_color.c

3965

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_color.c

3966

const struct drm_plane_state *state = &plane_state->uapi;

drivers/gpu/drm/i915/display/intel_color.c

3969

const struct drm_color_lut32 *pre_csc_lut = plane_state->hw.degamma_lut->data;

drivers/gpu/drm/i915/display/intel_color.c

4016

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_color.c

4018

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_color.c

4019

const struct drm_plane_state *state = &plane_state->uapi;

drivers/gpu/drm/i915/display/intel_color.c

4022

const struct drm_color_lut32 *post_csc_lut = plane_state->hw.gamma_lut->data;

drivers/gpu/drm/i915/display/intel_color.c

4071

xelpd_plane_load_luts(struct intel_dsb *dsb, const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_color.c

4073

if (plane_state->hw.degamma_lut)

drivers/gpu/drm/i915/display/intel_color.c

4074

xelpd_program_plane_pre_csc_lut(dsb, plane_state);

drivers/gpu/drm/i915/display/intel_color.c

4076

if (plane_state->hw.gamma_lut)

drivers/gpu/drm/i915/display/intel_color.c

4077

xelpd_program_plane_post_csc_lut(dsb, plane_state);

drivers/gpu/drm/i915/display/intel_color.c

4256

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_color.c

4258

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_color.c

4259

struct intel_crtc *crtc = to_intel_crtc(plane_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

4262

glk_lut_3d_commit(dsb, crtc, !!plane_state->hw.lut_3d);

drivers/gpu/drm/i915/display/intel_color.c

4267

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_color.c

4269

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_color.c

4272

display->color.funcs->load_plane_csc_matrix(dsb, plane_state);

drivers/gpu/drm/i915/display/intel_color.c

4277

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_color.c

4279

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_color.c

4282

display->color.funcs->load_plane_luts(dsb, plane_state);

drivers/gpu/drm/i915/display/intel_color.c

4296

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_color.c

4298

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_color.c

4299

struct intel_crtc *crtc = to_intel_crtc(plane_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_color.c

4302

glk_load_lut_3d(dsb, crtc, plane_state->hw.lut_3d);

drivers/gpu/drm/i915/display/intel_color.c

4306

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_color.c

4308

if (plane_state->hw.ctm)

drivers/gpu/drm/i915/display/intel_color.c

4309

intel_color_load_plane_csc_matrix(dsb, plane_state);

drivers/gpu/drm/i915/display/intel_color.c

4310

if (plane_state->hw.degamma_lut || plane_state->hw.gamma_lut)

drivers/gpu/drm/i915/display/intel_color.c

4311

intel_color_load_plane_luts(dsb, plane_state);

drivers/gpu/drm/i915/display/intel_color.c

4312

if (plane_state->hw.lut_3d)

drivers/gpu/drm/i915/display/intel_color.c

4313

intel_color_load_3dlut(dsb, plane_state);

drivers/gpu/drm/i915/display/intel_color.c

95

const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_color.c

99

const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_color.h

46

const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_color.h

48

const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

115

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

117

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

118

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

123

str_yes_no(plane_state->uapi.visible));

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

130

fb->modifier, str_yes_no(plane_state->uapi.visible));

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

132

plane_state->hw.rotation, plane_state->scaler_id, plane_state->hw.scaling_filter);

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

133

if (plane_state->uapi.visible)

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

135

DRM_RECT_FP_ARG(&plane_state->uapi.src),

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

136

DRM_RECT_ARG(&plane_state->uapi.dst));

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

182

const struct intel_plane_state *plane_state;

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

396

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

398

intel_dump_plane_state(&p, plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

100

src_x = plane_state->uapi.src.x1 >> 16;

drivers/gpu/drm/i915/display/intel_cursor.c

101

src_y = plane_state->uapi.src.y1 >> 16;

drivers/gpu/drm/i915/display/intel_cursor.c

103

intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);

drivers/gpu/drm/i915/display/intel_cursor.c

105

plane_state, 0);

drivers/gpu/drm/i915/display/intel_cursor.c

118

drm_rect_translate_to(&plane_state->uapi.src,

drivers/gpu/drm/i915/display/intel_cursor.c

123

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_cursor.c

124

int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/intel_cursor.c

125

int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/intel_cursor.c

130

plane_state->view.color_plane[0].offset = offset;

drivers/gpu/drm/i915/display/intel_cursor.c

131

plane_state->view.color_plane[0].x = src_x;

drivers/gpu/drm/i915/display/intel_cursor.c

132

plane_state->view.color_plane[0].y = src_y;

drivers/gpu/drm/i915/display/intel_cursor.c

138

struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_cursor.c

140

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

141

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_cursor.c

142

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_cursor.c

143

const struct drm_rect src = plane_state->uapi.src;

drivers/gpu/drm/i915/display/intel_cursor.c

144

const struct drm_rect dst = plane_state->uapi.dst;

drivers/gpu/drm/i915/display/intel_cursor.c

153

ret = intel_plane_check_clipping(plane_state, crtc_state,

drivers/gpu/drm/i915/display/intel_cursor.c

161

plane_state->uapi.src = src;

drivers/gpu/drm/i915/display/intel_cursor.c

162

plane_state->uapi.dst = dst;

drivers/gpu/drm/i915/display/intel_cursor.c

165

drm_rect_translate(&plane_state->uapi.dst,

drivers/gpu/drm/i915/display/intel_cursor.c

169

ret = intel_cursor_check_surface(plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

173

if (!plane_state->uapi.visible)

drivers/gpu/drm/i915/display/intel_cursor.c

176

ret = intel_plane_check_src_coordinates(plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

208

static u32 i845_cursor_ctl(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_cursor.c

212

CURSOR_STRIDE(plane_state->view.color_plane[0].mapping_stride);

drivers/gpu/drm/i915/display/intel_cursor.c

215

static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_cursor.c

217

int width = drm_rect_width(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/intel_cursor.c

223

return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);

drivers/gpu/drm/i915/display/intel_cursor.c

227

struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_cursor.c

229

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

230

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_cursor.c

231

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_cursor.c

234

ret = intel_check_cursor(crtc_state, plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

243

if (!i845_cursor_size_ok(plane_state)) {

drivers/gpu/drm/i915/display/intel_cursor.c

247

drm_rect_width(&plane_state->uapi.dst),

drivers/gpu/drm/i915/display/intel_cursor.c

248

drm_rect_height(&plane_state->uapi.dst));

drivers/gpu/drm/i915/display/intel_cursor.c

252

drm_WARN_ON(display->drm, plane_state->uapi.visible &&

drivers/gpu/drm/i915/display/intel_cursor.c

253

plane_state->view.color_plane[0].mapping_stride != fb->pitches[0]);

drivers/gpu/drm/i915/display/intel_cursor.c

268

plane_state->ctl = i845_cursor_ctl(plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

277

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_cursor.c

282

if (plane_state && plane_state->uapi.visible) {

drivers/gpu/drm/i915/display/intel_cursor.c

283

unsigned int width = drm_rect_width(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/intel_cursor.c

284

unsigned int height = drm_rect_height(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/intel_cursor.c

286

cntl = plane_state->ctl |

drivers/gpu/drm/i915/display/intel_cursor.c

291

base = plane_state->surf;

drivers/gpu/drm/i915/display/intel_cursor.c

292

pos = intel_cursor_position(crtc_state, plane_state, false);

drivers/gpu/drm/i915/display/intel_cursor.c

36

static u32 intel_cursor_surf_offset(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_cursor.c

38

return plane_state->view.color_plane[0].offset;

drivers/gpu/drm/i915/display/intel_cursor.c

400

static u32 i9xx_cursor_ctl(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_cursor.c

402

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

408

switch (drm_rect_width(&plane_state->uapi.dst)) {

drivers/gpu/drm/i915/display/intel_cursor.c

419

MISSING_CASE(drm_rect_width(&plane_state->uapi.dst));

drivers/gpu/drm/i915/display/intel_cursor.c

42

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_cursor.c

423

if (plane_state->hw.rotation & DRM_MODE_ROTATE_180)

drivers/gpu/drm/i915/display/intel_cursor.c

433

static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_cursor.c

435

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

436

int width = drm_rect_width(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/intel_cursor.c

437

int height = drm_rect_height(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/intel_cursor.c

439

if (!intel_cursor_size_ok(plane_state))

drivers/gpu/drm/i915/display/intel_cursor.c

45

int x = plane_state->uapi.dst.x1;

drivers/gpu/drm/i915/display/intel_cursor.c

459

plane_state->hw.rotation & DRM_MODE_ROTATE_0) {

drivers/gpu/drm/i915/display/intel_cursor.c

46

int y = plane_state->uapi.dst.y1;

drivers/gpu/drm/i915/display/intel_cursor.c

471

struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_cursor.c

473

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

474

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_cursor.c

475

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_cursor.c

479

ret = intel_check_cursor(crtc_state, plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

488

if (!i9xx_cursor_size_ok(plane_state)) {

drivers/gpu/drm/i915/display/intel_cursor.c

492

drm_rect_width(&plane_state->uapi.dst),

drivers/gpu/drm/i915/display/intel_cursor.c

493

drm_rect_height(&plane_state->uapi.dst));

drivers/gpu/drm/i915/display/intel_cursor.c

497

drm_WARN_ON(display->drm, plane_state->uapi.visible &&

drivers/gpu/drm/i915/display/intel_cursor.c

498

plane_state->view.color_plane[0].mapping_stride != fb->pitches[0]);

drivers/gpu/drm/i915/display/intel_cursor.c

501

drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) {

drivers/gpu/drm/i915/display/intel_cursor.c

505

fb->pitches[0], drm_rect_width(&plane_state->uapi.dst));

drivers/gpu/drm/i915/display/intel_cursor.c

520

plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) {

drivers/gpu/drm/i915/display/intel_cursor.c

527

plane_state->ctl = i9xx_cursor_ctl(plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

548

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_cursor.c

55

y = max(-1 * drm_rect_height(&plane_state->uapi.dst) + 1,

drivers/gpu/drm/i915/display/intel_cursor.c

551

u32 ctl = plane_state->ctl;

drivers/gpu/drm/i915/display/intel_cursor.c

567

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_cursor.c

575

if (drm_rect_height(&plane_state->psr2_sel_fetch_area) > 0) {

drivers/gpu/drm/i915/display/intel_cursor.c

577

u32 val = intel_cursor_position(crtc_state, plane_state,

drivers/gpu/drm/i915/display/intel_cursor.c

583

intel_de_write_dsb(display, dsb, SEL_FETCH_CUR_CTL(pipe), plane_state->ctl);

drivers/gpu/drm/i915/display/intel_cursor.c

587

wa_16021440873(dsb, plane, crtc_state, plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

652

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_cursor.c

658

if (plane_state && plane_state->uapi.visible) {

drivers/gpu/drm/i915/display/intel_cursor.c

659

int width = drm_rect_width(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/intel_cursor.c

660

int height = drm_rect_height(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/intel_cursor.c

662

cntl = plane_state->ctl |

drivers/gpu/drm/i915/display/intel_cursor.c

668

base = plane_state->surf;

drivers/gpu/drm/i915/display/intel_cursor.c

669

pos = intel_cursor_position(crtc_state, plane_state, false);

drivers/gpu/drm/i915/display/intel_cursor.c

695

if (plane_state)

drivers/gpu/drm/i915/display/intel_cursor.c

696

i9xx_cursor_update_sel_fetch_arm(dsb, plane, crtc_state, plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

73

static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_cursor.c

76

&plane_state->uapi.plane->dev->mode_config;

drivers/gpu/drm/i915/display/intel_cursor.c

77

int width = drm_rect_width(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/intel_cursor.c

78

int height = drm_rect_height(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/intel_cursor.c

791

struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/intel_cursor.c

792

container_of(work, typeof(*plane_state), unpin_work);

drivers/gpu/drm/i915/display/intel_cursor.c

793

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_cursor.c

795

intel_plane_unpin_fb(plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

796

intel_plane_destroy_state(&plane->base, &plane_state->uapi);

drivers/gpu/drm/i915/display/intel_cursor.c

84

static int intel_cursor_check_surface(struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_cursor.c

86

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

87

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_cursor.c

88

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/intel_cursor.c

93

ret = intel_plane_compute_gtt(plane_state);

drivers/gpu/drm/i915/display/intel_cursor.c

97

if (!plane_state->uapi.visible)

drivers/gpu/drm/i915/display/intel_display.c

1109

const struct intel_plane_state __maybe_unused *plane_state;

drivers/gpu/drm/i915/display/intel_display.c

1113

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

drivers/gpu/drm/i915/display/intel_display.c

1126

const struct intel_plane_state __maybe_unused *plane_state;

drivers/gpu/drm/i915/display/intel_display.c

1130

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

drivers/gpu/drm/i915/display/intel_display.c

5528

const struct intel_plane_state *plane_state;

drivers/gpu/drm/i915/display/intel_display.c

5532

plane_state, i)

drivers/gpu/drm/i915/display/intel_display.c

5533

assert_plane(plane, plane_state->is_y_plane ||

drivers/gpu/drm/i915/display/intel_display.c

5534

plane_state->uapi.visible);

drivers/gpu/drm/i915/display/intel_display.c

582

struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_display.c

585

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_display.c

587

plane_state->uapi.visible = visible;

drivers/gpu/drm/i915/display/intel_display.c

621

struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/intel_display.c

6234

const struct intel_plane_state *plane_state;

drivers/gpu/drm/i915/display/intel_display.c

6247

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

drivers/gpu/drm/i915/display/intel_display.c

6248

crtc = to_intel_crtc(plane_state->hw.crtc);

drivers/gpu/drm/i915/display/intel_display.c

629

intel_plane_set_invisible(crtc_state, plane_state);

drivers/gpu/drm/i915/display/intel_display.c

630

intel_set_plane_visible(crtc_state, plane_state, false);

drivers/gpu/drm/i915/display/intel_display.c

666

intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_display.c

670

intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,

drivers/gpu/drm/i915/display/intel_display.c

671

plane_state->view.color_plane[0].offset, 0);

drivers/gpu/drm/i915/display/intel_display.c

7213

struct intel_plane_state *plane_state;

drivers/gpu/drm/i915/display/intel_display.c

7216

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

drivers/gpu/drm/i915/display/intel_display.c

7217

struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_display.c

7245

&plane_state->ccval,

drivers/gpu/drm/i915/display/intel_display.c

7246

sizeof(plane_state->ccval));

drivers/gpu/drm/i915/display/intel_display.h

313

plane, plane_state, \

drivers/gpu/drm/i915/display/intel_display.h

317

for_each_if ((plane_state = \

drivers/gpu/drm/i915/display/intel_display.h

454

unsigned int intel_plane_fence_y_offset(const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_display.h

462

struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_display_debugfs.c

332

static const char *plane_visibility(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_display_debugfs.c

334

if (plane_state->uapi.visible)

drivers/gpu/drm/i915/display/intel_display_debugfs.c

337

if (plane_state->is_y_plane)

drivers/gpu/drm/i915/display/intel_display_debugfs.c

345

const struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/intel_display_debugfs.c

347

const struct drm_framebuffer *fb = plane_state->uapi.fb;

drivers/gpu/drm/i915/display/intel_display_debugfs.c

351

src = drm_plane_state_src(&plane_state->uapi);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

352

dst = drm_plane_state_dest(&plane_state->uapi);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

355

plane_state->uapi.rotation);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

365

", rotation=%s\n", plane_visibility(plane_state),

drivers/gpu/drm/i915/display/intel_display_debugfs.c

368

if (plane_state->planar_linked_plane)

drivers/gpu/drm/i915/display/intel_display_debugfs.c

370

plane_state->planar_linked_plane->base.base.id, plane_state->planar_linked_plane->base.name,

drivers/gpu/drm/i915/display/intel_display_debugfs.c

371

plane_state->is_y_plane ? "Y plane" : "UV plane");

drivers/gpu/drm/i915/display/intel_display_debugfs.c

376

const struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/intel_display_debugfs.c

378

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_display_debugfs.c

385

plane_state->hw.rotation);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

391

str_yes_no(plane_state->uapi.visible),

drivers/gpu/drm/i915/display/intel_display_debugfs.c

392

DRM_RECT_FP_ARG(&plane_state->uapi.src),

drivers/gpu/drm/i915/display/intel_display_debugfs.c

393

DRM_RECT_ARG(&plane_state->uapi.dst),

drivers/gpu/drm/i915/display/intel_display_trace.h

411

TP_PROTO(const struct intel_plane_state *plane_state, struct intel_crtc *crtc),

drivers/gpu/drm/i915/display/intel_display_trace.h

412

TP_ARGS(plane_state, crtc),

drivers/gpu/drm/i915/display/intel_display_trace.h

415

__string(dev, __dev_name_drm(plane_state->uapi.plane))

drivers/gpu/drm/i915/display/intel_display_trace.h

422

__string(name, plane_state->uapi.plane->name)

drivers/gpu/drm/i915/display/intel_display_trace.h

431

__entry->format = plane_state->hw.fb->format->format;

drivers/gpu/drm/i915/display/intel_display_trace.h

432

memcpy(__entry->src, &plane_state->uapi.src, sizeof(__entry->src));

drivers/gpu/drm/i915/display/intel_display_trace.h

433

memcpy(__entry->dst, &plane_state->uapi.dst, sizeof(__entry->dst));

drivers/gpu/drm/i915/display/intel_display_trace.h

444

TP_PROTO(const struct intel_plane_state *plane_state, struct intel_crtc *crtc),

drivers/gpu/drm/i915/display/intel_display_trace.h

445

TP_ARGS(plane_state, crtc),

drivers/gpu/drm/i915/display/intel_display_trace.h

448

__string(dev, __dev_name_drm(plane_state->uapi.plane))

drivers/gpu/drm/i915/display/intel_display_trace.h

455

__string(name, plane_state->uapi.plane->name)

drivers/gpu/drm/i915/display/intel_display_trace.h

464

__entry->format = plane_state->hw.fb->format->format;

drivers/gpu/drm/i915/display/intel_display_trace.h

465

memcpy(__entry->src, &plane_state->uapi.src, sizeof(__entry->src));

drivers/gpu/drm/i915/display/intel_display_trace.h

466

memcpy(__entry->dst, &plane_state->uapi.dst, sizeof(__entry->dst));

drivers/gpu/drm/i915/display/intel_display_types.h

1623

const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_display_types.h

1628

const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_display_types.h

1638

struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_display_types.h

1639

u32 (*surf_offset)(const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_display_types.h

1641

const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_display_types.h

1645

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_display_types.h

1661

#define to_intel_plane_state(plane_state) \

drivers/gpu/drm/i915/display/intel_display_types.h

1662

container_of_const((plane_state), struct intel_plane_state, uapi)

drivers/gpu/drm/i915/display/intel_fb.c

1047

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_fb.c

1051

return intel_adjust_aligned_offset(x, y, plane_state->hw.fb, color_plane,

drivers/gpu/drm/i915/display/intel_fb.c

1052

plane_state->hw.rotation,

drivers/gpu/drm/i915/display/intel_fb.c

1053

plane_state->view.color_plane[color_plane].mapping_stride,

drivers/gpu/drm/i915/display/intel_fb.c

1127

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_fb.c

1130

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fb.c

1131

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_fb.c

1132

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_fb.c

1133

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/intel_fb.c

1134

unsigned int pitch = plane_state->view.color_plane[color_plane].mapping_stride;

drivers/gpu/drm/i915/display/intel_fb.c

1233

static bool intel_plane_can_remap(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fb.c

1235

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fb.c

1236

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_fb.c

1237

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_fb.c

1285

bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fb.c

1287

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fb.c

1288

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_fb.c

1291

(plane->fbc && !plane_state->no_fbc_reason &&

drivers/gpu/drm/i915/display/intel_fb.c

1292

i915_gtt_view_is_normal(&plane_state->view.gtt));

drivers/gpu/drm/i915/display/intel_fb.c

1305

static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fb.c

1307

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_fb.c

1308

const struct intel_framebuffer *fb = to_intel_framebuffer(plane_state->hw.fb);

drivers/gpu/drm/i915/display/intel_fb.c

1309

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/intel_fb.c

1316

if (!plane_state->uapi.visible)

drivers/gpu/drm/i915/display/intel_fb.c

1319

if (!intel_plane_can_remap(plane_state))

drivers/gpu/drm/i915/display/intel_fb.c

1835

static void intel_plane_remap_gtt(struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fb.c

1837

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fb.c

1838

struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_fb.c

1840

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/intel_fb.c

1846

intel_fb_view_init(display, &plane_state->view,

drivers/gpu/drm/i915/display/intel_fb.c

1851

src_x = plane_state->uapi.src.x1 >> 16;

drivers/gpu/drm/i915/display/intel_fb.c

1852

src_y = plane_state->uapi.src.y1 >> 16;

drivers/gpu/drm/i915/display/intel_fb.c

1853

src_w = drm_rect_width(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/intel_fb.c

1854

src_h = drm_rect_height(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/intel_fb.c

1859

drm_rect_translate(&plane_state->uapi.src,

drivers/gpu/drm/i915/display/intel_fb.c

1864

drm_rect_rotate(&plane_state->uapi.src,

drivers/gpu/drm/i915/display/intel_fb.c

1894

&plane_state->view);

drivers/gpu/drm/i915/display/intel_fb.c

1952

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_fb.c

1955

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_fb.c

1957

unsigned int pitch = plane_state->view.color_plane[color_plane].mapping_stride;

drivers/gpu/drm/i915/display/intel_fb.c

1968

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_fb.c

1972

*x += plane_state->view.color_plane[color_plane].x;

drivers/gpu/drm/i915/display/intel_fb.c

1973

*y += plane_state->view.color_plane[color_plane].y;

drivers/gpu/drm/i915/display/intel_fb.c

2042

static int intel_plane_check_stride(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fb.c

2044

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fb.c

2045

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_fb.c

2046

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_fb.c

2047

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/intel_fb.c

2056

if (intel_plane_can_remap(plane_state) &&

drivers/gpu/drm/i915/display/intel_fb.c

2057

!plane_state->uapi.visible)

drivers/gpu/drm/i915/display/intel_fb.c

2061

stride = plane_state->view.color_plane[0].mapping_stride;

drivers/gpu/drm/i915/display/intel_fb.c

2076

int intel_plane_compute_gtt(struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fb.c

2079

to_intel_framebuffer(plane_state->hw.fb);

drivers/gpu/drm/i915/display/intel_fb.c

2080

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/intel_fb.c

2085

if (intel_plane_needs_remap(plane_state)) {

drivers/gpu/drm/i915/display/intel_fb.c

2086

intel_plane_remap_gtt(plane_state);

drivers/gpu/drm/i915/display/intel_fb.c

2094

return intel_plane_check_stride(plane_state);

drivers/gpu/drm/i915/display/intel_fb.c

2097

intel_fb_fill_view(fb, rotation, &plane_state->view);

drivers/gpu/drm/i915/display/intel_fb.c

2101

drm_rect_rotate(&plane_state->uapi.src,

drivers/gpu/drm/i915/display/intel_fb.c

2105

return intel_plane_check_stride(plane_state);

drivers/gpu/drm/i915/display/intel_fb.h

74

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_fb.h

78

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_fb.h

81

bool intel_plane_uses_fence(const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_fb.h

93

int intel_plane_compute_gtt(struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_fb.h

96

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_fb.h

99

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_fbc.c

1070

static bool i8xx_fbc_stride_is_valid(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1072

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_fbc.c

1073

unsigned int stride = intel_fbc_plane_stride(plane_state) *

drivers/gpu/drm/i915/display/intel_fbc.c

1079

static bool i965_fbc_stride_is_valid(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1081

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_fbc.c

1082

unsigned int stride = intel_fbc_plane_stride(plane_state) *

drivers/gpu/drm/i915/display/intel_fbc.c

1088

static bool g4x_fbc_stride_is_valid(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1093

static bool skl_fbc_stride_is_valid(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1095

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_fbc.c

1096

unsigned int stride = intel_fbc_plane_stride(plane_state) *

drivers/gpu/drm/i915/display/intel_fbc.c

1106

static bool icl_fbc_stride_is_valid(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1111

static bool stride_is_valid(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1113

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1116

return icl_fbc_stride_is_valid(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1118

return skl_fbc_stride_is_valid(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1120

return g4x_fbc_stride_is_valid(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1122

return i965_fbc_stride_is_valid(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1124

return i8xx_fbc_stride_is_valid(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1127

static bool i8xx_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1129

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1130

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_fbc.c

1147

static bool g4x_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1149

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1150

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_fbc.c

1166

static bool lnl_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1168

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_fbc.c

1183

xe3p_lpd_fbc_fp16_format_is_valid(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1185

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_fbc.c

1196

static bool xe3p_lpd_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1198

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_fbc.c

1200

if (lnl_fbc_pixel_format_is_valid(plane_state))

drivers/gpu/drm/i915/display/intel_fbc.c

1203

if (xe3p_lpd_fbc_fp16_format_is_valid(plane_state))

drivers/gpu/drm/i915/display/intel_fbc.c

1217

bool intel_fbc_need_pixel_normalizer(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1219

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1222

xe3p_lpd_fbc_fp16_format_is_valid(plane_state))

drivers/gpu/drm/i915/display/intel_fbc.c

1228

static bool pixel_format_is_valid(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1230

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1233

return xe3p_lpd_fbc_pixel_format_is_valid(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1235

return lnl_fbc_pixel_format_is_valid(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1237

return g4x_fbc_pixel_format_is_valid(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1239

return i8xx_fbc_pixel_format_is_valid(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1242

static bool i8xx_fbc_rotation_is_valid(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1244

return plane_state->hw.rotation == DRM_MODE_ROTATE_0;

drivers/gpu/drm/i915/display/intel_fbc.c

1247

static bool g4x_fbc_rotation_is_valid(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1252

static bool skl_fbc_rotation_is_valid(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1254

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_fbc.c

1255

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/intel_fbc.c

1264

static bool rotation_is_valid(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1266

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1269

return skl_fbc_rotation_is_valid(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1271

return g4x_fbc_rotation_is_valid(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1273

return i8xx_fbc_rotation_is_valid(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1303

static bool intel_fbc_surface_size_ok(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1305

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1310

effective_w = plane_state->view.color_plane[0].x +

drivers/gpu/drm/i915/display/intel_fbc.c

1311

(drm_rect_width(&plane_state->uapi.src) >> 16);

drivers/gpu/drm/i915/display/intel_fbc.c

1312

effective_h = plane_state->view.color_plane[0].y +

drivers/gpu/drm/i915/display/intel_fbc.c

1313

(drm_rect_height(&plane_state->uapi.src) >> 16);

drivers/gpu/drm/i915/display/intel_fbc.c

1336

static bool intel_fbc_plane_size_valid(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1338

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1343

w = drm_rect_width(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/intel_fbc.c

1344

h = drm_rect_height(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/intel_fbc.c

1349

static bool i8xx_fbc_tiling_valid(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1351

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_fbc.c

1356

static bool skl_fbc_tiling_valid(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1361

static bool tiling_is_valid(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1363

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1366

return skl_fbc_tiling_valid(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1368

return i8xx_fbc_tiling_valid(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1425

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

143

static unsigned int intel_fbc_plane_stride(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1434

drm_rect_fp_to_int(&src, &plane_state->uapi.src);

drivers/gpu/drm/i915/display/intel_fbc.c

1446

const struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/intel_fbc.c

145

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_fbc.c

1451

WARN_ON(plane_state->no_fbc_reason);

drivers/gpu/drm/i915/display/intel_fbc.c

1459

fbc_state->fence_y_offset = intel_plane_fence_y_offset(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1461

drm_WARN_ON(display->drm, plane_state->fence_id >= 0 &&

drivers/gpu/drm/i915/display/intel_fbc.c

1464

fbc_state->fence_id = plane_state->fence_id;

drivers/gpu/drm/i915/display/intel_fbc.c

1466

fbc_state->cfb_stride = intel_fbc_cfb_stride(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1467

fbc_state->cfb_size = intel_fbc_cfb_size(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1468

fbc_state->override_cfb_stride = intel_fbc_override_cfb_stride(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1471

static bool intel_fbc_is_fence_ok(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1473

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

148

stride = plane_state->view.color_plane[0].mapping_stride;

drivers/gpu/drm/i915/display/intel_fbc.c

1487

return DISPLAY_VER(display) >= 9 || plane_state->fence_id >= 0;

drivers/gpu/drm/i915/display/intel_fbc.c

149

if (!drm_rotation_90_or_270(plane_state->hw.rotation))

drivers/gpu/drm/i915/display/intel_fbc.c

1490

static bool intel_fbc_is_cfb_ok(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1492

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1493

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_fbc.c

1496

return intel_fbc_min_limit(plane_state) <= fbc->limit &&

drivers/gpu/drm/i915/display/intel_fbc.c

1497

intel_fbc_cfb_size(plane_state) <= fbc->limit *

drivers/gpu/drm/i915/display/intel_fbc.c

1501

static bool intel_fbc_is_ok(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1503

return !plane_state->no_fbc_reason &&

drivers/gpu/drm/i915/display/intel_fbc.c

1504

intel_fbc_is_fence_ok(plane_state) &&

drivers/gpu/drm/i915/display/intel_fbc.c

1505

intel_fbc_is_cfb_ok(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1509

__intel_fbc_prepare_dirty_rect(const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_fbc.c

1512

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_fbc.c

1515

int width = drm_rect_width(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/intel_fbc.c

1516

const struct drm_rect *damage = &plane_state->damage;

drivers/gpu/drm/i915/display/intel_fbc.c

1517

int y_offset = plane_state->view.color_plane[0].y;

drivers/gpu/drm/i915/display/intel_fbc.c

1522

!intel_fbc_is_ok(plane_state)) {

drivers/gpu/drm/i915/display/intel_fbc.c

1541

struct intel_plane_state *plane_state;

drivers/gpu/drm/i915/display/intel_fbc.c

1548

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

drivers/gpu/drm/i915/display/intel_fbc.c

155

static unsigned int intel_fbc_cfb_cpp(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1557

__intel_fbc_prepare_dirty_rect(plane_state,

drivers/gpu/drm/i915/display/intel_fbc.c

157

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_fbc.c

1580

struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/intel_fbc.c

1582

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_fbc.c

1583

struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);

drivers/gpu/drm/i915/display/intel_fbc.c

1591

plane_state->no_fbc_reason = "stolen memory not initialised";

drivers/gpu/drm/i915/display/intel_fbc.c

1596

plane_state->no_fbc_reason = "VGPU active";

drivers/gpu/drm/i915/display/intel_fbc.c

1601

plane_state->no_fbc_reason = "disabled per module param or by default";

drivers/gpu/drm/i915/display/intel_fbc.c

1605

if (!plane_state->uapi.visible) {

drivers/gpu/drm/i915/display/intel_fbc.c

1606

plane_state->no_fbc_reason = "plane not visible";

drivers/gpu/drm/i915/display/intel_fbc.c

1611

plane_state->no_fbc_reason = "Wa_16023588340";

drivers/gpu/drm/i915/display/intel_fbc.c

1621

plane_state->no_fbc_reason = "Wa_15018326506";

drivers/gpu/drm/i915/display/intel_fbc.c

1628

plane_state->no_fbc_reason = "VT-d enabled";

drivers/gpu/drm/i915/display/intel_fbc.c

1635

plane_state->no_fbc_reason = "interlaced mode not supported";

drivers/gpu/drm/i915/display/intel_fbc.c

164

static unsigned int intel_fbc_plane_cfb_stride(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

1640

plane_state->no_fbc_reason = "double wide pipe not supported";

drivers/gpu/drm/i915/display/intel_fbc.c

1657

plane_state->no_fbc_reason = "Selective update enabled";

drivers/gpu/drm/i915/display/intel_fbc.c

166

unsigned int cpp = intel_fbc_cfb_cpp(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

1665

plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";

drivers/gpu/drm/i915/display/intel_fbc.c

1669

if (!pixel_format_is_valid(plane_state)) {

drivers/gpu/drm/i915/display/intel_fbc.c

1670

plane_state->no_fbc_reason = "pixel format not supported";

drivers/gpu/drm/i915/display/intel_fbc.c

1674

if (!tiling_is_valid(plane_state)) {

drivers/gpu/drm/i915/display/intel_fbc.c

1675

plane_state->no_fbc_reason = "tiling not supported";

drivers/gpu/drm/i915/display/intel_fbc.c

1679

if (!rotation_is_valid(plane_state)) {

drivers/gpu/drm/i915/display/intel_fbc.c

168

return intel_fbc_plane_stride(plane_state) * cpp;

drivers/gpu/drm/i915/display/intel_fbc.c

1680

plane_state->no_fbc_reason = "rotation not supported";

drivers/gpu/drm/i915/display/intel_fbc.c

1684

if (!stride_is_valid(plane_state)) {

drivers/gpu/drm/i915/display/intel_fbc.c

1685

plane_state->no_fbc_reason = "stride not supported";

drivers/gpu/drm/i915/display/intel_fbc.c

1690

plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE &&

drivers/gpu/drm/i915/display/intel_fbc.c

1692

plane_state->no_fbc_reason = "per-pixel alpha not supported";

drivers/gpu/drm/i915/display/intel_fbc.c

1696

if (!intel_fbc_plane_size_valid(plane_state)) {

drivers/gpu/drm/i915/display/intel_fbc.c

1697

plane_state->no_fbc_reason = "plane size too big";

drivers/gpu/drm/i915/display/intel_fbc.c

1701

if (!intel_fbc_surface_size_ok(plane_state)) {

drivers/gpu/drm/i915/display/intel_fbc.c

1702

plane_state->no_fbc_reason = "surface size too big";

drivers/gpu/drm/i915/display/intel_fbc.c

1712

plane_state->view.color_plane[0].y & 3) {

drivers/gpu/drm/i915/display/intel_fbc.c

1713

plane_state->no_fbc_reason = "plane start Y offset misaligned";

drivers/gpu/drm/i915/display/intel_fbc.c

1719

(plane_state->view.color_plane[0].y +

drivers/gpu/drm/i915/display/intel_fbc.c

1720

(drm_rect_height(&plane_state->uapi.src) >> 16)) & 3) {

drivers/gpu/drm/i915/display/intel_fbc.c

1721

plane_state->no_fbc_reason = "plane end Y offset misaligned";

drivers/gpu/drm/i915/display/intel_fbc.c

1726

plane_state->no_fbc_reason = "pixel rate too high";

drivers/gpu/drm/i915/display/intel_fbc.c

1730

plane_state->no_fbc_reason = NULL;

drivers/gpu/drm/i915/display/intel_fbc.c

1842

const struct intel_plane_state __maybe_unused *plane_state;

drivers/gpu/drm/i915/display/intel_fbc.c

1847

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

drivers/gpu/drm/i915/display/intel_fbc.c

1903

const struct intel_plane_state __maybe_unused *plane_state;

drivers/gpu/drm/i915/display/intel_fbc.c

1907

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

drivers/gpu/drm/i915/display/intel_fbc.c

2002

struct intel_plane_state __maybe_unused *plane_state;

drivers/gpu/drm/i915/display/intel_fbc.c

2006

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

drivers/gpu/drm/i915/display/intel_fbc.c

2022

const struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/intel_fbc.c

2032

if (intel_fbc_is_ok(plane_state)) {

drivers/gpu/drm/i915/display/intel_fbc.c

2042

fbc->no_fbc_reason = plane_state->no_fbc_reason;

drivers/gpu/drm/i915/display/intel_fbc.c

2046

if (!intel_fbc_is_fence_ok(plane_state)) {

drivers/gpu/drm/i915/display/intel_fbc.c

2056

if (intel_fbc_alloc_cfb(fbc, intel_fbc_cfb_size(plane_state),

drivers/gpu/drm/i915/display/intel_fbc.c

2057

intel_fbc_min_limit(plane_state))) {

drivers/gpu/drm/i915/display/intel_fbc.c

2069

intel_fbc_hw_intialize_dirty_rect(fbc, plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

2106

const struct intel_plane_state *plane_state;

drivers/gpu/drm/i915/display/intel_fbc.c

2110

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

drivers/gpu/drm/i915/display/intel_fbc.c

2119

plane_state->no_fbc_reason) {

drivers/gpu/drm/i915/display/intel_fbc.c

215

static unsigned int intel_fbc_cfb_stride(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

217

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

218

unsigned int stride = intel_fbc_plane_cfb_stride(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

219

unsigned int width = drm_rect_width(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/intel_fbc.c

220

unsigned int cpp = intel_fbc_cfb_cpp(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

2401

const struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/intel_fbc.c

2410

plane_state->no_fbc_reason ?: "FBC possible");

drivers/gpu/drm/i915/display/intel_fbc.c

246

static unsigned int intel_fbc_cfb_size(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

248

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

249

unsigned int height = drm_rect_height(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/intel_fbc.c

251

return _intel_fbc_cfb_size(display, height, intel_fbc_cfb_stride(plane_state));

drivers/gpu/drm/i915/display/intel_fbc.c

254

static u16 intel_fbc_override_cfb_stride(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

256

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

257

unsigned int stride_aligned = intel_fbc_cfb_stride(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

258

unsigned int stride = intel_fbc_plane_cfb_stride(plane_state);

drivers/gpu/drm/i915/display/intel_fbc.c

259

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_fbc.c

839

static int intel_fbc_min_limit(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.c

841

return plane_state->hw.fb->format->cpp[0] == 2 ? 2 : 1;

drivers/gpu/drm/i915/display/intel_fbc.h

59

bool intel_fbc_need_pixel_normalizer(const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_fbdev.c

388

struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/intel_fbdev.c

390

struct drm_gem_object *obj = intel_fb_bo(plane_state->uapi.fb);

drivers/gpu/drm/i915/display/intel_fbdev.c

410

fb = to_intel_framebuffer(plane_state->uapi.fb);

drivers/gpu/drm/i915/display/intel_fbdev.c

497

struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/intel_fbdev.c

503

drm_WARN(display->drm, !plane_state->uapi.fb,

drivers/gpu/drm/i915/display/intel_initial_plane.c

124

struct intel_plane_state *plane_state = to_intel_plane_state(plane->base.state);

drivers/gpu/drm/i915/display/intel_initial_plane.c

151

plane_state->uapi.rotation = plane_config->rotation;

drivers/gpu/drm/i915/display/intel_initial_plane.c

153

plane_state->uapi.rotation, &plane_state->view);

drivers/gpu/drm/i915/display/intel_initial_plane.c

159

plane_state->uapi.src_x = 0;

drivers/gpu/drm/i915/display/intel_initial_plane.c

160

plane_state->uapi.src_y = 0;

drivers/gpu/drm/i915/display/intel_initial_plane.c

161

plane_state->uapi.src_w = fb->width << 16;

drivers/gpu/drm/i915/display/intel_initial_plane.c

162

plane_state->uapi.src_h = fb->height << 16;

drivers/gpu/drm/i915/display/intel_initial_plane.c

164

plane_state->uapi.crtc_x = 0;

drivers/gpu/drm/i915/display/intel_initial_plane.c

165

plane_state->uapi.crtc_y = 0;

drivers/gpu/drm/i915/display/intel_initial_plane.c

166

plane_state->uapi.crtc_w = fb->width;

drivers/gpu/drm/i915/display/intel_initial_plane.c

167

plane_state->uapi.crtc_h = fb->height;

drivers/gpu/drm/i915/display/intel_initial_plane.c

169

plane_state->uapi.fb = fb;

drivers/gpu/drm/i915/display/intel_initial_plane.c

172

plane_state->uapi.crtc = &crtc->base;

drivers/gpu/drm/i915/display/intel_initial_plane.c

173

intel_plane_copy_uapi_to_hw_state(plane_state, plane_state, crtc);

drivers/gpu/drm/i915/display/intel_initial_plane.c

56

const struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/intel_initial_plane.c

64

if (!plane_state->ggtt_vma)

drivers/gpu/drm/i915/display/intel_initial_plane.c

69

return plane_state;

drivers/gpu/drm/i915/display/intel_load_detect.c

27

struct drm_plane_state *plane_state;

drivers/gpu/drm/i915/display/intel_load_detect.c

34

for_each_new_plane_in_state(state, plane, plane_state, i) {

drivers/gpu/drm/i915/display/intel_load_detect.c

35

if (plane_state->crtc != crtc)

drivers/gpu/drm/i915/display/intel_load_detect.c

38

ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);

drivers/gpu/drm/i915/display/intel_load_detect.c

42

drm_atomic_set_fb_for_plane(plane_state, NULL);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

482

const struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/intel_modeset_setup.c

485

if (plane_state->uapi.visible &&

drivers/gpu/drm/i915/display/intel_modeset_setup.c

55

const struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/intel_modeset_setup.c

58

if (plane_state->uapi.visible)

drivers/gpu/drm/i915/display/intel_modeset_setup.c

667

struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/intel_modeset_setup.c

678

intel_set_plane_visible(crtc_state, plane_state, visible);

drivers/gpu/drm/i915/display/intel_modeset_setup.c

843

const struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/intel_modeset_setup.c

850

if (plane_state->uapi.visible)

drivers/gpu/drm/i915/display/intel_modeset_setup.c

857

if (plane_state->uapi.visible && plane->min_cdclk) {

drivers/gpu/drm/i915/display/intel_plane.c

1085

int intel_plane_check_clipping(struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_plane.c

1090

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_plane.c

1091

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_plane.c

1092

struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_plane.c

1093

struct drm_rect *src = &plane_state->uapi.src;

drivers/gpu/drm/i915/display/intel_plane.c

1094

struct drm_rect *dst = &plane_state->uapi.dst;

drivers/gpu/drm/i915/display/intel_plane.c

1096

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/intel_plane.c

1100

plane_state->uapi.visible = false;

drivers/gpu/drm/i915/display/intel_plane.c

1121

plane_state->uapi.visible = drm_rect_clip_scaled(src, dst, clip);

drivers/gpu/drm/i915/display/intel_plane.c

1125

if (!can_position && plane_state->uapi.visible &&

drivers/gpu/drm/i915/display/intel_plane.c

1140

int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_plane.c

1142

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_plane.c

1143

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_plane.c

1144

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_plane.c

1145

struct drm_rect *src = &plane_state->uapi.src;

drivers/gpu/drm/i915/display/intel_plane.c

1147

bool rotated = drm_rotation_90_or_270(plane_state->hw.rotation);

drivers/gpu/drm/i915/display/intel_plane.c

1222

intel_plane_fb_min_alignment(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_plane.c

1224

const struct intel_framebuffer *fb = to_intel_framebuffer(plane_state->hw.fb);

drivers/gpu/drm/i915/display/intel_plane.c

1230

intel_plane_fb_min_phys_alignment(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_plane.c

1232

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_plane.c

1233

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_plane.c

1242

intel_plane_fb_vtd_guard(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_plane.c

1244

return intel_fb_view_vtd_guard(plane_state->hw.fb,

drivers/gpu/drm/i915/display/intel_plane.c

1245

&plane_state->view,

drivers/gpu/drm/i915/display/intel_plane.c

1246

plane_state->hw.rotation);

drivers/gpu/drm/i915/display/intel_plane.c

1249

int intel_plane_pin_fb(struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_plane.c

1252

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_plane.c

1253

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_plane.c

1255

to_intel_framebuffer(plane_state->hw.fb);

drivers/gpu/drm/i915/display/intel_plane.c

1270

&plane_state->view.gtt,

drivers/gpu/drm/i915/display/intel_plane.c

1277

.view = &plane_state->view.gtt,

drivers/gpu/drm/i915/display/intel_plane.c

1278

.alignment = intel_plane_fb_min_alignment(plane_state),

drivers/gpu/drm/i915/display/intel_plane.c

1279

.phys_alignment = intel_plane_fb_min_phys_alignment(plane_state),

drivers/gpu/drm/i915/display/intel_plane.c

1280

.vtd_guard = intel_plane_fb_vtd_guard(plane_state),

drivers/gpu/drm/i915/display/intel_plane.c

1289

intel_plane_uses_fence(plane_state) ? &fence_id : NULL);

drivers/gpu/drm/i915/display/intel_plane.c

1292

.view = &plane_state->view.gtt,

drivers/gpu/drm/i915/display/intel_plane.c

1293

.alignment = intel_plane_fb_min_alignment(plane_state),

drivers/gpu/drm/i915/display/intel_plane.c

1305

plane_state->dpt_vma = dpt_vma;

drivers/gpu/drm/i915/display/intel_plane.c

1306

plane_state->ggtt_vma = ggtt_vma;

drivers/gpu/drm/i915/display/intel_plane.c

1307

plane_state->fence_id = fence_id;

drivers/gpu/drm/i915/display/intel_plane.c

1309

plane_state->surf = offset + plane->surf_offset(plane_state);

drivers/gpu/drm/i915/display/intel_plane.c

1534

const struct intel_plane_state *plane_state = to_intel_plane_state(plane->base.state);

drivers/gpu/drm/i915/display/intel_plane.c

1535

struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);

drivers/gpu/drm/i915/display/intel_plane.c

1537

const struct intel_framebuffer *fb = to_intel_framebuffer(plane_state->hw.fb);

drivers/gpu/drm/i915/display/intel_plane.c

1592

struct intel_plane_state *plane_state;

drivers/gpu/drm/i915/display/intel_plane.c

1600

plane_state = to_intel_plane_state(plane->state);

drivers/gpu/drm/i915/display/intel_plane.c

1601

fb = to_intel_framebuffer(plane_state->hw.fb);

drivers/gpu/drm/i915/display/intel_plane.c

1709

struct intel_plane_state *plane_state;

drivers/gpu/drm/i915/display/intel_plane.c

1719

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

drivers/gpu/drm/i915/display/intel_plane.c

172

struct intel_plane_state *plane_state = to_intel_plane_state(state);

drivers/gpu/drm/i915/display/intel_plane.c

174

drm_WARN_ON(plane->dev, plane_state->ggtt_vma);

drivers/gpu/drm/i915/display/intel_plane.c

175

drm_WARN_ON(plane->dev, plane_state->dpt_vma);

drivers/gpu/drm/i915/display/intel_plane.c

1751

link_nv12_planes(crtc_state, plane_state, y_plane_state);

drivers/gpu/drm/i915/display/intel_plane.c

1765

struct intel_plane_state *plane_state;

drivers/gpu/drm/i915/display/intel_plane.c

177

__drm_atomic_helper_plane_destroy_state(&plane_state->uapi);

drivers/gpu/drm/i915/display/intel_plane.c

1770

plane_state = intel_atomic_get_plane_state(state, plane);

drivers/gpu/drm/i915/display/intel_plane.c

1771

if (IS_ERR(plane_state))

drivers/gpu/drm/i915/display/intel_plane.c

1772

return PTR_ERR(plane_state);

drivers/gpu/drm/i915/display/intel_plane.c

178

if (plane_state->hw.fb)

drivers/gpu/drm/i915/display/intel_plane.c

179

drm_framebuffer_put(plane_state->hw.fb);

drivers/gpu/drm/i915/display/intel_plane.c

1802

const struct intel_plane_state *plane_state;

drivers/gpu/drm/i915/display/intel_plane.c

1807

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

drivers/gpu/drm/i915/display/intel_plane.c

1808

struct intel_plane *linked = plane_state->planar_linked_plane;

drivers/gpu/drm/i915/display/intel_plane.c

181

if (plane_state->hw.degamma_lut)

drivers/gpu/drm/i915/display/intel_plane.c

182

drm_property_blob_put(plane_state->hw.degamma_lut);

drivers/gpu/drm/i915/display/intel_plane.c

183

if (plane_state->hw.gamma_lut)

drivers/gpu/drm/i915/display/intel_plane.c

184

drm_property_blob_put(plane_state->hw.gamma_lut);

drivers/gpu/drm/i915/display/intel_plane.c

185

if (plane_state->hw.ctm)

drivers/gpu/drm/i915/display/intel_plane.c

186

drm_property_blob_put(plane_state->hw.ctm);

drivers/gpu/drm/i915/display/intel_plane.c

187

if (plane_state->hw.lut_3d)

drivers/gpu/drm/i915/display/intel_plane.c

1877

struct intel_plane_state __maybe_unused *plane_state;

drivers/gpu/drm/i915/display/intel_plane.c

188

drm_property_blob_put(plane_state->hw.lut_3d);

drivers/gpu/drm/i915/display/intel_plane.c

1886

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

drivers/gpu/drm/i915/display/intel_plane.c

190

kfree(plane_state);

drivers/gpu/drm/i915/display/intel_plane.c

1922

for_each_new_intel_plane_in_state(state, plane, plane_state, i)

drivers/gpu/drm/i915/display/intel_plane.c

268

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_plane.c

282

return intel_adjusted_rate(&plane_state->uapi.src,

drivers/gpu/drm/i915/display/intel_plane.c

283

&plane_state->uapi.dst,

drivers/gpu/drm/i915/display/intel_plane.c

288

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_plane.c

291

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_plane.c

293

if (!plane_state->uapi.visible)

drivers/gpu/drm/i915/display/intel_plane.c

296

return intel_plane_pixel_rate(crtc_state, plane_state) *

drivers/gpu/drm/i915/display/intel_plane.c

302

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_plane.c

305

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_plane.c

306

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_plane.c

313

if (!plane_state->uapi.visible)

drivers/gpu/drm/i915/display/intel_plane.c

321

width = drm_rect_width(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/intel_plane.c

322

height = drm_rect_height(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/intel_plane.c

336

return intel_adjusted_rate(&plane_state->uapi.src,

drivers/gpu/drm/i915/display/intel_plane.c

337

&plane_state->uapi.dst,

drivers/gpu/drm/i915/display/intel_plane.c

344

const struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/intel_plane.c

346

struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);

drivers/gpu/drm/i915/display/intel_plane.c

349

if (!plane_state->uapi.visible || !plane->min_cdclk)

drivers/gpu/drm/i915/display/intel_plane.c

355

plane->min_cdclk(new_crtc_state, plane_state);

drivers/gpu/drm/i915/display/intel_plane.c

358

static void intel_plane_clear_hw_state(struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_plane.c

360

if (plane_state->hw.fb)

drivers/gpu/drm/i915/display/intel_plane.c

361

drm_framebuffer_put(plane_state->hw.fb);

drivers/gpu/drm/i915/display/intel_plane.c

362

if (plane_state->hw.degamma_lut)

drivers/gpu/drm/i915/display/intel_plane.c

363

drm_property_blob_put(plane_state->hw.degamma_lut);

drivers/gpu/drm/i915/display/intel_plane.c

364

if (plane_state->hw.gamma_lut)

drivers/gpu/drm/i915/display/intel_plane.c

365

drm_property_blob_put(plane_state->hw.gamma_lut);

drivers/gpu/drm/i915/display/intel_plane.c

366

if (plane_state->hw.ctm)

drivers/gpu/drm/i915/display/intel_plane.c

367

drm_property_blob_put(plane_state->hw.ctm);

drivers/gpu/drm/i915/display/intel_plane.c

368

if (plane_state->hw.lut_3d)

drivers/gpu/drm/i915/display/intel_plane.c

369

drm_property_blob_put(plane_state->hw.lut_3d);

drivers/gpu/drm/i915/display/intel_plane.c

371

memset(&plane_state->hw, 0, sizeof(plane_state->hw));

drivers/gpu/drm/i915/display/intel_plane.c

394

intel_plane_colorop_replace_blob(struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_plane.c

399

return drm_property_replace_blob(&plane_state->hw.ctm, blob);

drivers/gpu/drm/i915/display/intel_plane.c

401

return drm_property_replace_blob(&plane_state->hw.degamma_lut, blob);

drivers/gpu/drm/i915/display/intel_plane.c

403

return drm_property_replace_blob(&plane_state->hw.gamma_lut, blob);

drivers/gpu/drm/i915/display/intel_plane.c

405

return drm_property_replace_blob(&plane_state->hw.lut_3d, blob);

drivers/gpu/drm/i915/display/intel_plane.c

411

intel_plane_color_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_plane.c

417

struct drm_atomic_commit *state = plane_state->uapi.state;

drivers/gpu/drm/i915/display/intel_plane.c

433

changed |= intel_plane_colorop_replace_blob(plane_state,

drivers/gpu/drm/i915/display/intel_plane.c

445

void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_plane.c

449

intel_plane_clear_hw_state(plane_state);

drivers/gpu/drm/i915/display/intel_plane.c

457

plane_state->hw.crtc = from_plane_state->uapi.crtc ? &crtc->base : NULL;

drivers/gpu/drm/i915/display/intel_plane.c

459

plane_state->hw.fb = from_plane_state->uapi.fb;

drivers/gpu/drm/i915/display/intel_plane.c

460

if (plane_state->hw.fb)

drivers/gpu/drm/i915/display/intel_plane.c

461

drm_framebuffer_get(plane_state->hw.fb);

drivers/gpu/drm/i915/display/intel_plane.c

463

plane_state->hw.alpha = from_plane_state->uapi.alpha;

drivers/gpu/drm/i915/display/intel_plane.c

464

plane_state->hw.pixel_blend_mode =

drivers/gpu/drm/i915/display/intel_plane.c

466

plane_state->hw.rotation = from_plane_state->uapi.rotation;

drivers/gpu/drm/i915/display/intel_plane.c

467

plane_state->hw.color_encoding = from_plane_state->uapi.color_encoding;

drivers/gpu/drm/i915/display/intel_plane.c

468

plane_state->hw.color_range = from_plane_state->uapi.color_range;

drivers/gpu/drm/i915/display/intel_plane.c

469

plane_state->hw.scaling_filter = from_plane_state->uapi.scaling_filter;

drivers/gpu/drm/i915/display/intel_plane.c

471

plane_state->uapi.src = drm_plane_state_src(&from_plane_state->uapi);

drivers/gpu/drm/i915/display/intel_plane.c

472

plane_state->uapi.dst = drm_plane_state_dest(&from_plane_state->uapi);

drivers/gpu/drm/i915/display/intel_plane.c

474

intel_plane_color_copy_uapi_to_hw_state(plane_state, from_plane_state, crtc);

drivers/gpu/drm/i915/display/intel_plane.c

477

void intel_plane_copy_hw_state(struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_plane.c

480

intel_plane_clear_hw_state(plane_state);

drivers/gpu/drm/i915/display/intel_plane.c

482

memcpy(&plane_state->hw, &from_plane_state->hw,

drivers/gpu/drm/i915/display/intel_plane.c

483

sizeof(plane_state->hw));

drivers/gpu/drm/i915/display/intel_plane.c

485

if (plane_state->hw.fb)

drivers/gpu/drm/i915/display/intel_plane.c

486

drm_framebuffer_get(plane_state->hw.fb);

drivers/gpu/drm/i915/display/intel_plane.c

490

struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_plane.c

492

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_plane.c

493

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_plane.c

495

if (!plane_state->planar_linked_plane)

drivers/gpu/drm/i915/display/intel_plane.c

498

plane_state->planar_linked_plane = NULL;

drivers/gpu/drm/i915/display/intel_plane.c

500

if (!plane_state->is_y_plane)

drivers/gpu/drm/i915/display/intel_plane.c

503

drm_WARN_ON(display->drm, plane_state->uapi.visible);

drivers/gpu/drm/i915/display/intel_plane.c

505

plane_state->is_y_plane = false;

drivers/gpu/drm/i915/display/intel_plane.c

515

struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_plane.c

517

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_plane.c

519

unlink_nv12_plane(crtc_state, plane_state);

drivers/gpu/drm/i915/display/intel_plane.c

532

plane_state->uapi.visible = false;

drivers/gpu/drm/i915/display/intel_plane.c

535

static bool intel_plane_is_scaled(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_plane.c

537

int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/intel_plane.c

538

int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/intel_plane.c

539

int dst_w = drm_rect_width(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/intel_plane.c

540

int dst_h = drm_rect_height(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/intel_plane.c

65

static void intel_plane_state_reset(struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_plane.c

68

memset(plane_state, 0, sizeof(*plane_state));

drivers/gpu/drm/i915/display/intel_plane.c

70

__drm_atomic_helper_plane_state_reset(&plane_state->uapi, &plane->base);

drivers/gpu/drm/i915/display/intel_plane.c

72

plane_state->scaler_id = -1;

drivers/gpu/drm/i915/display/intel_plane.c

73

plane_state->fence_id = -1;

drivers/gpu/drm/i915/display/intel_plane.c

78

struct intel_plane_state *plane_state;

drivers/gpu/drm/i915/display/intel_plane.c

85

plane_state = kzalloc_obj(*plane_state);

drivers/gpu/drm/i915/display/intel_plane.c

86

if (!plane_state) {

drivers/gpu/drm/i915/display/intel_plane.c

894

struct intel_plane_state __maybe_unused *plane_state;

drivers/gpu/drm/i915/display/intel_plane.c

901

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

drivers/gpu/drm/i915/display/intel_plane.c

91

intel_plane_state_reset(plane_state, plane);

drivers/gpu/drm/i915/display/intel_plane.c

93

plane->base.state = &plane_state->uapi;

drivers/gpu/drm/i915/display/intel_plane.c

930

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_plane.c

934

trace_intel_plane_update_noarm(plane_state, crtc);

drivers/gpu/drm/i915/display/intel_plane.c

940

plane->update_noarm(dsb, plane, crtc_state, plane_state);

drivers/gpu/drm/i915/display/intel_plane.c

946

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_plane.c

952

plane->async_flip(dsb, plane, crtc_state, plane_state, async_flip);

drivers/gpu/drm/i915/display/intel_plane.c

958

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_plane.c

963

intel_plane_async_flip(dsb, plane, crtc_state, plane_state, true);

drivers/gpu/drm/i915/display/intel_plane.c

967

trace_intel_plane_update_arm(plane_state, crtc);

drivers/gpu/drm/i915/display/intel_plane.c

968

plane->update_arm(dsb, plane, crtc_state, plane_state);

drivers/gpu/drm/i915/display/intel_plane.h

33

const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_plane.h

36

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_plane.h

38

void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_plane.h

41

void intel_plane_copy_hw_state(struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_plane.h

46

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_plane.h

51

const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_plane.h

55

const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_plane.h

75

int intel_plane_check_clipping(struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_plane.h

79

int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_plane.h

81

struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_psr.c

2851

static bool psr2_sel_fetch_plane_state_supported(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_psr.c

2853

if (plane_state->uapi.dst.y1 < 0 ||

drivers/gpu/drm/i915/display/intel_psr.c

2854

plane_state->uapi.dst.x1 < 0 ||

drivers/gpu/drm/i915/display/intel_psr.c

2855

plane_state->scaler_id >= 0 ||

drivers/gpu/drm/i915/display/intel_psr.c

2856

plane_state->hw.rotation != DRM_MODE_ROTATE_0)

drivers/gpu/drm/i915/display/intel_sprite.c

1009

static u32 g4x_sprite_ctl(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

1011

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1012

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_sprite.c

1013

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/intel_sprite.c

1014

const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;

drivers/gpu/drm/i915/display/intel_sprite.c

1058

if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)

drivers/gpu/drm/i915/display/intel_sprite.c

1061

if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)

drivers/gpu/drm/i915/display/intel_sprite.c

1078

static void g4x_sprite_update_gamma(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

1080

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1081

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_sprite.c

1082

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_sprite.c

1108

static void ilk_sprite_update_gamma(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

1110

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1111

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_sprite.c

1112

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_sprite.c

1138

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

1142

int crtc_x = plane_state->uapi.dst.x1;

drivers/gpu/drm/i915/display/intel_sprite.c

1143

int crtc_y = plane_state->uapi.dst.y1;

drivers/gpu/drm/i915/display/intel_sprite.c

1144

u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/intel_sprite.c

1145

u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/intel_sprite.c

1146

u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/intel_sprite.c

1147

u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/intel_sprite.c

1156

plane_state->view.color_plane[0].mapping_stride);

drivers/gpu/drm/i915/display/intel_sprite.c

1168

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

1172

const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;

drivers/gpu/drm/i915/display/intel_sprite.c

1173

u32 x = plane_state->view.color_plane[0].x;

drivers/gpu/drm/i915/display/intel_sprite.c

1174

u32 y = plane_state->view.color_plane[0].y;

drivers/gpu/drm/i915/display/intel_sprite.c

1177

dvscntr = plane_state->ctl | g4x_sprite_ctl_crtc(crtc_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1187

intel_fb_xy_to_linear(x, y, plane_state, 0));

drivers/gpu/drm/i915/display/intel_sprite.c

1197

intel_de_write_fw(display, DVSSURF(pipe), plane_state->surf);

drivers/gpu/drm/i915/display/intel_sprite.c

1200

g4x_sprite_update_gamma(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1202

ilk_sprite_update_gamma(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1272

struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

1274

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1275

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_sprite.c

1276

const struct drm_rect *src = &plane_state->uapi.src;

drivers/gpu/drm/i915/display/intel_sprite.c

1277

const struct drm_rect *dst = &plane_state->uapi.dst;

drivers/gpu/drm/i915/display/intel_sprite.c

1281

unsigned int stride = plane_state->view.color_plane[0].mapping_stride;

drivers/gpu/drm/i915/display/intel_sprite.c

1338

struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

1340

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1345

if (g4x_fb_scalable(plane_state->hw.fb)) {

drivers/gpu/drm/i915/display/intel_sprite.c

1355

ret = intel_plane_check_clipping(plane_state, crtc_state,

drivers/gpu/drm/i915/display/intel_sprite.c

1360

ret = i9xx_check_plane_surface(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1364

if (!plane_state->uapi.visible)

drivers/gpu/drm/i915/display/intel_sprite.c

1367

ret = intel_plane_check_src_coordinates(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1371

ret = g4x_sprite_check_scaling(crtc_state, plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1376

plane_state->ctl = ivb_sprite_ctl(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1378

plane_state->ctl = g4x_sprite_ctl(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1383

int chv_plane_check_rotation(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

1385

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1386

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/intel_sprite.c

140

vlv_sprite_update_clrc(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

1402

struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

1406

ret = chv_plane_check_rotation(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1410

ret = intel_plane_check_clipping(plane_state, crtc_state,

drivers/gpu/drm/i915/display/intel_sprite.c

1417

ret = i9xx_check_plane_surface(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

142

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1421

if (!plane_state->uapi.visible)

drivers/gpu/drm/i915/display/intel_sprite.c

1424

ret = intel_plane_check_src_coordinates(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

1428

plane_state->ctl = vlv_sprite_ctl(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

143

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_sprite.c

144

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_sprite.c

150

plane_state->hw.color_range == DRM_COLOR_YCBCR_LIMITED_RANGE) {

drivers/gpu/drm/i915/display/intel_sprite.c

180

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_sprite.c

184

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_sprite.c

238

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

252

vlv_plane_ratio(crtc_state, plane_state, &num, &den);

drivers/gpu/drm/i915/display/intel_sprite.c

267

static u32 vlv_sprite_ctl(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

269

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_sprite.c

270

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/intel_sprite.c

271

const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;

drivers/gpu/drm/i915/display/intel_sprite.c

324

if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)

drivers/gpu/drm/i915/display/intel_sprite.c

342

static void vlv_sprite_update_gamma(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

344

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

345

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_sprite.c

346

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_sprite.c

369

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

374

int crtc_x = plane_state->uapi.dst.x1;

drivers/gpu/drm/i915/display/intel_sprite.c

375

int crtc_y = plane_state->uapi.dst.y1;

drivers/gpu/drm/i915/display/intel_sprite.c

376

u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/intel_sprite.c

377

u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/intel_sprite.c

380

plane_state->view.color_plane[0].mapping_stride);

drivers/gpu/drm/i915/display/intel_sprite.c

391

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

396

const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;

drivers/gpu/drm/i915/display/intel_sprite.c

397

u32 x = plane_state->view.color_plane[0].x;

drivers/gpu/drm/i915/display/intel_sprite.c

398

u32 y = plane_state->view.color_plane[0].y;

drivers/gpu/drm/i915/display/intel_sprite.c

401

sprctl = plane_state->ctl | vlv_sprite_ctl_crtc(crtc_state);

drivers/gpu/drm/i915/display/intel_sprite.c

404

chv_sprite_update_csc(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

418

intel_fb_xy_to_linear(x, y, plane_state, 0));

drivers/gpu/drm/i915/display/intel_sprite.c

428

intel_de_write_fw(display, SPSURF(pipe, plane_id), plane_state->surf);

drivers/gpu/drm/i915/display/intel_sprite.c

430

vlv_sprite_update_clrc(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

431

vlv_sprite_update_gamma(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

483

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_sprite.c

487

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_sprite.c

520

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_sprite.c

523

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_sprite.c

547

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

561

ivb_plane_ratio(crtc_state, plane_state, &num, &den);

drivers/gpu/drm/i915/display/intel_sprite.c

567

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

581

src_w = drm_rect_width(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/intel_sprite.c

582

dst_w = drm_rect_width(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/intel_sprite.c

585

ivb_plane_ratio_scaling(crtc_state, plane_state, &num, &den);

drivers/gpu/drm/i915/display/intel_sprite.c

587

ivb_plane_ratio(crtc_state, plane_state, &num, &den);

drivers/gpu/drm/i915/display/intel_sprite.c

597

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_sprite.c

601

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_sprite.c

630

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

635

hsw_plane_ratio(crtc_state, plane_state, &num, &den);

drivers/gpu/drm/i915/display/intel_sprite.c

653

static bool ivb_need_sprite_gamma(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

655

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

656

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_sprite.c

662

static u32 ivb_sprite_ctl(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

664

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

665

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_sprite.c

666

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/intel_sprite.c

667

const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;

drivers/gpu/drm/i915/display/intel_sprite.c

68

chv_sprite_update_csc(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

70

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

71

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_sprite.c

711

if (!ivb_need_sprite_gamma(plane_state))

drivers/gpu/drm/i915/display/intel_sprite.c

714

if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)

drivers/gpu/drm/i915/display/intel_sprite.c

717

if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)

drivers/gpu/drm/i915/display/intel_sprite.c

72

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_sprite.c

734

static void ivb_sprite_linear_gamma(const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_sprite.c

759

static void ivb_sprite_update_gamma(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

761

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

762

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_sprite.c

767

if (!ivb_need_sprite_gamma(plane_state))

drivers/gpu/drm/i915/display/intel_sprite.c

770

ivb_sprite_linear_gamma(plane_state, gamma);

drivers/gpu/drm/i915/display/intel_sprite.c

792

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

796

int crtc_x = plane_state->uapi.dst.x1;

drivers/gpu/drm/i915/display/intel_sprite.c

797

int crtc_y = plane_state->uapi.dst.y1;

drivers/gpu/drm/i915/display/intel_sprite.c

798

u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/intel_sprite.c

799

u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/intel_sprite.c

800

u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/intel_sprite.c

801

u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/intel_sprite.c

810

plane_state->view.color_plane[0].mapping_stride);

drivers/gpu/drm/i915/display/intel_sprite.c

823

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

827

const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;

drivers/gpu/drm/i915/display/intel_sprite.c

828

u32 x = plane_state->view.color_plane[0].x;

drivers/gpu/drm/i915/display/intel_sprite.c

829

u32 y = plane_state->view.color_plane[0].y;

drivers/gpu/drm/i915/display/intel_sprite.c

832

sprctl = plane_state->ctl | ivb_sprite_ctl_crtc(crtc_state);

drivers/gpu/drm/i915/display/intel_sprite.c

848

intel_fb_xy_to_linear(x, y, plane_state, 0));

drivers/gpu/drm/i915/display/intel_sprite.c

859

intel_de_write_fw(display, SPRSURF(pipe), plane_state->surf);

drivers/gpu/drm/i915/display/intel_sprite.c

861

ivb_sprite_update_gamma(plane_state);

drivers/gpu/drm/i915/display/intel_sprite.c

914

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_sprite.c

916

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/intel_sprite.c

930

hscale = drm_rect_calc_hscale(&plane_state->uapi.src,

drivers/gpu/drm/i915/display/intel_sprite.c

931

&plane_state->uapi.dst,

drivers/gpu/drm/i915/display/intel_sprite.c

98

const s16 *csc = csc_matrix[plane_state->hw.color_encoding];

drivers/gpu/drm/i915/display/intel_sprite.h

19

int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_sprite.h

20

int chv_plane_check_rotation(const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_sprite.h

23

const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_sprite.h

25

const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_sprite.h

27

const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/intel_sprite_uapi.c

106

plane_state = drm_atomic_get_plane_state(state,

drivers/gpu/drm/i915/display/intel_sprite_uapi.c

108

ret = PTR_ERR_OR_ZERO(plane_state);

drivers/gpu/drm/i915/display/intel_sprite_uapi.c

110

intel_plane_set_ckey(to_intel_plane_state(plane_state), set);

drivers/gpu/drm/i915/display/intel_sprite_uapi.c

16

static void intel_plane_set_ckey(struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/intel_sprite_uapi.c

19

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/intel_sprite_uapi.c

20

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_sprite_uapi.c

21

struct drm_intel_sprite_colorkey *key = &plane_state->ckey;

drivers/gpu/drm/i915/display/intel_sprite_uapi.c

48

struct drm_plane_state *plane_state;

drivers/gpu/drm/i915/display/intel_sprite_uapi.c

92

plane_state = drm_atomic_get_plane_state(state, plane);

drivers/gpu/drm/i915/display/intel_sprite_uapi.c

93

ret = PTR_ERR_OR_ZERO(plane_state);

drivers/gpu/drm/i915/display/intel_sprite_uapi.c

95

intel_plane_set_ckey(to_intel_plane_state(plane_state), set);

drivers/gpu/drm/i915/display/intel_wm.c

120

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_wm.c

122

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/intel_wm.c

137

return plane_state->hw.fb != NULL;

drivers/gpu/drm/i915/display/intel_wm.c

139

return plane_state->uapi.visible;

drivers/gpu/drm/i915/display/intel_wm.h

30

const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/skl_scaler.c

305

struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_scaler.c

307

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_scaler.c

308

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/skl_scaler.c

309

struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_scaler.c

310

bool force_detach = !fb || !plane_state->uapi.visible;

drivers/gpu/drm/i915/display/skl_scaler.c

320

&plane_state->scaler_id,

drivers/gpu/drm/i915/display/skl_scaler.c

321

drm_rect_width(&plane_state->uapi.src) >> 16,

drivers/gpu/drm/i915/display/skl_scaler.c

322

drm_rect_height(&plane_state->uapi.src) >> 16,

drivers/gpu/drm/i915/display/skl_scaler.c

323

drm_rect_width(&plane_state->uapi.dst),

drivers/gpu/drm/i915/display/skl_scaler.c

324

drm_rect_height(&plane_state->uapi.dst),

drivers/gpu/drm/i915/display/skl_scaler.c

337

struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/skl_scaler.c

399

struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/skl_scaler.c

409

*scaler_id = intel_allocate_scaler(scaler_state, crtc, plane_state, casf_scaler);

drivers/gpu/drm/i915/display/skl_scaler.c

416

if (plane_state && plane_state->hw.fb &&

drivers/gpu/drm/i915/display/skl_scaler.c

417

plane_state->hw.fb->format->is_yuv &&

drivers/gpu/drm/i915/display/skl_scaler.c

418

plane_state->hw.fb->format->num_planes > 1) {

drivers/gpu/drm/i915/display/skl_scaler.c

419

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/skl_scaler.c

432

plane_state->planar_linked_plane;

drivers/gpu/drm/i915/display/skl_scaler.c

455

if (plane_state && plane_state->hw.fb) {

drivers/gpu/drm/i915/display/skl_scaler.c

456

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_scaler.c

457

const struct drm_rect *src = &plane_state->uapi.src;

drivers/gpu/drm/i915/display/skl_scaler.c

458

const struct drm_rect *dst = &plane_state->uapi.dst;

drivers/gpu/drm/i915/display/skl_scaler.c

557

struct intel_plane_state *plane_state;

drivers/gpu/drm/i915/display/skl_scaler.c

563

plane_state = intel_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/i915/display/skl_scaler.c

570

if (!plane_state && DISPLAY_VER(display) >= 10)

drivers/gpu/drm/i915/display/skl_scaler.c

573

plane_state = intel_atomic_get_plane_state(state, plane);

drivers/gpu/drm/i915/display/skl_scaler.c

574

if (IS_ERR(plane_state))

drivers/gpu/drm/i915/display/skl_scaler.c

575

return PTR_ERR(plane_state);

drivers/gpu/drm/i915/display/skl_scaler.c

580

plane_state, &plane_state->scaler_id,

drivers/gpu/drm/i915/display/skl_scaler.c

859

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_scaler.c

862

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_scaler.c

864

int scaler_id = plane_state->scaler_id;

drivers/gpu/drm/i915/display/skl_scaler.c

867

int crtc_x = plane_state->uapi.dst.x1;

drivers/gpu/drm/i915/display/skl_scaler.c

868

int crtc_y = plane_state->uapi.dst.y1;

drivers/gpu/drm/i915/display/skl_scaler.c

869

u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/skl_scaler.c

870

u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/skl_scaler.c

876

hscale = drm_rect_calc_hscale(&plane_state->uapi.src,

drivers/gpu/drm/i915/display/skl_scaler.c

877

&plane_state->uapi.dst,

drivers/gpu/drm/i915/display/skl_scaler.c

879

vscale = drm_rect_calc_vscale(&plane_state->uapi.src,

drivers/gpu/drm/i915/display/skl_scaler.c

880

&plane_state->uapi.dst,

drivers/gpu/drm/i915/display/skl_scaler.c

902

skl_scaler_get_filter_select(plane_state->hw.scaling_filter, false);

drivers/gpu/drm/i915/display/skl_scaler.c

908

plane_state->hw.scaling_filter);

drivers/gpu/drm/i915/display/skl_scaler.h

22

struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/skl_scaler.h

32

const struct intel_plane_state *plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1020

static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1022

if (!plane_state->hw.fb->format->has_alpha)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1025

switch (plane_state->hw.pixel_blend_mode) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

1033

MISSING_CASE(plane_state->hw.pixel_blend_mode);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1038

static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1040

if (!plane_state->hw.fb->format->has_alpha)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1043

switch (plane_state->hw.pixel_blend_mode) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

1051

MISSING_CASE(plane_state->hw.pixel_blend_mode);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1145

static u32 adlp_plane_ctl_arb_slots(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1147

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1185

static u32 skl_plane_ctl(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1187

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1188

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1189

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1190

const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1196

plane_ctl |= skl_plane_ctl_alpha(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1199

if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1202

if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1221

plane_ctl |= adlp_plane_ctl_arb_slots(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1243

static u32 glk_plane_color_ctl(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1245

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1246

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1247

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1251

plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1254

switch (plane_state->hw.color_encoding) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

1266

if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1270

if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1274

if (plane_state->force_black)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1277

if (plane_state->hw.degamma_lut)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1280

if (plane_state->hw.ctm)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1283

if (plane_state->hw.gamma_lut) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

1285

if (drm_color_lut32_size(plane_state->hw.gamma_lut) != 32)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1292

static u32 skl_surf_address(const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

1295

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1296

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1297

u32 offset = plane_state->view.color_plane[color_plane].offset;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1308

static int icl_plane_color_plane(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1310

if (plane_state->planar_linked_plane && !plane_state->is_y_plane)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1316

static u32 skl_plane_surf_offset(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1318

int color_plane = icl_plane_color_plane(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1321

plane_surf = skl_surf_address(plane_state, color_plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1323

if (plane_state->decrypt)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1329

u32 skl_plane_aux_dist(const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

1332

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1333

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1340

aux_dist = skl_surf_address(plane_state, aux_plane) -

drivers/gpu/drm/i915/display/skl_universal_plane.c

1341

skl_surf_address(plane_state, color_plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1344

aux_dist |= PLANE_AUX_STRIDE(skl_plane_stride(plane_state, aux_plane));

drivers/gpu/drm/i915/display/skl_universal_plane.c

1349

static u32 skl_plane_keyval(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1351

const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1356

static u32 skl_plane_keymax(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1358

const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1359

u8 alpha = plane_state->hw.alpha >> 8;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1364

static u32 skl_plane_keymsk(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1366

const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1367

u8 alpha = plane_state->hw.alpha >> 8;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1407

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1412

u32 stride = skl_plane_stride(plane_state, 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1413

int crtc_x = plane_state->uapi.dst.x1;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1414

int crtc_y = plane_state->uapi.dst.y1;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1415

u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1416

u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1419

if (plane_state->scaler_id >= 0) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

1438

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1443

u32 x = plane_state->view.color_plane[0].x;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1444

u32 y = plane_state->view.color_plane[0].y;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1447

plane_ctl = plane_state->ctl |

drivers/gpu/drm/i915/display/skl_universal_plane.c

1456

plane_color_ctl = plane_state->color_ctl |

drivers/gpu/drm/i915/display/skl_universal_plane.c

1460

skl_plane_keyval(plane_state));

drivers/gpu/drm/i915/display/skl_universal_plane.c

1462

skl_plane_keymsk(plane_state));

drivers/gpu/drm/i915/display/skl_universal_plane.c

1464

skl_plane_keymax(plane_state));

drivers/gpu/drm/i915/display/skl_universal_plane.c

1470

skl_plane_aux_dist(plane_state, 0));

drivers/gpu/drm/i915/display/skl_universal_plane.c

1473

PLANE_OFFSET_Y(plane_state->view.color_plane[1].y) |

drivers/gpu/drm/i915/display/skl_universal_plane.c

1474

PLANE_OFFSET_X(plane_state->view.color_plane[1].x));

drivers/gpu/drm/i915/display/skl_universal_plane.c

1487

if (plane_state->scaler_id >= 0)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1488

skl_program_plane_scaler(dsb, plane, crtc_state, plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1498

plane_state->surf);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1504

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

1516

clip = &plane_state->psr2_sel_fetch_area;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1519

y = max(0, plane_state->uapi.dst.y1 - crtc_state->psr2_su_area.y1);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1521

y = (clip->y1 + plane_state->uapi.dst.y1);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1523

val |= plane_state->uapi.dst.x1;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1526

x = plane_state->view.color_plane[color_plane].x;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1533

y = plane_state->view.color_plane[color_plane].y + clip->y1;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1535

y = plane_state->view.color_plane[color_plane].y + DIV_ROUND_UP(clip->y1, 2);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1543

val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1551

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1556

int color_plane = icl_plane_color_plane(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1557

u32 stride = skl_plane_stride(plane_state, color_plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1558

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1559

int crtc_x = plane_state->uapi.dst.x1;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1560

int crtc_y = plane_state->uapi.dst.y1;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1561

int x = plane_state->view.color_plane[color_plane].x;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1562

int y = plane_state->view.color_plane[color_plane].y;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1563

int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1564

int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1567

plane_color_ctl = plane_state->color_ctl |

drivers/gpu/drm/i915/display/skl_universal_plane.c

1570

intel_color_plane_program_pipeline(dsb, plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1573

if (plane_state->scaler_id >= 0) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

1586

skl_plane_keyval(plane_state));

drivers/gpu/drm/i915/display/skl_universal_plane.c

1588

skl_plane_keymsk(plane_state));

drivers/gpu/drm/i915/display/skl_universal_plane.c

1590

skl_plane_keymax(plane_state));

drivers/gpu/drm/i915/display/skl_universal_plane.c

1597

lower_32_bits(plane_state->ccval));

drivers/gpu/drm/i915/display/skl_universal_plane.c

1599

upper_32_bits(plane_state->ccval));

drivers/gpu/drm/i915/display/skl_universal_plane.c

1605

skl_plane_aux_dist(plane_state, color_plane));

drivers/gpu/drm/i915/display/skl_universal_plane.c

1609

plane_state->cus_ctl);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1615

icl_program_input_csc(dsb, plane, plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1623

if (plane_state->force_black)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1626

icl_plane_update_sel_fetch_noarm(dsb, plane, crtc_state, plane_state, color_plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1632

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1640

if (drm_rect_height(&plane_state->psr2_sel_fetch_area) > 0)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1651

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1658

plane_ctl = plane_state->ctl |

drivers/gpu/drm/i915/display/skl_universal_plane.c

1668

if (plane_state->scaler_id >= 0)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1669

skl_program_plane_scaler(dsb, plane, crtc_state, plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1671

icl_plane_update_sel_fetch_arm(dsb, plane, crtc_state, plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1673

intel_color_plane_commit_arm(dsb, plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1683

pixel_normalizer_value(plane_state));

drivers/gpu/drm/i915/display/skl_universal_plane.c

1693

plane_state->surf);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1711

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

1717

u32 plane_ctl = plane_state->ctl;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1718

u32 plane_surf = plane_state->surf;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1748

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1750

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1751

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1752

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1753

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1835

plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE &&

drivers/gpu/drm/i915/display/skl_universal_plane.c

1847

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1849

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1850

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1851

int crtc_x = plane_state->uapi.dst.x1;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1852

int crtc_w = drm_rect_width(&plane_state->uapi.dst);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1878

static int skl_plane_check_nv12_rotation(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

1880

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1881

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1882

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1883

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1884

int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1958

skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

1962

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1963

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1964

int aux_x = plane_state->view.color_plane[ccs_plane].x;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1965

int aux_y = plane_state->view.color_plane[ccs_plane].y;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1966

u32 aux_offset = plane_state->view.color_plane[ccs_plane].offset;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1984

plane_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

1995

plane_state->view.color_plane[ccs_plane].offset = aux_offset;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1996

plane_state->view.color_plane[ccs_plane].x = aux_x;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1997

plane_state->view.color_plane[ccs_plane].y = aux_y;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2003

int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2006

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2007

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2008

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2010

u32 aux_offset = plane_state->view.color_plane[aux_plane].offset;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2012

int w = drm_rect_width(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2014

intel_add_fb_offsets(x, y, plane_state, 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2015

*offset = intel_plane_compute_aligned_offset(x, y, plane_state, 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2025

*offset = intel_plane_adjust_aligned_offset(x, y, plane_state, 0,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2038

while ((*x + w) * cpp > plane_state->view.color_plane[0].mapping_stride) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

2046

*offset = intel_plane_adjust_aligned_offset(x, y, plane_state, 0,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2055

static int skl_check_main_surface(struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2057

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2058

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2059

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2060

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2061

int x = plane_state->uapi.src.x1 >> 16;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2062

int y = plane_state->uapi.src.y1 >> 16;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2063

int w = drm_rect_width(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2064

int h = drm_rect_height(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2082

ret = skl_calc_main_surface_offset(plane_state, &x, &y, &offset);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2092

while (!skl_check_main_ccs_coordinates(plane_state, x, y,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2097

offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2101

if (x != plane_state->view.color_plane[aux_plane].x ||

drivers/gpu/drm/i915/display/skl_universal_plane.c

2102

y != plane_state->view.color_plane[aux_plane].y) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

2115

plane_state->view.color_plane[0].offset = offset;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2116

plane_state->view.color_plane[0].x = x;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2117

plane_state->view.color_plane[0].y = y;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2123

drm_rect_translate_to(&plane_state->uapi.src,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2129

static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2131

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2132

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2133

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2134

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2150

int luma_x = plane_state->uapi.src.x1 >> 16;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2151

int luma_y = plane_state->uapi.src.y1 >> 16;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2152

int luma_w = drm_rect_width(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2153

int luma_h = drm_rect_height(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2169

intel_add_fb_offsets(&x, &y, plane_state, uv_plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2171

plane_state, uv_plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2174

u32 aux_offset = plane_state->view.color_plane[ccs_plane].offset;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2179

plane_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2184

while (!skl_check_main_ccs_coordinates(plane_state, x, y,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2190

plane_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2195

if (x != plane_state->view.color_plane[ccs_plane].x ||

drivers/gpu/drm/i915/display/skl_universal_plane.c

2196

y != plane_state->view.color_plane[ccs_plane].y) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

2209

plane_state->view.color_plane[uv_plane].offset = offset;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2210

plane_state->view.color_plane[uv_plane].x = x;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2211

plane_state->view.color_plane[uv_plane].y = y;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2216

static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2218

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2219

int src_x = plane_state->uapi.src.x1 >> 16;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2220

int src_y = plane_state->uapi.src.y1 >> 16;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2241

intel_add_fb_offsets(&x, &y, plane_state, ccs_plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2244

plane_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2247

plane_state->view.color_plane[ccs_plane].offset = offset;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2248

plane_state->view.color_plane[ccs_plane].x = (x * hsub + src_x % hsub) / main_hsub;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2249

plane_state->view.color_plane[ccs_plane].y = (y * vsub + src_y % vsub) / main_vsub;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2255

static int skl_check_plane_surface(struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2257

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2260

ret = intel_plane_compute_gtt(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2264

if (!plane_state->uapi.visible)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2272

ret = skl_check_ccs_aux_surface(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2279

ret = skl_check_nv12_aux_surface(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2284

ret = skl_check_main_surface(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2313

static void check_protection(struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2315

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2316

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2322

plane_state->decrypt = intel_bo_key_check(obj) == 0;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2323

plane_state->force_black = intel_bo_is_protected(obj) &&

drivers/gpu/drm/i915/display/skl_universal_plane.c

2324

!plane_state->decrypt;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2328

make_damage_viewport_relative(struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2330

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2331

const struct drm_rect *src = &plane_state->uapi.src;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2332

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2333

struct drm_rect *damage = &plane_state->damage;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2338

if (!fb || !plane_state->uapi.visible) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

2339

plane_state->damage = DRM_RECT_INIT(0, 0, 0, 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2352

static void clip_damage(struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2354

struct drm_rect *damage = &plane_state->damage;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2360

drm_rect_fp_to_int(&src, &plane_state->uapi.src);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2366

struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2368

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2369

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2370

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2375

ret = skl_plane_check_fb(crtc_state, plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2380

if (!plane_state->ckey.flags && skl_fb_scalable(fb)) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

2385

ret = intel_plane_check_clipping(plane_state, crtc_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2390

make_damage_viewport_relative(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2392

ret = skl_check_plane_surface(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2396

if (!plane_state->uapi.visible)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2399

ret = skl_plane_check_dst_coordinates(crtc_state, plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2403

ret = intel_plane_check_src_coordinates(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2407

clip_damage(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2409

ret = skl_plane_check_nv12_rotation(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2413

check_protection(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2416

if (!(plane_state->hw.alpha >> 8)) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

2417

plane_state->uapi.visible = false;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2418

plane_state->damage = DRM_RECT_INIT(0, 0, 0, 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2421

plane_state->ctl = skl_plane_ctl(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2424

plane_state->color_ctl = glk_plane_color_ctl(plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2429

plane_state->cus_ctl = PLANE_CUS_ENABLE |

drivers/gpu/drm/i915/display/skl_universal_plane.c

2433

plane_state->cus_ctl = 0;

drivers/gpu/drm/i915/display/skl_universal_plane.c

267

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

269

unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

276

glk_plane_ratio(const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

279

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_universal_plane.c

291

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

293

unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

296

glk_plane_ratio(plane_state, &num, &den);

drivers/gpu/drm/i915/display/skl_universal_plane.c

303

skl_plane_ratio(const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

306

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_universal_plane.c

318

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

320

unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);

drivers/gpu/drm/i915/display/skl_universal_plane.c

3227

const struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/skl_universal_plane.c

323

skl_plane_ratio(plane_state, &num, &den);

drivers/gpu/drm/i915/display/skl_universal_plane.c

3232

if (!plane_state->uapi.visible)

drivers/gpu/drm/i915/display/skl_universal_plane.c

3239

if (plane_config->base == plane_state->surf)

drivers/gpu/drm/i915/display/skl_universal_plane.c

3242

intel_de_write(display, PLANE_SURF(pipe, plane_id), plane_state->surf);

drivers/gpu/drm/i915/display/skl_universal_plane.c

678

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

722

const u16 *csc = input_csc_matrix[plane_state->hw.color_encoding];

drivers/gpu/drm/i915/display/skl_universal_plane.c

766

static u32 skl_plane_stride(const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/skl_universal_plane.c

769

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_universal_plane.c

770

unsigned int rotation = plane_state->hw.rotation;

drivers/gpu/drm/i915/display/skl_universal_plane.c

771

u32 stride = plane_state->view.color_plane[color_plane].scanout_stride;

drivers/gpu/drm/i915/display/skl_universal_plane.c

901

static u32 pixel_normalizer_value(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_universal_plane.c

903

if (!intel_fbc_need_pixel_normalizer(plane_state))

drivers/gpu/drm/i915/display/skl_universal_plane.h

32

int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/skl_universal_plane.h

43

u32 skl_plane_aux_dist(const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/skl_watermark.c

1755

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/skl_watermark.c

1758

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_watermark.c

1766

width = drm_rect_width(&plane_state->uapi.src) >> 16;

drivers/gpu/drm/i915/display/skl_watermark.c

1770

plane_state->hw.rotation,

drivers/gpu/drm/i915/display/skl_watermark.c

1771

intel_plane_pixel_rate(crtc_state, plane_state),

drivers/gpu/drm/i915/display/skl_watermark.c

1773

plane_state->uapi.src.x1);

drivers/gpu/drm/i915/display/skl_watermark.c

2047

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/skl_watermark.c

2055

ret = skl_compute_plane_wm_params(crtc_state, plane_state,

drivers/gpu/drm/i915/display/skl_watermark.c

2076

const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/display/skl_watermark.c

2086

ret = skl_compute_plane_wm_params(crtc_state, plane_state,

drivers/gpu/drm/i915/display/skl_watermark.c

2104

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_watermark.c

2106

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/skl_watermark.c

2109

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_watermark.c

2114

if (!intel_wm_plane_visible(crtc_state, plane_state))

drivers/gpu/drm/i915/display/skl_watermark.c

2117

ret = skl_build_plane_wm_single(crtc_state, plane_state,

drivers/gpu/drm/i915/display/skl_watermark.c

2123

ret = skl_build_plane_wm_uv(crtc_state, plane_state,

drivers/gpu/drm/i915/display/skl_watermark.c

2133

const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/skl_watermark.c

2135

struct intel_display *display = to_intel_display(plane_state);

drivers/gpu/drm/i915/display/skl_watermark.c

2136

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

drivers/gpu/drm/i915/display/skl_watermark.c

2142

if (plane_state->is_y_plane)

drivers/gpu/drm/i915/display/skl_watermark.c

2147

if (plane_state->planar_linked_plane) {

drivers/gpu/drm/i915/display/skl_watermark.c

2148

const struct drm_framebuffer *fb = plane_state->hw.fb;

drivers/gpu/drm/i915/display/skl_watermark.c

2151

!intel_wm_plane_visible(crtc_state, plane_state));

drivers/gpu/drm/i915/display/skl_watermark.c

2155

ret = skl_build_plane_wm_single(crtc_state, plane_state,

drivers/gpu/drm/i915/display/skl_watermark.c

2156

plane_state->planar_linked_plane, 0);

drivers/gpu/drm/i915/display/skl_watermark.c

2160

ret = skl_build_plane_wm_single(crtc_state, plane_state,

drivers/gpu/drm/i915/display/skl_watermark.c

2164

} else if (intel_wm_plane_visible(crtc_state, plane_state)) {

drivers/gpu/drm/i915/display/skl_watermark.c

2165

ret = skl_build_plane_wm_single(crtc_state, plane_state,

drivers/gpu/drm/i915/display/skl_watermark.c

2348

const struct intel_plane_state *plane_state;

drivers/gpu/drm/i915/display/skl_watermark.c

2352

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

drivers/gpu/drm/i915/display/skl_watermark.c

2362

ret = icl_build_plane_wm(crtc_state, plane_state);

drivers/gpu/drm/i915/display/skl_watermark.c

2364

ret = skl_build_plane_wm(crtc_state, plane_state);

drivers/gpu/drm/i915/display/skl_watermark.c

2445

struct intel_plane_state *plane_state;

drivers/gpu/drm/i915/display/skl_watermark.c

2460

plane_state = intel_atomic_get_plane_state(state, plane);

drivers/gpu/drm/i915/display/skl_watermark.c

2461

if (IS_ERR(plane_state))

drivers/gpu/drm/i915/display/skl_watermark.c

2462

return PTR_ERR(plane_state);

drivers/gpu/drm/i915/display/skl_watermark.c

2794

struct intel_plane_state *plane_state;

drivers/gpu/drm/i915/display/skl_watermark.c

2817

plane_state = intel_atomic_get_plane_state(state, plane);

drivers/gpu/drm/i915/display/skl_watermark.c

2818

if (IS_ERR(plane_state))

drivers/gpu/drm/i915/display/skl_watermark.c

2819

return PTR_ERR(plane_state);

drivers/gpu/drm/i915/display/skl_watermark.c

3806

const struct intel_plane_state *plane_state =

drivers/gpu/drm/i915/display/skl_watermark.c

3811

if (plane_state->uapi.visible)

drivers/gpu/drm/i915/i915_initial_plane.c

256

struct intel_plane_state *plane_state = to_intel_plane_state(_plane_state);

drivers/gpu/drm/i915/i915_initial_plane.c

260

plane_state->ggtt_vma = i915_vma_get(vma);

drivers/gpu/drm/i915/i915_initial_plane.c

261

if (intel_plane_uses_fence(plane_state) &&

drivers/gpu/drm/i915/i915_initial_plane.c

263

plane_state->fence_id = vma->fence->id;

drivers/gpu/drm/i915/i915_initial_plane.c

265

plane_state->surf = i915_ggtt_offset(plane_state->ggtt_vma);

drivers/gpu/drm/imx/dc/dc-plane.c

100

if (!plane_state->fb)

drivers/gpu/drm/imx/dc/dc-plane.c

103

if (!plane_state->crtc) {

drivers/gpu/drm/imx/dc/dc-plane.c

109

drm_atomic_get_new_crtc_state(state, plane_state->crtc);

drivers/gpu/drm/imx/dc/dc-plane.c

113

ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state,

drivers/gpu/drm/imx/dc/dc-plane.c

122

ret = dc_plane_check_max_source_resolution(plane_state);

drivers/gpu/drm/imx/dc/dc-plane.c

126

return dc_plane_check_fb(plane_state);

drivers/gpu/drm/imx/dc/dc-plane.c

94

struct drm_plane_state *plane_state =

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

810

struct drm_plane_state *plane_state;

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

832

for_each_new_plane_in_state(state, plane, plane_state, i) {

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

833

ipu_state = to_ipu_plane_state(plane_state);

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

836

if (!plane_state->fb) {

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

841

if (!(plane_state->fb->flags & DRM_MODE_FB_MODIFIERS) ||

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

842

plane_state->fb->modifier == DRM_FORMAT_MOD_LINEAR)

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

849

plane_state->fb->format->format,

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

850

plane_state->fb->modifier))

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

857

for_each_new_plane_in_state(state, plane, plane_state, i) {

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

858

ipu_state = to_ipu_plane_state(plane_state);

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

861

if (!plane_state->fb) {

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

866

if ((plane_state->fb->flags & DRM_MODE_FB_MODIFIERS) &&

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

867

plane_state->fb->modifier != DRM_FORMAT_MOD_LINEAR)

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

871

plane_state->fb->modifier = DRM_FORMAT_MOD_LINEAR;

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

875

plane_state->fb->format->format,

drivers/gpu/drm/imx/ipuv3/ipuv3-plane.c

876

plane_state->fb->modifier)) {

drivers/gpu/drm/imx/lcdc/imx-lcdc.c

192

struct drm_plane_state *plane_state)

drivers/gpu/drm/imx/lcdc/imx-lcdc.c

209

bpp = imx_lcdc_get_format(plane_state->fb->format->format);

drivers/gpu/drm/imx/lcdc/imx-lcdc.c

276

struct drm_plane_state *plane_state,

drivers/gpu/drm/mcde/mcde_display.c

1154

struct drm_plane_state *plane_state)

drivers/gpu/drm/mediatek/mtk_crtc.c

306

struct mtk_plane_state *plane_state;

drivers/gpu/drm/mediatek/mtk_crtc.c

308

plane_state = to_mtk_plane_state(plane->state);

drivers/gpu/drm/mediatek/mtk_crtc.c

310

plane_state->pending.config = false;

drivers/gpu/drm/mediatek/mtk_crtc.c

318

struct mtk_plane_state *plane_state;

drivers/gpu/drm/mediatek/mtk_crtc.c

320

plane_state = to_mtk_plane_state(plane->state);

drivers/gpu/drm/mediatek/mtk_crtc.c

322

plane_state->pending.async_config = false;

drivers/gpu/drm/mediatek/mtk_crtc.c

419

struct mtk_plane_state *plane_state;

drivers/gpu/drm/mediatek/mtk_crtc.c

423

plane_state = to_mtk_plane_state(plane->state);

drivers/gpu/drm/mediatek/mtk_crtc.c

426

plane_state->pending.enable = false;

drivers/gpu/drm/mediatek/mtk_crtc.c

430

plane_state, NULL);

drivers/gpu/drm/mediatek/mtk_crtc.c

512

struct mtk_plane_state *plane_state;

drivers/gpu/drm/mediatek/mtk_crtc.c

514

plane_state = to_mtk_plane_state(plane->state);

drivers/gpu/drm/mediatek/mtk_crtc.c

516

if (!plane_state->pending.config)

drivers/gpu/drm/mediatek/mtk_crtc.c

523

plane_state,

drivers/gpu/drm/mediatek/mtk_crtc.c

526

plane_state->pending.config = false;

drivers/gpu/drm/mediatek/mtk_crtc.c

536

struct mtk_plane_state *plane_state;

drivers/gpu/drm/mediatek/mtk_crtc.c

538

plane_state = to_mtk_plane_state(plane->state);

drivers/gpu/drm/mediatek/mtk_crtc.c

540

if (!plane_state->pending.async_config)

drivers/gpu/drm/mediatek/mtk_crtc.c

547

plane_state,

drivers/gpu/drm/mediatek/mtk_crtc.c

550

plane_state->pending.async_config = false;

drivers/gpu/drm/mediatek/mtk_crtc.c

580

struct mtk_plane_state *plane_state;

drivers/gpu/drm/mediatek/mtk_crtc.c

582

plane_state = to_mtk_plane_state(plane->state);

drivers/gpu/drm/mediatek/mtk_crtc.c

583

if (plane_state->pending.dirty) {

drivers/gpu/drm/mediatek/mtk_crtc.c

584

plane_state->pending.config = true;

drivers/gpu/drm/mediatek/mtk_crtc.c

585

plane_state->pending.dirty = false;

drivers/gpu/drm/mediatek/mtk_crtc.c

587

} else if (plane_state->pending.async_dirty) {

drivers/gpu/drm/mediatek/mtk_crtc.c

588

plane_state->pending.async_config = true;

drivers/gpu/drm/mediatek/mtk_crtc.c

589

plane_state->pending.async_dirty = false;

drivers/gpu/drm/mediatek/mtk_crtc.c

737

struct mtk_plane_state *plane_state = to_mtk_plane_state(plane->state);

drivers/gpu/drm/mediatek/mtk_crtc.c

753

memcpy(mtk_plane_state, plane_state, sizeof(*plane_state));

drivers/gpu/drm/mediatek/mtk_crtc.c

820

struct mtk_plane_state *plane_state;

drivers/gpu/drm/mediatek/mtk_crtc.c

822

plane_state = to_mtk_plane_state(plane->state);

drivers/gpu/drm/mediatek/mtk_crtc.c

823

plane_state->pending.enable = false;

drivers/gpu/drm/mediatek/mtk_crtc.c

824

plane_state->pending.config = true;

drivers/gpu/drm/mediatek/mtk_crtc.h

26

struct drm_atomic_commit *plane_state);

drivers/gpu/drm/mgag200/mgag200_mode.c

505

struct drm_plane_state *plane_state = plane->state;

drivers/gpu/drm/mgag200/mgag200_mode.c

507

struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/mgag200/mgag200_mode.c

508

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/mgag200/mgag200_mode.c

513

drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1345

struct drm_plane_state *plane_state =

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1348

if (IS_ERR(plane_state)) {

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1349

ret = PTR_ERR(plane_state);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1353

states[plane_state->normalized_zpos] = plane_state;

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1175

struct drm_plane_state *plane_state =

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1182

if (IS_ERR(plane_state))

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1183

return PTR_ERR(plane_state);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1185

if (plane_state->crtc)

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1187

plane_state->crtc);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1189

ret = dpu_plane_atomic_check_nosspp(plane, plane_state, crtc_state);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1193

if (!plane_state->visible)

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1202

old_plane_state->src_w != plane_state->src_w ||

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1203

old_plane_state->src_h != plane_state->src_h ||

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1204

old_plane_state->crtc_w != plane_state->crtc_w ||

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1205

old_plane_state->crtc_h != plane_state->crtc_h ||

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1207

msm_framebuffer_format(plane_state->fb))

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1214

struct drm_plane_state *plane_state,

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1219

struct drm_plane *plane = plane_state->plane;

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1238

msm_framebuffer_format(plane_state->fb),

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1254

struct drm_plane_state *plane_state,

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1258

struct drm_plane *plane = plane_state->plane;

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1267

pstate = to_dpu_plane_state(plane_state);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1275

if (!plane_state->fb)

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1278

ret = dpu_plane_split(plane, plane_state, crtc_state);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1282

fmt = msm_framebuffer_format(plane_state->fb);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1284

reqs.scale = (plane_state->src_w >> 16 != plane_state->crtc_w) ||

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1285

(plane_state->src_h >> 16 != plane_state->crtc_h);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1287

reqs.rot90 = drm_rotation_90_or_270(plane_state->rotation);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1297

prev_adjacent_plane_state[i] = plane_state;

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1302

plane_state,

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1315

struct drm_plane_state *plane_state,

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1318

struct drm_plane *plane = plane_state->plane;

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1320

struct dpu_plane_state *pstate = to_dpu_plane_state(plane_state);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1332

ret = dpu_plane_split(plane, plane_state, crtc_state);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1338

msm_framebuffer_format(plane_state->fb),

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1363

struct drm_plane_state *plane_state = states[i];

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1365

if (!plane_state ||

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1366

!plane_state->visible)

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1369

if (plane_state->crtc)

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1371

plane_state->crtc);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1375

state, plane_state,

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1379

state, plane_state,

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

655

struct plane_state *pa = (struct plane_state *)a;

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

656

struct plane_state *pb = (struct plane_state *)b;

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

702

struct plane_state pstates[STAGE_MAX + 1];

drivers/gpu/drm/mxsfb/lcdif_kms.c

163

struct drm_plane_state *plane_state,

drivers/gpu/drm/mxsfb/lcdif_kms.c

167

const u32 format = plane_state->fb->format->format;

drivers/gpu/drm/mxsfb/lcdif_kms.c

278

lcdif_yuv2rgb_coeffs[plane_state->color_encoding]

drivers/gpu/drm/mxsfb/lcdif_kms.c

279

[plane_state->color_range];

drivers/gpu/drm/mxsfb/lcdif_kms.c

403

struct drm_plane_state *plane_state)

drivers/gpu/drm/mxsfb/lcdif_kms.c

419

lcdif_set_formats(lcdif, plane_state, lcdif_crtc_state->bus_format);

drivers/gpu/drm/mxsfb/lcdif_kms.c

669

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state,

drivers/gpu/drm/mxsfb/lcdif_kms.c

677

return drm_atomic_helper_check_plane_state(plane_state, crtc_state,

drivers/gpu/drm/mxsfb/mxsfb_kms.c

525

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state,

drivers/gpu/drm/mxsfb/mxsfb_kms.c

533

return drm_atomic_helper_check_plane_state(plane_state, crtc_state,

drivers/gpu/drm/omapdrm/omap_crtc.c

670

struct drm_plane_state *plane_state;

drivers/gpu/drm/omapdrm/omap_crtc.c

678

plane_state = drm_atomic_get_plane_state(state->state, crtc->primary);

drivers/gpu/drm/omapdrm/omap_crtc.c

679

if (IS_ERR(plane_state))

drivers/gpu/drm/omapdrm/omap_crtc.c

680

return PTR_ERR(plane_state);

drivers/gpu/drm/omapdrm/omap_crtc.c

683

plane_state->rotation = val;

drivers/gpu/drm/omapdrm/omap_crtc.c

685

plane_state->zpos = val;

drivers/gpu/drm/omapdrm/omap_drv.c

166

struct drm_plane_state *plane_state =

drivers/gpu/drm/omapdrm/omap_drv.c

169

if (IS_ERR(plane_state)) {

drivers/gpu/drm/omapdrm/omap_drv.c

170

ret = PTR_ERR(plane_state);

drivers/gpu/drm/omapdrm/omap_drv.c

173

states[n++] = plane_state;

drivers/gpu/drm/pl111/pl111_display.c

122

struct drm_plane_state *plane_state)

drivers/gpu/drm/qxl/qxl_display.c

514

struct drm_plane_state *plane_state)

drivers/gpu/drm/qxl/qxl_display.c

516

struct qxl_crtc *qcrtc = to_qxl_crtc(plane_state->crtc);

drivers/gpu/drm/qxl/qxl_display.c

540

cmd->u.set.position.x = plane_state->crtc_x + plane_state->hotspot_x;

drivers/gpu/drm/qxl/qxl_display.c

541

cmd->u.set.position.y = plane_state->crtc_y + plane_state->hotspot_y;

drivers/gpu/drm/qxl/qxl_display.c

559

struct drm_plane_state *plane_state)

drivers/gpu/drm/qxl/qxl_display.c

561

struct qxl_crtc *qcrtc = to_qxl_crtc(plane_state->crtc);

drivers/gpu/drm/qxl/qxl_display.c

583

cmd->u.position.x = plane_state->crtc_x + plane_state->hotspot_x;

drivers/gpu/drm/qxl/qxl_display.c

584

cmd->u.position.y = plane_state->crtc_y + plane_state->hotspot_y;

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1524

struct drm_plane_state *plane_state;

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1541

plane_state =

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1543

if (IS_ERR(plane_state)) {

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1546

return PTR_ERR(plane_state);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1549

if (drm_is_afbc(plane_state->fb->modifier))

drivers/gpu/drm/sitronix/st7571.c

346

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/sitronix/st7571.c

347

struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/sitronix/st7571.c

348

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/sitronix/st7571.c

365

drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state);

drivers/gpu/drm/sitronix/st7586.c

176

struct drm_plane_state *plane_state = plane->state;

drivers/gpu/drm/sitronix/st7586.c

177

struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/sitronix/st7586.c

178

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/sitronix/st7586.c

189

if (drm_atomic_helper_damage_merged(old_plane_state, plane_state, &rect))

drivers/gpu/drm/sitronix/st7920.c

345

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/sitronix/st7920.c

346

struct st7920_plane_state *st7920_state = to_st7920_plane_state(plane_state);

drivers/gpu/drm/sitronix/st7920.c

348

struct drm_crtc *crtc = plane_state->crtc;

drivers/gpu/drm/sitronix/st7920.c

357

ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state,

drivers/gpu/drm/sitronix/st7920.c

363

else if (!plane_state->visible)

drivers/gpu/drm/sitronix/st7920.c

372

if (plane_state->fb->format != fi) {

drivers/gpu/drm/sitronix/st7920.c

392

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/sitronix/st7920.c

394

struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/sitronix/st7920.c

395

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);

drivers/gpu/drm/sitronix/st7920.c

397

struct st7920_plane_state *st7920_plane_state = to_st7920_plane_state(plane_state);

drivers/gpu/drm/sitronix/st7920.c

398

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/sitronix/st7920.c

410

drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state);

drivers/gpu/drm/sitronix/st7920.c

412

dst_clip = plane_state->dst;

drivers/gpu/drm/sitronix/st7920.c

436

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/sitronix/st7920.c

441

if (!plane_state->crtc)

drivers/gpu/drm/sitronix/st7920.c

444

crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);

drivers/gpu/drm/solomon/ssd130x.c

1081

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/solomon/ssd130x.c

1082

struct ssd130x_plane_state *ssd130x_state = to_ssd130x_plane_state(plane_state);

drivers/gpu/drm/solomon/ssd130x.c

1084

struct drm_crtc *crtc = plane_state->crtc;

drivers/gpu/drm/solomon/ssd130x.c

1093

ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state,

drivers/gpu/drm/solomon/ssd130x.c

1099

else if (!plane_state->visible)

drivers/gpu/drm/solomon/ssd130x.c

1108

if (plane_state->fb->format != fi) {

drivers/gpu/drm/solomon/ssd130x.c

1130

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/solomon/ssd130x.c

1131

struct ssd130x_plane_state *ssd130x_state = to_ssd130x_plane_state(plane_state);

drivers/gpu/drm/solomon/ssd130x.c

1133

struct drm_crtc *crtc = plane_state->crtc;

drivers/gpu/drm/solomon/ssd130x.c

1142

ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state,

drivers/gpu/drm/solomon/ssd130x.c

1148

else if (!plane_state->visible)

drivers/gpu/drm/solomon/ssd130x.c

1157

if (plane_state->fb->format != fi) {

drivers/gpu/drm/solomon/ssd130x.c

1177

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/solomon/ssd130x.c

1178

struct drm_crtc *crtc = plane_state->crtc;

drivers/gpu/drm/solomon/ssd130x.c

1185

ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state,

drivers/gpu/drm/solomon/ssd130x.c

1191

else if (!plane_state->visible)

drivers/gpu/drm/solomon/ssd130x.c

1200

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/solomon/ssd130x.c

1202

struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/solomon/ssd130x.c

1203

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);

drivers/gpu/drm/solomon/ssd130x.c

1205

struct ssd130x_plane_state *ssd130x_plane_state = to_ssd130x_plane_state(plane_state);

drivers/gpu/drm/solomon/ssd130x.c

1206

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/solomon/ssd130x.c

1219

drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state);

drivers/gpu/drm/solomon/ssd130x.c

1221

dst_clip = plane_state->dst;

drivers/gpu/drm/solomon/ssd130x.c

1241

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/solomon/ssd130x.c

1243

struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/solomon/ssd130x.c

1244

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);

drivers/gpu/drm/solomon/ssd130x.c

1246

struct ssd130x_plane_state *ssd130x_plane_state = to_ssd130x_plane_state(plane_state);

drivers/gpu/drm/solomon/ssd130x.c

1247

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/solomon/ssd130x.c

1260

drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state);

drivers/gpu/drm/solomon/ssd130x.c

1262

dst_clip = plane_state->dst;

drivers/gpu/drm/solomon/ssd130x.c

1282

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/solomon/ssd130x.c

1284

struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/solomon/ssd130x.c

1285

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);

drivers/gpu/drm/solomon/ssd130x.c

1287

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/solomon/ssd130x.c

1300

drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state);

drivers/gpu/drm/solomon/ssd130x.c

1302

dst_clip = plane_state->dst;

drivers/gpu/drm/solomon/ssd130x.c

1323

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/solomon/ssd130x.c

1328

if (!plane_state->crtc)

drivers/gpu/drm/solomon/ssd130x.c

1331

crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);

drivers/gpu/drm/solomon/ssd130x.c

1347

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/solomon/ssd130x.c

1352

if (!plane_state->crtc)

drivers/gpu/drm/solomon/ssd130x.c

1355

crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);

drivers/gpu/drm/solomon/ssd130x.c

1371

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/solomon/ssd130x.c

1376

if (!plane_state->crtc)

drivers/gpu/drm/solomon/ssd130x.c

1379

crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);

drivers/gpu/drm/sprd/sprd_dpu.c

506

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state,

drivers/gpu/drm/sprd/sprd_dpu.c

511

if (!plane_state->fb || !plane_state->crtc)

drivers/gpu/drm/sprd/sprd_dpu.c

514

fmt = drm_format_to_dpu(plane_state->fb);

drivers/gpu/drm/sprd/sprd_dpu.c

518

crtc_state = drm_atomic_get_crtc_state(plane_state->state, plane_state->crtc);

drivers/gpu/drm/sprd/sprd_dpu.c

522

return drm_atomic_helper_check_plane_state(plane_state, crtc_state,

drivers/gpu/drm/sun4i/sun4i_backend.c

492

struct drm_plane_state *plane_state =

drivers/gpu/drm/sun4i/sun4i_backend.c

494

if (IS_ERR(plane_state))

drivers/gpu/drm/sun4i/sun4i_backend.c

495

return PTR_ERR(plane_state);

drivers/gpu/drm/sun4i/sun4i_backend.c

498

state_to_sun4i_layer_state(plane_state);

drivers/gpu/drm/sun4i/sun4i_backend.c

499

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/sun4i/sun4i_backend.c

501

if (!sun4i_backend_plane_is_supported(plane_state,

drivers/gpu/drm/sun4i/sun4i_backend.c

518

if (fb->format->has_alpha || (plane_state->alpha != DRM_BLEND_ALPHA_OPAQUE))

drivers/gpu/drm/sun4i/sun4i_backend.c

522

plane_state->normalized_zpos);

drivers/gpu/drm/sun4i/sun4i_backend.c

525

plane_states[plane_state->normalized_zpos] = plane_state;

drivers/gpu/drm/sun4i/sun8i_mixer.c

261

struct drm_plane_state *plane_state;

drivers/gpu/drm/sun4i/sun8i_mixer.c

275

plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/sun4i/sun8i_mixer.c

276

if (!plane_state)

drivers/gpu/drm/sun4i/sun8i_mixer.c

277

plane_state = plane->state;

drivers/gpu/drm/sun4i/sun8i_mixer.c

279

enable = plane_state->crtc && plane_state->visible;

drivers/gpu/drm/sun4i/sun8i_mixer.c

280

zpos = plane_state->normalized_zpos;

drivers/gpu/drm/sun4i/sun8i_mixer.c

281

x = plane_state->dst.x1;

drivers/gpu/drm/sun4i/sun8i_mixer.c

282

y = plane_state->dst.y1;

drivers/gpu/drm/sun4i/sun8i_mixer.c

283

w = drm_rect_width(&plane_state->dst);

drivers/gpu/drm/sun4i/sun8i_mixer.c

284

h = drm_rect_height(&plane_state->dst);

drivers/gpu/drm/sysfb/drm_sysfb_helper.h

112

struct drm_plane_state *plane_state);

drivers/gpu/drm/sysfb/drm_sysfb_helper.h

140

struct drm_plane_state *plane_state);

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

242

struct drm_plane_state *plane_state)

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

245

struct drm_sysfb_plane_state *sysfb_plane_state = to_drm_sysfb_plane_state(plane_state);

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

246

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

252

ret = drm_gem_begin_shadow_fb_access(plane, plane_state);

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

261

crtc_state = drm_atomic_get_new_crtc_state(plane_state->state, plane_state->crtc);

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

280

drm_gem_end_shadow_fb_access(plane, plane_state);

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

333

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

335

struct drm_sysfb_plane_state *sysfb_plane_state = to_drm_sysfb_plane_state(plane_state);

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

337

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

339

struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

354

drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state);

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

357

struct drm_rect dst_clip = plane_state->dst;

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

379

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

388

plane_state->src_x >> 16, plane_state->src_y >> 16,

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

389

plane_state->src_w >> 16, plane_state->src_h >> 16);

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

441

struct drm_plane_state *plane_state = plane->state;

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

446

if (drm_WARN_ON(dev, !plane_state))

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

448

sysfb_plane_state = to_drm_sysfb_plane_state(plane_state);

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

463

struct drm_plane_state *plane_state)

drivers/gpu/drm/sysfb/drm_sysfb_modeset.c

465

drm_sysfb_plane_state_destroy(to_drm_sysfb_plane_state(plane_state));

drivers/gpu/drm/tegra/dc.c

2450

const struct drm_plane_state *plane_state)

drivers/gpu/drm/tegra/dc.c

2458

if (!plane_state->visible || !plane_state->fb)

drivers/gpu/drm/tegra/dc.c

2465

if (tegra_plane_is_cursor(plane_state))

drivers/gpu/drm/tegra/dc.c

2469

rect = plane_state->dst;

drivers/gpu/drm/tegra/dc.c

2498

const struct drm_plane_state *plane_state;

drivers/gpu/drm/tegra/dc.c

2526

drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, new_state) {

drivers/gpu/drm/tegra/dc.c

2527

tegra_state = to_const_tegra_plane_state(plane_state);

drivers/gpu/drm/tegra/dc.c

2534

mask = tegra_plane_overlap_mask(new_state, plane_state);

drivers/gpu/drm/tegra/dc.c

2556

drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, new_state) {

drivers/gpu/drm/tegra/dc.c

2565

tegra_state = to_const_tegra_plane_state(plane_state);

drivers/gpu/drm/tegra/dc.c

722

struct tegra_plane_state *plane_state = to_tegra_plane_state(new_plane_state);

drivers/gpu/drm/tegra/dc.c

727

struct tegra_bo_tiling *tiling = &plane_state->tiling;

drivers/gpu/drm/tegra/dc.c

732

plane_state->peak_memory_bandwidth = 0;

drivers/gpu/drm/tegra/dc.c

733

plane_state->avg_memory_bandwidth = 0;

drivers/gpu/drm/tegra/dc.c

737

plane_state->total_peak_memory_bandwidth = 0;

drivers/gpu/drm/tegra/dc.c

742

&plane_state->format,

drivers/gpu/drm/tegra/dc.c

743

&plane_state->swap);

drivers/gpu/drm/tegra/dc.c

754

err = tegra_plane_setup_legacy_state(tegra, plane_state);

drivers/gpu/drm/tegra/dc.c

781

plane_state->reflect_x = true;

drivers/gpu/drm/tegra/dc.c

783

plane_state->reflect_x = false;

drivers/gpu/drm/tegra/dc.c

786

plane_state->reflect_y = true;

drivers/gpu/drm/tegra/dc.c

788

plane_state->reflect_y = false;

drivers/gpu/drm/tegra/dc.c

970

struct tegra_plane_state *plane_state = to_tegra_plane_state(new_plane_state);

drivers/gpu/drm/tegra/dc.c

974

plane_state->peak_memory_bandwidth = 0;

drivers/gpu/drm/tegra/dc.c

975

plane_state->avg_memory_bandwidth = 0;

drivers/gpu/drm/tegra/dc.c

979

plane_state->total_peak_memory_bandwidth = 0;

drivers/gpu/drm/tegra/hub.c

431

struct tegra_plane_state *plane_state = to_tegra_plane_state(new_plane_state);

drivers/gpu/drm/tegra/hub.c

433

struct tegra_bo_tiling *tiling = &plane_state->tiling;

drivers/gpu/drm/tegra/hub.c

442

&plane_state->format,

drivers/gpu/drm/tegra/hub.c

443

&plane_state->swap);

drivers/gpu/drm/tegra/plane.c

620

struct drm_plane_state *old, *plane_state;

drivers/gpu/drm/tegra/plane.c

638

plane_state = drm_atomic_get_plane_state(state->base.state,

drivers/gpu/drm/tegra/plane.c

640

if (IS_ERR(plane_state))

drivers/gpu/drm/tegra/plane.c

641

return PTR_ERR(plane_state);

drivers/gpu/drm/tests/drm_plane_helper_test.c

101

static void check_crtc_eq(struct kunit *test, struct drm_plane_state *plane_state,

drivers/gpu/drm/tests/drm_plane_helper_test.c

107

KUNIT_EXPECT_TRUE_MSG(test, drm_rect_equals(&plane_state->dst, &expected),

drivers/gpu/drm/tests/drm_plane_helper_test.c

109

DRM_RECT_ARG(&plane_state->dst), DRM_RECT_ARG(&expected));

drivers/gpu/drm/tests/drm_plane_helper_test.c

115

struct drm_plane_state *plane_state = test->priv;

drivers/gpu/drm/tests/drm_plane_helper_test.c

118

drm_atomic_helper_check_plane_state(plane_state, &crtc_state,

drivers/gpu/drm/tests/drm_plane_helper_test.c

123

KUNIT_EXPECT_TRUE(test, plane_state->visible);

drivers/gpu/drm/tests/drm_plane_helper_test.c

124

check_src_eq(test, plane_state, params->src_expected.x, params->src_expected.y,

drivers/gpu/drm/tests/drm_plane_helper_test.c

126

check_crtc_eq(test, plane_state, params->crtc_expected.x, params->crtc_expected.y,

drivers/gpu/drm/tests/drm_plane_helper_test.c

257

struct drm_plane_state *plane_state = test->priv;

drivers/gpu/drm/tests/drm_plane_helper_test.c

260

drm_atomic_helper_check_plane_state(plane_state, &crtc_state,

drivers/gpu/drm/tests/drm_plane_helper_test.c

82

static void check_src_eq(struct kunit *test, struct drm_plane_state *plane_state,

drivers/gpu/drm/tests/drm_plane_helper_test.c

88

KUNIT_ASSERT_GE_MSG(test, plane_state->src.x1, 0,

drivers/gpu/drm/tests/drm_plane_helper_test.c

90

plane_state->src.x1, DRM_RECT_FP_ARG(&plane_state->src));

drivers/gpu/drm/tests/drm_plane_helper_test.c

92

KUNIT_ASSERT_GE_MSG(test, plane_state->src.y1, 0,

drivers/gpu/drm/tests/drm_plane_helper_test.c

94

plane_state->src.y1, DRM_RECT_FP_ARG(&plane_state->src));

drivers/gpu/drm/tests/drm_plane_helper_test.c

96

KUNIT_EXPECT_TRUE_MSG(test, drm_rect_equals(&plane_state->src, &expected),

drivers/gpu/drm/tests/drm_plane_helper_test.c

98

DRM_RECT_FP_ARG(&plane_state->src), DRM_RECT_FP_ARG(&expected));

drivers/gpu/drm/tiny/appletbdrm.c

481

struct drm_plane_state *plane_state = plane->state;

drivers/gpu/drm/tiny/appletbdrm.c

488

appletbdrm_flush_damage(adev, old_plane_state, plane_state);

drivers/gpu/drm/tiny/arcpgu.c

199

struct drm_plane_state *plane_state)

drivers/gpu/drm/tiny/bochs.c

449

struct drm_plane_state *plane_state = plane->state;

drivers/gpu/drm/tiny/bochs.c

451

struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/tiny/bochs.c

452

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/tiny/bochs.c

459

drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state);

drivers/gpu/drm/tiny/bochs.c

469

plane_state->crtc_x,

drivers/gpu/drm/tiny/bochs.c

470

plane_state->crtc_y,

drivers/gpu/drm/tiny/cirrus-qemu.c

332

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/tiny/cirrus-qemu.c

333

struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/tiny/cirrus-qemu.c

334

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/tiny/cirrus-qemu.c

353

drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state);

drivers/gpu/drm/tiny/gm12u320.c

561

struct drm_plane_state *plane_state)

drivers/gpu/drm/tiny/gm12u320.c

565

struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/tiny/gm12u320.c

568

gm12u320_fb_mark_dirty(plane_state->fb, &shadow_plane_state->data[0], &rect);

drivers/gpu/drm/tiny/ili9225.c

185

struct drm_plane_state *plane_state = plane->state;

drivers/gpu/drm/tiny/ili9225.c

186

struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/tiny/ili9225.c

187

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/tiny/ili9225.c

192

if (!plane_state->fb)

drivers/gpu/drm/tiny/ili9225.c

198

if (drm_atomic_helper_damage_merged(old_plane_state, plane_state, &rect))

drivers/gpu/drm/tiny/pixpaper.c

863

struct drm_plane_state *plane_state =

drivers/gpu/drm/tiny/pixpaper.c

866

to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/tiny/pixpaper.c

867

struct drm_crtc *crtc = plane_state->crtc;

drivers/gpu/drm/tiny/pixpaper.c

871

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/tiny/pixpaper.c

884

if (!fb || !plane_state->visible) {

drivers/gpu/drm/tiny/repaper.c

636

struct drm_plane_state *plane_state)

drivers/gpu/drm/tiny/sharp-memory.c

227

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/tiny/sharp-memory.c

234

return drm_atomic_helper_check_plane_state(plane_state, crtc_state,

drivers/gpu/drm/tiny/sharp-memory.c

244

struct drm_plane_state *plane_state = plane->state;

drivers/gpu/drm/tiny/sharp-memory.c

245

struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/tiny/sharp-memory.c

253

if (drm_atomic_helper_damage_merged(old_state, plane_state, &rect))

drivers/gpu/drm/tiny/sharp-memory.c

254

sharp_memory_fb_dirty(plane_state->fb, shadow_plane_state->data,

drivers/gpu/drm/tve200/tve200_display.c

124

struct drm_plane_state *plane_state)

drivers/gpu/drm/udl/udl_modeset.c

286

struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/udl/udl_modeset.c

287

struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);

drivers/gpu/drm/udl/udl_modeset.c

288

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/udl/udl_modeset.c

304

drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state);

drivers/gpu/drm/vc4/vc4_hvs.c

798

const struct drm_plane_state *plane_state;

drivers/gpu/drm/vc4/vc4_hvs.c

808

drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {

drivers/gpu/drm/vc4/vc4_hvs.c

809

u32 plane_dlist_count = vc4_plane_dlist_size(plane_state);

drivers/gpu/drm/vkms/vkms_composer.c

193

static void pre_blend_color_transform(const struct vkms_plane_state *plane_state,

drivers/gpu/drm/vkms/vkms_composer.c

199

struct drm_colorop *colorop = plane_state->base.base.color_pipeline;

drivers/gpu/drm/vkms/vkms_composer.c

532

struct vkms_plane_state **plane_state = crtc_state->active_planes;

drivers/gpu/drm/vkms/vkms_composer.c

536

if (iosys_map_is_null(&plane_state[i]->frame_info->map[0]))

drivers/gpu/drm/vkms/vkms_crtc.c

120

struct drm_plane_state *plane_state;

drivers/gpu/drm/vkms/vkms_crtc.c

131

plane_state = drm_atomic_get_new_plane_state(crtc_state->state, plane);

drivers/gpu/drm/vkms/vkms_crtc.c

132

WARN_ON(!plane_state);

drivers/gpu/drm/vkms/vkms_crtc.c

134

if (!plane_state->visible)

drivers/gpu/drm/vkms/vkms_crtc.c

147

plane_state = drm_atomic_get_new_plane_state(crtc_state->state, plane);

drivers/gpu/drm/vkms/vkms_crtc.c

149

if (!plane_state->visible)

drivers/gpu/drm/vkms/vkms_crtc.c

153

to_vkms_plane_state(plane_state);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

903

struct drm_plane_state *plane_state;

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

922

plane_state = du->primary.state;

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

923

if (plane_state->crtc != crtc)

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

927

implicit_fb = plane_state->fb;

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

928

else if (implicit_fb != plane_state->fb)

drivers/gpu/drm/xe/display/xe_initial_plane.c

139

struct intel_plane_state *plane_state = to_intel_plane_state(_plane_state);

drivers/gpu/drm/xe/display/xe_initial_plane.c

142

.view = &plane_state->view.gtt,

drivers/gpu/drm/xe/display/xe_initial_plane.c

151

plane_state->ggtt_vma = vma;

drivers/gpu/drm/xe/display/xe_initial_plane.c

153

plane_state->surf = offset;

drivers/gpu/drm/xen/xen_drm_front_kms.c

110

struct drm_plane_state *plane_state)

drivers/gpu/drm/xen/xen_drm_front_kms.c

115

struct drm_framebuffer *fb = plane_state->fb;

drivers/gpu/drm/xen/xen_drm_front_kms.c

183

struct drm_plane_state *plane_state =

drivers/gpu/drm/xen/xen_drm_front_kms.c

195

if (old_plane_state->fb && plane_state->fb) {

drivers/gpu/drm/xen/xen_drm_front_kms.c

206

xen_drm_front_fb_to_cookie(plane_state->fb));

drivers/gpu/drm/xen/xen_drm_front_kms.c

228

struct drm_plane_state *plane_state,

include/drm/drm_atomic.h

900

struct drm_plane_state *plane_state;

include/drm/drm_atomic.h

902

plane_state = drm_atomic_get_new_plane_state(state, plane);

include/drm/drm_atomic.h

903

if (plane_state)

include/drm/drm_atomic.h

904

return plane_state;

include/drm/drm_atomic_helper.h

231

#define drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) \

include/drm/drm_atomic_helper.h

233

for_each_if ((plane_state = \

include/drm/drm_atomic_helper.h

54

int drm_atomic_helper_check_plane_state(struct drm_plane_state *plane_state,

include/drm/drm_atomic_uapi.h

51

drm_atomic_set_crtc_for_plane(struct drm_plane_state *plane_state,

include/drm/drm_atomic_uapi.h

53

void drm_atomic_set_fb_for_plane(struct drm_plane_state *plane_state,

include/drm/drm_atomic_uapi.h

55

bool drm_atomic_set_colorop_for_plane(struct drm_plane_state *plane_state,

include/drm/drm_damage_helper.h

68

struct drm_plane_state *plane_state);

include/drm/drm_gem_atomic_helper.h

100

struct drm_plane_state *plane_state);

include/drm/drm_gem_atomic_helper.h

114

int drm_gem_begin_shadow_fb_access(struct drm_plane *plane, struct drm_plane_state *plane_state);

include/drm/drm_gem_atomic_helper.h

115

void drm_gem_end_shadow_fb_access(struct drm_plane *plane, struct drm_plane_state *plane_state);

include/drm/drm_gem_atomic_helper.h

130

struct drm_plane_state *plane_state);

include/drm/drm_gem_atomic_helper.h

132

struct drm_plane_state *plane_state);

include/drm/drm_gem_atomic_helper.h

137

struct drm_plane_state *plane_state);

include/drm/drm_simple_kms_helper.h

25

struct drm_plane_state *plane_state);

include/drm/drm_simple_kms_helper.h

28

struct drm_plane_state *plane_state,

include/drm/drm_simple_kms_helper.h

33

struct drm_plane_state *plane_state);

include/drm/drm_simple_kms_helper.h

35

struct drm_plane_state *plane_state);

include/drm/drm_simple_kms_helper.h

39

struct drm_plane_state *plane_state);

include/drm/drm_simple_kms_helper.h

49

struct drm_plane_state *plane_state);

include/drm/intel/display_parent_interface.h

129

int (*setup)(struct drm_plane_state *plane_state, struct intel_initial_plane_config *plane_config,