drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5615

struct amdgpu_mode_info *mode_info, int plane_id,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5636

possible_crtcs = 1 << plane_id;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5637

if (plane_id >= dm->dc->caps.max_streams)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5649

mode_info->planes[plane_id] = plane;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

229

__field(uint32_t, plane_id)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

258

__entry->plane_id = state->plane->base.id;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

293

__entry->plane_id, __entry->plane_type, __entry->plane_state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

709

static bool dml21_wrapper_get_plane_id(const struct dc_state *context, unsigned int stream_id, const struct dc_plane_state *plane, unsigned int *plane_id)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

713

if (!plane_id)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

720

*plane_id = (i << 16) | j;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

748

unsigned int plane_id;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

752

if (!dml21_wrapper_get_plane_id(context, stream_id, plane, &plane_id)) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

758

if (dml_ctx->v21.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid[i] && dml_ctx->v21.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id[i] == plane_id) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

25

int dml21_find_dml_pipe_idx_by_plane_id(struct dml2_context *ctx, unsigned int plane_id)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

29

if (ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id_valid[i] && ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id[i] == plane_id)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

36

bool dml21_get_plane_id(const struct dc_state *state, const struct dc_plane_state *plane, unsigned int *plane_id)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

40

if (!plane_id)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

46

*plane_id = (i << 16) | j;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

55

unsigned int dml21_get_dc_plane_idx_from_plane_id(unsigned int plane_id)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

57

return 0xffff & plane_id;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h

20

int dml21_find_dml_pipe_idx_by_plane_id(struct dml2_context *ctx, unsigned int plane_id);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h

21

bool dml21_get_plane_id(const struct dc_state *state, const struct dc_plane_state *plane, unsigned int *plane_id);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h

46

unsigned int dml21_get_dc_plane_idx_from_plane_id(unsigned int plane_id);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1058

unsigned int plane_id;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1135

stream_id, plane_index, &plane_id)) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1136

plane_disp_cfg_index = find_disp_cfg_idx_by_plane_id(mapping, plane_id);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

124

struct dc_state *state, unsigned int plane_id)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

133

if (plane_id_assigned_to_pipe == plane_id)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

142

struct dc_state *state, unsigned int plane_id, unsigned int *pipes)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

157

if (plane_id_assigned_to_pipe == plane_id && !pipe->prev_odm_pipe

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

59

unsigned int stream_id, unsigned int plane_index, unsigned int *plane_id)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

64

if (!plane_id)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

661

unsigned int plane_id;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

668

if (!get_plane_id(ctx, state, plane, stream->stream_id, plane_index, &plane_id)) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

675

master_pipe = find_master_pipe_of_plane(ctx, state, plane_id);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

678

pipes_assigned = find_pipes_assigned_to_plane(ctx, state, plane_id, pipes);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

72

*plane_id = (i << 16) | j;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

773

unsigned int plane_id;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

777

if (!get_plane_id(ctx, state, plane, stream->stream_id, plane_index, &plane_id)) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

814

unsigned int plane_id;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

82

static int find_disp_cfg_idx_by_plane_id(struct dml2_dml_to_dc_pipe_mapping *mapping, unsigned int plane_id)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

820

stream->stream_id, plane_idx, &plane_id);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

821

cfg_idx = find_disp_cfg_idx_by_plane_id(mapping, plane_id);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

843

main_stream->stream_id, plane_idx, &plane_id);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

846

stream->stream_id, plane_idx, &plane_id);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

849

cfg_idx = find_disp_cfg_idx_by_plane_id(mapping, plane_id);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

87

if (mapping->disp_cfg_to_plane_id_valid[i] && mapping->disp_cfg_to_plane_id[i] == plane_id)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1159

unsigned int stream_id, unsigned int plane_index, unsigned int *plane_id)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1164

if (!plane_id)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1172

*plane_id = (i << 16) | j;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1186

unsigned int plane_id;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1190

if (!get_plane_id(context->bw_ctx.dml2, context, plane, stream_id, plane_index, &plane_id)) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1196

if (dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid[i] && dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id[i] == plane_id) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

207

static int find_dml_pipe_idx_by_plane_id(struct dml2_context *ctx, unsigned int plane_id)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

211

if (ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id_valid[i] && ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id[i] == plane_id)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

219

unsigned int stream_id, unsigned int plane_index, unsigned int *plane_id)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

224

if (!plane_id)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

232

*plane_id = (i << 16) | j;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

284

unsigned int dc_pipe_ctx_index, dml_pipe_idx, plane_id;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

310

in_ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[context->res_ctx.pipe_ctx[dc_pipe_ctx_index].pipe_idx], &plane_id)) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

311

dml_pipe_idx = find_dml_pipe_idx_by_plane_id(in_ctx, plane_id);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

517

unsigned int i = 0, dml_pipe_idx = 0, plane_id = 0;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

528

in_ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[display_state->res_ctx.pipe_ctx[i].pipe_idx], &plane_id))

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

529

dml_pipe_idx = find_dml_pipe_idx_by_plane_id(in_ctx, plane_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1054

int plane_id)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1059

hws->funcs.dpp_root_clock_control(hws, plane_id, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1066

hws->funcs.dpp_pg_control(hws, plane_id, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1069

hws->funcs.hubp_pg_control(hws, plane_id, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1074

"Un-gated front end for pipe %d\n", plane_id);

drivers/gpu/drm/drm_plane.c

1151

plane = drm_plane_find(dev, file_priv, plane_req->plane_id);

drivers/gpu/drm/drm_plane.c

1154

plane_req->plane_id);

drivers/gpu/drm/drm_plane.c

863

plane = drm_plane_find(dev, file_priv, plane_resp->plane_id);

drivers/gpu/drm/drm_plane.c

883

plane_resp->plane_id = plane->base.id;

drivers/gpu/drm/i915/display/i9xx_wm.c

1025

int level, enum plane_id plane_id, u16 value)

drivers/gpu/drm/i915/display/i9xx_wm.c

1033

dirty |= raw->plane[plane_id] != value;

drivers/gpu/drm/i915/display/i9xx_wm.c

1034

raw->plane[plane_id] = value;

drivers/gpu/drm/i915/display/i9xx_wm.c

1068

enum plane_id plane_id = plane->id;

drivers/gpu/drm/i915/display/i9xx_wm.c

1073

dirty |= g4x_raw_plane_wm_set(crtc_state, 0, plane_id, 0);

drivers/gpu/drm/i915/display/i9xx_wm.c

1074

if (plane_id == PLANE_PRIMARY)

drivers/gpu/drm/i915/display/i9xx_wm.c

1084

max_wm = g4x_plane_fifo_size(plane_id, level);

drivers/gpu/drm/i915/display/i9xx_wm.c

1089

dirty |= raw->plane[plane_id] != wm;

drivers/gpu/drm/i915/display/i9xx_wm.c

1090

raw->plane[plane_id] = wm;

drivers/gpu/drm/i915/display/i9xx_wm.c

1092

if (plane_id != PLANE_PRIMARY ||

drivers/gpu/drm/i915/display/i9xx_wm.c

1097

raw->plane[plane_id]);

drivers/gpu/drm/i915/display/i9xx_wm.c

1112

dirty |= g4x_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);

drivers/gpu/drm/i915/display/i9xx_wm.c

1114

if (plane_id == PLANE_PRIMARY)

drivers/gpu/drm/i915/display/i9xx_wm.c

1122

crtc_state->wm.g4x.raw[G4X_WM_LEVEL_NORMAL].plane[plane_id],

drivers/gpu/drm/i915/display/i9xx_wm.c

1123

crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].plane[plane_id],

drivers/gpu/drm/i915/display/i9xx_wm.c

1124

crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]);

drivers/gpu/drm/i915/display/i9xx_wm.c

1126

if (plane_id == PLANE_PRIMARY)

drivers/gpu/drm/i915/display/i9xx_wm.c

1137

enum plane_id plane_id, int level)

drivers/gpu/drm/i915/display/i9xx_wm.c

1141

return raw->plane[plane_id] <= g4x_plane_fifo_size(plane_id, level);

drivers/gpu/drm/i915/display/i9xx_wm.c

1162

enum plane_id plane_id;

drivers/gpu/drm/i915/display/i9xx_wm.c

1164

for_each_plane_id_on_crtc(crtc, plane_id)

drivers/gpu/drm/i915/display/i9xx_wm.c

1165

wm_state->wm.plane[plane_id] = USHRT_MAX;

drivers/gpu/drm/i915/display/i9xx_wm.c

1206

enum plane_id plane_id;

drivers/gpu/drm/i915/display/i9xx_wm.c

1214

for_each_plane_id_on_crtc(crtc, plane_id)

drivers/gpu/drm/i915/display/i9xx_wm.c

1215

wm_state->wm.plane[plane_id] = raw->plane[plane_id];

drivers/gpu/drm/i915/display/i9xx_wm.c

1299

enum plane_id plane_id;

drivers/gpu/drm/i915/display/i9xx_wm.c

1316

for_each_plane_id_on_crtc(crtc, plane_id) {

drivers/gpu/drm/i915/display/i9xx_wm.c

1317

intermediate->wm.plane[plane_id] =

drivers/gpu/drm/i915/display/i9xx_wm.c

1318

max(optimal->wm.plane[plane_id],

drivers/gpu/drm/i915/display/i9xx_wm.c

1319

active->wm.plane[plane_id]);

drivers/gpu/drm/i915/display/i9xx_wm.c

1321

drm_WARN_ON(display->drm, intermediate->wm.plane[plane_id] >

drivers/gpu/drm/i915/display/i9xx_wm.c

1322

g4x_plane_fifo_size(plane_id, G4X_WM_LEVEL_NORMAL));

drivers/gpu/drm/i915/display/i9xx_wm.c

1567

enum plane_id plane_id;

drivers/gpu/drm/i915/display/i9xx_wm.c

1591

for_each_plane_id_on_crtc(crtc, plane_id) {

drivers/gpu/drm/i915/display/i9xx_wm.c

1594

if ((active_planes & BIT(plane_id)) == 0) {

drivers/gpu/drm/i915/display/i9xx_wm.c

1595

fifo_state->plane[plane_id] = 0;

drivers/gpu/drm/i915/display/i9xx_wm.c

1599

rate = raw->plane[plane_id];

drivers/gpu/drm/i915/display/i9xx_wm.c

1600

fifo_state->plane[plane_id] = fifo_size * rate / total_rate;

drivers/gpu/drm/i915/display/i9xx_wm.c

1601

fifo_left -= fifo_state->plane[plane_id];

drivers/gpu/drm/i915/display/i9xx_wm.c

1612

for_each_plane_id_on_crtc(crtc, plane_id) {

drivers/gpu/drm/i915/display/i9xx_wm.c

1618

if ((active_planes & BIT(plane_id)) == 0)

drivers/gpu/drm/i915/display/i9xx_wm.c

1622

fifo_state->plane[plane_id] += plane_extra;

drivers/gpu/drm/i915/display/i9xx_wm.c

1644

enum plane_id plane_id;

drivers/gpu/drm/i915/display/i9xx_wm.c

1646

for_each_plane_id_on_crtc(crtc, plane_id)

drivers/gpu/drm/i915/display/i9xx_wm.c

1647

wm_state->wm[level].plane[plane_id] = USHRT_MAX;

drivers/gpu/drm/i915/display/i9xx_wm.c

1667

int level, enum plane_id plane_id, u16 value)

drivers/gpu/drm/i915/display/i9xx_wm.c

1675

dirty |= raw->plane[plane_id] != value;

drivers/gpu/drm/i915/display/i9xx_wm.c

1676

raw->plane[plane_id] = value;

drivers/gpu/drm/i915/display/i9xx_wm.c

1687

enum plane_id plane_id = plane->id;

drivers/gpu/drm/i915/display/i9xx_wm.c

1692

dirty |= vlv_raw_plane_wm_set(crtc_state, 0, plane_id, 0);

drivers/gpu/drm/i915/display/i9xx_wm.c

1699

int max_wm = plane_id == PLANE_CURSOR ? 63 : 511;

drivers/gpu/drm/i915/display/i9xx_wm.c

1704

dirty |= raw->plane[plane_id] != wm;

drivers/gpu/drm/i915/display/i9xx_wm.c

1705

raw->plane[plane_id] = wm;

drivers/gpu/drm/i915/display/i9xx_wm.c

1709

dirty |= vlv_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);

drivers/gpu/drm/i915/display/i9xx_wm.c

1716

crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id],

drivers/gpu/drm/i915/display/i9xx_wm.c

1717

crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id],

drivers/gpu/drm/i915/display/i9xx_wm.c

1718

crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]);

drivers/gpu/drm/i915/display/i9xx_wm.c

1724

enum plane_id plane_id, int level)

drivers/gpu/drm/i915/display/i9xx_wm.c

1731

return raw->plane[plane_id] <= fifo_state->plane[plane_id];

drivers/gpu/drm/i915/display/i9xx_wm.c

1751

enum plane_id plane_id;

drivers/gpu/drm/i915/display/i9xx_wm.c

1770

for_each_plane_id_on_crtc(crtc, plane_id) {

drivers/gpu/drm/i915/display/i9xx_wm.c

1771

wm_state->wm[level].plane[plane_id] =

drivers/gpu/drm/i915/display/i9xx_wm.c

1772

vlv_invert_wm_value(raw->plane[plane_id],

drivers/gpu/drm/i915/display/i9xx_wm.c

1773

fifo_state->plane[plane_id]);

drivers/gpu/drm/i915/display/i9xx_wm.c

1985

enum plane_id plane_id;

drivers/gpu/drm/i915/display/i9xx_wm.c

1987

for_each_plane_id_on_crtc(crtc, plane_id) {

drivers/gpu/drm/i915/display/i9xx_wm.c

1988

intermediate->wm[level].plane[plane_id] =

drivers/gpu/drm/i915/display/i9xx_wm.c

1989

min(optimal->wm[level].plane[plane_id],

drivers/gpu/drm/i915/display/i9xx_wm.c

1990

active->wm[level].plane[plane_id]);

drivers/gpu/drm/i915/display/i9xx_wm.c

3778

enum plane_id plane_id;

drivers/gpu/drm/i915/display/i9xx_wm.c

3788

for_each_plane_id_on_crtc(crtc, plane_id) {

drivers/gpu/drm/i915/display/i9xx_wm.c

3789

active->wm.plane[plane_id] =

drivers/gpu/drm/i915/display/i9xx_wm.c

3790

wm->pipe[pipe].plane[plane_id];

drivers/gpu/drm/i915/display/i9xx_wm.c

3802

for_each_plane_id_on_crtc(crtc, plane_id)

drivers/gpu/drm/i915/display/i9xx_wm.c

3803

raw->plane[plane_id] = active->wm.plane[plane_id];

drivers/gpu/drm/i915/display/i9xx_wm.c

3827

for_each_plane_id_on_crtc(crtc, plane_id)

drivers/gpu/drm/i915/display/i9xx_wm.c

3829

plane_id, USHRT_MAX);

drivers/gpu/drm/i915/display/i9xx_wm.c

3870

enum plane_id plane_id = plane->id;

drivers/gpu/drm/i915/display/i9xx_wm.c

3880

raw->plane[plane_id] = 0;

drivers/gpu/drm/i915/display/i9xx_wm.c

3882

if (plane_id == PLANE_PRIMARY)

drivers/gpu/drm/i915/display/i9xx_wm.c

3961

enum plane_id plane_id;

drivers/gpu/drm/i915/display/i9xx_wm.c

3976

for_each_plane_id_on_crtc(crtc, plane_id) {

drivers/gpu/drm/i915/display/i9xx_wm.c

3977

active->wm[level].plane[plane_id] =

drivers/gpu/drm/i915/display/i9xx_wm.c

3978

wm->pipe[pipe].plane[plane_id];

drivers/gpu/drm/i915/display/i9xx_wm.c

3980

raw->plane[plane_id] =

drivers/gpu/drm/i915/display/i9xx_wm.c

3981

vlv_invert_wm_value(active->wm[level].plane[plane_id],

drivers/gpu/drm/i915/display/i9xx_wm.c

3982

fifo_state->plane[plane_id]);

drivers/gpu/drm/i915/display/i9xx_wm.c

3986

for_each_plane_id_on_crtc(crtc, plane_id)

drivers/gpu/drm/i915/display/i9xx_wm.c

3988

plane_id, USHRT_MAX);

drivers/gpu/drm/i915/display/i9xx_wm.c

4022

enum plane_id plane_id = plane->id;

drivers/gpu/drm/i915/display/i9xx_wm.c

4032

raw->plane[plane_id] = 0;

drivers/gpu/drm/i915/display/i9xx_wm.c

926

static int g4x_plane_fifo_size(enum plane_id plane_id, int level)

drivers/gpu/drm/i915/display/i9xx_wm.c

942

switch (plane_id) {

drivers/gpu/drm/i915/display/i9xx_wm.c

950

MISSING_CASE(plane_id);

drivers/gpu/drm/i915/display/intel_color.c

3873

enum plane_id plane = to_intel_plane(state->plane)->id;

drivers/gpu/drm/i915/display/intel_color.c

3968

enum plane_id plane = to_intel_plane(state->plane)->id;

drivers/gpu/drm/i915/display/intel_color.c

4021

enum plane_id plane = to_intel_plane(state->plane)->id;

drivers/gpu/drm/i915/display/intel_crtc.c

876

enum plane_id plane_id;

drivers/gpu/drm/i915/display/intel_crtc.c

878

for_each_plane_id_on_crtc(crtc, plane_id) {

drivers/gpu/drm/i915/display/intel_crtc.c

883

if (plane_id == PLANE_CURSOR)

drivers/gpu/drm/i915/display/intel_crtc.c

886

data_rate += crtc_state->data_rate[plane_id];

drivers/gpu/drm/i915/display/intel_crtc.c

889

data_rate += crtc_state->data_rate_y[plane_id];

drivers/gpu/drm/i915/display/intel_cursor.c

621

enum plane_id plane_id = plane->id;

drivers/gpu/drm/i915/display/intel_cursor.c

625

&crtc_state->wm.skl.plane_ddb[plane_id];

drivers/gpu/drm/i915/display/intel_cursor.c

630

skl_cursor_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));

drivers/gpu/drm/i915/display/intel_cursor.c

633

skl_cursor_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id)));

drivers/gpu/drm/i915/display/intel_cursor.c

636

const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

113

dbuf_bw->active_planes[slice] |= BIT(plane_id);

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

122

enum plane_id plane_id;

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

129

for_each_plane_id_on_crtc(crtc, plane_id) {

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

134

if (plane_id == PLANE_CURSOR)

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

137

skl_plane_calc_dbuf_bw(dbuf_bw, crtc, plane_id,

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

138

&crtc_state->wm.skl.plane_ddb[plane_id],

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

139

crtc_state->data_rate[plane_id]);

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

142

skl_plane_calc_dbuf_bw(dbuf_bw, crtc, plane_id,

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

143

&crtc_state->wm.skl.plane_ddb_y[plane_id],

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

144

crtc_state->data_rate[plane_id]);

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

99

enum plane_id plane_id,

drivers/gpu/drm/i915/display/intel_display_debugfs.c

677

enum plane_id plane_id;

drivers/gpu/drm/i915/display/intel_display_debugfs.c

681

for_each_plane_id_on_crtc(crtc, plane_id) {

drivers/gpu/drm/i915/display/intel_display_debugfs.c

682

entry = &crtc_state->wm.skl.plane_ddb[plane_id];

drivers/gpu/drm/i915/display/intel_display_debugfs.c

683

seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane_id + 1,

drivers/gpu/drm/i915/display/intel_display_irq.c

101

bool (*handle)(struct intel_crtc *crtc, enum plane_id plane_id);

drivers/gpu/drm/i915/display/intel_display_irq.c

103

enum plane_id plane_id;

drivers/gpu/drm/i915/display/intel_display_irq.c

106

static bool handle_plane_fault(struct intel_crtc *crtc, enum plane_id plane_id)

drivers/gpu/drm/i915/display/intel_display_irq.c

112

plane = intel_crtc_get_plane(crtc, plane_id);

drivers/gpu/drm/i915/display/intel_display_irq.c

1146

static bool handle_plane_ats_fault(struct intel_crtc *crtc, enum plane_id plane_id)

drivers/gpu/drm/i915/display/intel_display_irq.c

1157

static bool handle_pipedmc_ats_fault(struct intel_crtc *crtc, enum plane_id plane_id)

drivers/gpu/drm/i915/display/intel_display_irq.c

1168

static bool handle_pipedmc_fault(struct intel_crtc *crtc, enum plane_id plane_id)

drivers/gpu/drm/i915/display/intel_display_irq.c

1183

{ .fault = GEN11_PIPE_PLANE5_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_5, },

drivers/gpu/drm/i915/display/intel_display_irq.c

1184

{ .fault = GEN9_PIPE_PLANE4_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_4, },

drivers/gpu/drm/i915/display/intel_display_irq.c

1185

{ .fault = GEN9_PIPE_PLANE3_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_3, },

drivers/gpu/drm/i915/display/intel_display_irq.c

1186

{ .fault = GEN9_PIPE_PLANE2_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_2, },

drivers/gpu/drm/i915/display/intel_display_irq.c

1187

{ .fault = GEN9_PIPE_PLANE1_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_1, },

drivers/gpu/drm/i915/display/intel_display_irq.c

1188

{ .fault = GEN9_PIPE_CURSOR_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, },

drivers/gpu/drm/i915/display/intel_display_irq.c

1194

{ .fault = GEN11_PIPE_PLANE7_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_7, },

drivers/gpu/drm/i915/display/intel_display_irq.c

1195

{ .fault = GEN11_PIPE_PLANE6_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_6, },

drivers/gpu/drm/i915/display/intel_display_irq.c

1196

{ .fault = GEN11_PIPE_PLANE5_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_5, },

drivers/gpu/drm/i915/display/intel_display_irq.c

1197

{ .fault = GEN9_PIPE_PLANE4_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_4, },

drivers/gpu/drm/i915/display/intel_display_irq.c

1198

{ .fault = GEN9_PIPE_PLANE3_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_3, },

drivers/gpu/drm/i915/display/intel_display_irq.c

1199

{ .fault = GEN9_PIPE_PLANE2_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_2, },

drivers/gpu/drm/i915/display/intel_display_irq.c

1200

{ .fault = GEN9_PIPE_PLANE1_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_1, },

drivers/gpu/drm/i915/display/intel_display_irq.c

1201

{ .fault = GEN9_PIPE_CURSOR_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, },

drivers/gpu/drm/i915/display/intel_display_irq.c

1206

{ .fault = GEN11_PIPE_PLANE7_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_7, },

drivers/gpu/drm/i915/display/intel_display_irq.c

1207

{ .fault = GEN11_PIPE_PLANE6_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_6, },

drivers/gpu/drm/i915/display/intel_display_irq.c

1208

{ .fault = GEN11_PIPE_PLANE5_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_5, },

drivers/gpu/drm/i915/display/intel_display_irq.c

1209

{ .fault = GEN9_PIPE_PLANE4_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_4, },

drivers/gpu/drm/i915/display/intel_display_irq.c

1210

{ .fault = GEN9_PIPE_PLANE3_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_3, },

drivers/gpu/drm/i915/display/intel_display_irq.c

1211

{ .fault = GEN9_PIPE_PLANE2_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_2, },

drivers/gpu/drm/i915/display/intel_display_irq.c

1212

{ .fault = GEN9_PIPE_PLANE1_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_1, },

drivers/gpu/drm/i915/display/intel_display_irq.c

1213

{ .fault = GEN9_PIPE_CURSOR_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, },

drivers/gpu/drm/i915/display/intel_display_irq.c

1218

{ .fault = GEN9_PIPE_PLANE4_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_4, },

drivers/gpu/drm/i915/display/intel_display_irq.c

1219

{ .fault = GEN9_PIPE_PLANE3_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_3, },

drivers/gpu/drm/i915/display/intel_display_irq.c

1220

{ .fault = GEN9_PIPE_PLANE2_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_2, },

drivers/gpu/drm/i915/display/intel_display_irq.c

1221

{ .fault = GEN9_PIPE_PLANE1_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_1, },

drivers/gpu/drm/i915/display/intel_display_irq.c

1222

{ .fault = GEN9_PIPE_CURSOR_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, },

drivers/gpu/drm/i915/display/intel_display_irq.c

1227

{ .fault = GEN8_PIPE_SPRITE_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, },

drivers/gpu/drm/i915/display/intel_display_irq.c

1228

{ .fault = GEN8_PIPE_PRIMARY_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, },

drivers/gpu/drm/i915/display/intel_display_irq.c

1229

{ .fault = GEN8_PIPE_CURSOR_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, },

drivers/gpu/drm/i915/display/intel_display_irq.c

138

if (handler->handle(crtc, handler->plane_id))

drivers/gpu/drm/i915/display/intel_display_irq.c

1865

{ .fault = SPRITEB_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE1, },

drivers/gpu/drm/i915/display/intel_display_irq.c

1866

{ .fault = SPRITEA_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, },

drivers/gpu/drm/i915/display/intel_display_irq.c

1867

{ .fault = PLANEA_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, },

drivers/gpu/drm/i915/display/intel_display_irq.c

1868

{ .fault = CURSORA_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, },

drivers/gpu/drm/i915/display/intel_display_irq.c

1869

{ .fault = SPRITED_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE1, },

drivers/gpu/drm/i915/display/intel_display_irq.c

1870

{ .fault = SPRITEC_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, },

drivers/gpu/drm/i915/display/intel_display_irq.c

1871

{ .fault = PLANEB_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, },

drivers/gpu/drm/i915/display/intel_display_irq.c

1872

{ .fault = CURSORB_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, },

drivers/gpu/drm/i915/display/intel_display_irq.c

1873

{ .fault = SPRITEF_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE1, },

drivers/gpu/drm/i915/display/intel_display_irq.c

1874

{ .fault = SPRITEE_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, },

drivers/gpu/drm/i915/display/intel_display_irq.c

1875

{ .fault = PLANEC_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, },

drivers/gpu/drm/i915/display/intel_display_irq.c

1876

{ .fault = CURSORC_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, },

drivers/gpu/drm/i915/display/intel_display_irq.c

745

{ .fault = ERR_INT_SPRITE_A_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, },

drivers/gpu/drm/i915/display/intel_display_irq.c

746

{ .fault = ERR_INT_PRIMARY_A_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, },

drivers/gpu/drm/i915/display/intel_display_irq.c

747

{ .fault = ERR_INT_CURSOR_A_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, },

drivers/gpu/drm/i915/display/intel_display_irq.c

748

{ .fault = ERR_INT_SPRITE_B_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, },

drivers/gpu/drm/i915/display/intel_display_irq.c

749

{ .fault = ERR_INT_PRIMARY_B_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, },

drivers/gpu/drm/i915/display/intel_display_irq.c

750

{ .fault = ERR_INT_CURSOR_B_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, },

drivers/gpu/drm/i915/display/intel_display_irq.c

751

{ .fault = ERR_INT_SPRITE_C_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, },

drivers/gpu/drm/i915/display/intel_display_irq.c

752

{ .fault = ERR_INT_PRIMARY_C_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, },

drivers/gpu/drm/i915/display/intel_display_irq.c

753

{ .fault = ERR_INT_CURSOR_C_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, },

drivers/gpu/drm/i915/display/intel_display_irq.c

862

{ .fault = GTT_FAULT_SPRITE_A_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, },

drivers/gpu/drm/i915/display/intel_display_irq.c

863

{ .fault = GTT_FAULT_SPRITE_B_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, },

drivers/gpu/drm/i915/display/intel_display_irq.c

864

{ .fault = GTT_FAULT_PRIMARY_A_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, },

drivers/gpu/drm/i915/display/intel_display_irq.c

865

{ .fault = GTT_FAULT_PRIMARY_B_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, },

drivers/gpu/drm/i915/display/intel_display_irq.c

866

{ .fault = GTT_FAULT_CURSOR_A_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, },

drivers/gpu/drm/i915/display/intel_display_irq.c

867

{ .fault = GTT_FAULT_CURSOR_B_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, },

drivers/gpu/drm/i915/display/intel_display_regs.h

1022

#define PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id) REG_FIELD_PREP(PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK, (plane_id))

drivers/gpu/drm/i915/display/intel_display_regs.h

1229

#define PS_BINDING_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_MASK, (plane_id) + 1)

drivers/gpu/drm/i915/display/intel_display_regs.h

1252

#define PS_BINDING_Y_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_Y_MASK, (plane_id) + 1)

drivers/gpu/drm/i915/display/intel_display_regs.h

1435

#define GEN9_PIPE_PLANE_FLIP_DONE(plane_id) \

drivers/gpu/drm/i915/display/intel_display_regs.h

1436

REG_BIT(((plane_id) >= PLANE_5 ? 16 - PLANE_5 : 3 - PLANE_1) + (plane_id)) /* skl+ */

drivers/gpu/drm/i915/display/intel_display_types.h

1585

enum plane_id id;

drivers/gpu/drm/i915/display/intel_dpt.c

19

enum plane_id plane_id;

drivers/gpu/drm/i915/display/intel_dpt.c

21

for_each_plane_id_on_crtc(crtc, plane_id) {

drivers/gpu/drm/i915/display/intel_dpt.c

22

if (plane_id == PLANE_CURSOR)

drivers/gpu/drm/i915/display/intel_dpt.c

25

intel_de_rmw(display, PLANE_CHICKEN(pipe, plane_id),

drivers/gpu/drm/i915/display/intel_fbc_regs.h

66

#define DPFC_CTL_PLANE_BINDING(plane_id) REG_FIELD_PREP(DPFC_CTL_PLANE_BINDING_MASK, (plane_id))

drivers/gpu/drm/i915/display/intel_frontbuffer.h

58

#define INTEL_FRONTBUFFER(pipe, plane_id) \

drivers/gpu/drm/i915/display/intel_frontbuffer.h

59

BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe));

drivers/gpu/drm/i915/display/intel_plane.c

823

intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id)

drivers/gpu/drm/i915/display/intel_plane.c

829

if (plane->id == plane_id)

drivers/gpu/drm/i915/display/intel_plane.c

902

enum plane_id plane_id = plane->id;

drivers/gpu/drm/i915/display/intel_plane.c

905

!(*update_mask & BIT(plane_id)))

drivers/gpu/drm/i915/display/intel_plane.c

908

if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb[plane_id],

drivers/gpu/drm/i915/display/intel_plane.c

909

ddb, I915_MAX_PLANES, plane_id) ||

drivers/gpu/drm/i915/display/intel_plane.c

910

skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id],

drivers/gpu/drm/i915/display/intel_plane.c

911

ddb_y, I915_MAX_PLANES, plane_id))

drivers/gpu/drm/i915/display/intel_plane.c

914

*update_mask &= ~BIT(plane_id);

drivers/gpu/drm/i915/display/intel_plane.c

915

ddb[plane_id] = crtc_state->wm.skl.plane_ddb[plane_id];

drivers/gpu/drm/i915/display/intel_plane.c

916

ddb_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id];

drivers/gpu/drm/i915/display/intel_plane.h

22

enum plane_id;

drivers/gpu/drm/i915/display/intel_plane.h

25

intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id);

drivers/gpu/drm/i915/display/intel_sprite.c

104

intel_de_write_fw(display, SPCSCYGOFF(plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

106

intel_de_write_fw(display, SPCSCCBOFF(plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

108

intel_de_write_fw(display, SPCSCCROFF(plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

111

intel_de_write_fw(display, SPCSCC01(plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

113

intel_de_write_fw(display, SPCSCC23(plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

115

intel_de_write_fw(display, SPCSCC45(plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

117

intel_de_write_fw(display, SPCSCC67(plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

119

intel_de_write_fw(display, SPCSCC8(plane_id), SPCSC_C0(csc[8]));

drivers/gpu/drm/i915/display/intel_sprite.c

121

intel_de_write_fw(display, SPCSCYGICLAMP(plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

123

intel_de_write_fw(display, SPCSCCBICLAMP(plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

125

intel_de_write_fw(display, SPCSCCRICLAMP(plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

128

intel_de_write_fw(display, SPCSCYGOCLAMP(plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

130

intel_de_write_fw(display, SPCSCCBOCLAMP(plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

132

intel_de_write_fw(display, SPCSCCROCLAMP(plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

146

enum plane_id plane_id = plane->id;

drivers/gpu/drm/i915/display/intel_sprite.c

172

intel_de_write_fw(display, SPCLRC0(pipe, plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

174

intel_de_write_fw(display, SPCLRC1(pipe, plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

348

enum plane_id plane_id = plane->id;

drivers/gpu/drm/i915/display/intel_sprite.c

361

intel_de_write_fw(display, SPGAMC(pipe, plane_id, i - 1),

drivers/gpu/drm/i915/display/intel_sprite.c

373

enum plane_id plane_id = plane->id;

drivers/gpu/drm/i915/display/intel_sprite.c

379

intel_de_write_fw(display, SPSTRIDE(pipe, plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

381

intel_de_write_fw(display, SPPOS(pipe, plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

383

intel_de_write_fw(display, SPSIZE(pipe, plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

395

enum plane_id plane_id = plane->id;

drivers/gpu/drm/i915/display/intel_sprite.c

407

intel_de_write_fw(display, SPKEYMINVAL(pipe, plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

409

intel_de_write_fw(display, SPKEYMSK(pipe, plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

411

intel_de_write_fw(display, SPKEYMAXVAL(pipe, plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

415

intel_de_write_fw(display, SPCONSTALPHA(pipe, plane_id), 0);

drivers/gpu/drm/i915/display/intel_sprite.c

417

intel_de_write_fw(display, SPLINOFF(pipe, plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

419

intel_de_write_fw(display, SPTILEOFF(pipe, plane_id),

drivers/gpu/drm/i915/display/intel_sprite.c

427

intel_de_write_fw(display, SPCNTR(pipe, plane_id), sprctl);

drivers/gpu/drm/i915/display/intel_sprite.c

428

intel_de_write_fw(display, SPSURF(pipe, plane_id), plane_state->surf);

drivers/gpu/drm/i915/display/intel_sprite.c

441

enum plane_id plane_id = plane->id;

drivers/gpu/drm/i915/display/intel_sprite.c

443

intel_de_write_fw(display, SPCNTR(pipe, plane_id), 0);

drivers/gpu/drm/i915/display/intel_sprite.c

444

intel_de_write_fw(display, SPSURF(pipe, plane_id), 0);

drivers/gpu/drm/i915/display/intel_sprite.c

464

enum plane_id plane_id = plane->id;

drivers/gpu/drm/i915/display/intel_sprite.c

473

ret = intel_de_read(display, SPCNTR(plane->pipe, plane_id)) & SP_ENABLE;

drivers/gpu/drm/i915/display/intel_sprite.c

73

enum plane_id plane_id = plane->id;

drivers/gpu/drm/i915/display/intel_sprite_regs.h

230

#define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \

drivers/gpu/drm/i915/display/intel_sprite_regs.h

231

_PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))

drivers/gpu/drm/i915/display/intel_sprite_regs.h

232

#define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \

drivers/gpu/drm/i915/display/intel_sprite_regs.h

233

_MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))

drivers/gpu/drm/i915/display/intel_sprite_regs.h

237

#define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)

drivers/gpu/drm/i915/display/intel_sprite_regs.h

266

#define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)

drivers/gpu/drm/i915/display/intel_sprite_regs.h

270

#define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)

drivers/gpu/drm/i915/display/intel_sprite_regs.h

274

#define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)

drivers/gpu/drm/i915/display/intel_sprite_regs.h

282

#define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)

drivers/gpu/drm/i915/display/intel_sprite_regs.h

290

#define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)

drivers/gpu/drm/i915/display/intel_sprite_regs.h

294

#define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)

drivers/gpu/drm/i915/display/intel_sprite_regs.h

298

#define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)

drivers/gpu/drm/i915/display/intel_sprite_regs.h

303

#define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)

drivers/gpu/drm/i915/display/intel_sprite_regs.h

307

#define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)

drivers/gpu/drm/i915/display/intel_sprite_regs.h

315

#define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)

drivers/gpu/drm/i915/display/intel_sprite_regs.h

322

#define SPSURFLIVE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURFLIVE, _SPBSURFLIVE)

drivers/gpu/drm/i915/display/intel_sprite_regs.h

326

#define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)

drivers/gpu/drm/i915/display/intel_sprite_regs.h

334

#define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)

drivers/gpu/drm/i915/display/intel_sprite_regs.h

342

#define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */

drivers/gpu/drm/i915/display/intel_sprite_regs.h

351

#define _MMIO_CHV_SPCSC(plane_id, reg) \

drivers/gpu/drm/i915/display/intel_sprite_regs.h

352

_MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))

drivers/gpu/drm/i915/display/intel_sprite_regs.h

354

#define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900)

drivers/gpu/drm/i915/display/intel_sprite_regs.h

355

#define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904)

drivers/gpu/drm/i915/display/intel_sprite_regs.h

356

#define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908)

drivers/gpu/drm/i915/display/intel_sprite_regs.h

362

#define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c)

drivers/gpu/drm/i915/display/intel_sprite_regs.h

363

#define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910)

drivers/gpu/drm/i915/display/intel_sprite_regs.h

364

#define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914)

drivers/gpu/drm/i915/display/intel_sprite_regs.h

365

#define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918)

drivers/gpu/drm/i915/display/intel_sprite_regs.h

366

#define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c)

drivers/gpu/drm/i915/display/intel_sprite_regs.h

372

#define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920)

drivers/gpu/drm/i915/display/intel_sprite_regs.h

373

#define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924)

drivers/gpu/drm/i915/display/intel_sprite_regs.h

374

#define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928)

drivers/gpu/drm/i915/display/intel_sprite_regs.h

380

#define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c)

drivers/gpu/drm/i915/display/intel_sprite_regs.h

381

#define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930)

drivers/gpu/drm/i915/display/intel_sprite_regs.h

382

#define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934)

drivers/gpu/drm/i915/display/intel_sprite_uapi.c

67

plane = drm_plane_find(dev, file_priv, set->plane_id);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1382

enum plane_id plane_id = plane->id;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1385

intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 0), 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1386

intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 1), 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1388

intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 2), 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1389

intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 3), 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1391

intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 4), 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1392

intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 5), 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1394

intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane_id, 0), 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1395

intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane_id, 1), 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1396

intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane_id, 2), 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1398

intel_de_write_dsb(display, dsb, PLANE_CSC_POSTOFF(pipe, plane_id, 0), 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1399

intel_de_write_dsb(display, dsb, PLANE_CSC_POSTOFF(pipe, plane_id, 1), 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1400

intel_de_write_dsb(display, dsb, PLANE_CSC_POSTOFF(pipe, plane_id, 2), 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

1410

enum plane_id plane_id = plane->id;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1424

intel_de_write_dsb(display, dsb, PLANE_STRIDE(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1426

intel_de_write_dsb(display, dsb, PLANE_POS(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1428

intel_de_write_dsb(display, dsb, PLANE_SIZE(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1441

enum plane_id plane_id = plane->id;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1459

intel_de_write_dsb(display, dsb, PLANE_KEYVAL(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1461

intel_de_write_dsb(display, dsb, PLANE_KEYMSK(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1463

intel_de_write_dsb(display, dsb, PLANE_KEYMAX(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1466

intel_de_write_dsb(display, dsb, PLANE_OFFSET(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1469

intel_de_write_dsb(display, dsb, PLANE_AUX_DIST(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1472

intel_de_write_dsb(display, dsb, PLANE_AUX_OFFSET(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1477

intel_de_write_dsb(display, dsb, PLANE_COLOR_CTL(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1495

intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1497

intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1554

enum plane_id plane_id = plane->id;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1578

intel_de_write_dsb(display, dsb, PLANE_STRIDE(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1580

intel_de_write_dsb(display, dsb, PLANE_POS(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1582

intel_de_write_dsb(display, dsb, PLANE_SIZE(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1585

intel_de_write_dsb(display, dsb, PLANE_KEYVAL(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1587

intel_de_write_dsb(display, dsb, PLANE_KEYMSK(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1589

intel_de_write_dsb(display, dsb, PLANE_KEYMAX(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1592

intel_de_write_dsb(display, dsb, PLANE_OFFSET(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1596

intel_de_write_dsb(display, dsb, PLANE_CC_VAL(pipe, plane_id, 0),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1598

intel_de_write_dsb(display, dsb, PLANE_CC_VAL(pipe, plane_id, 1),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1604

intel_de_write_dsb(display, dsb, PLANE_AUX_DIST(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1607

if (icl_is_hdr_plane(display, plane_id))

drivers/gpu/drm/i915/display/skl_universal_plane.c

1608

intel_de_write_dsb(display, dsb, PLANE_CUS_CTL(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1611

intel_de_write_dsb(display, dsb, PLANE_COLOR_CTL(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1614

if (fb->format->is_yuv && icl_is_hdr_plane(display, plane_id))

drivers/gpu/drm/i915/display/skl_universal_plane.c

1654

enum plane_id plane_id = plane->id;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1690

intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1692

intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1715

enum plane_id plane_id = plane->id;

drivers/gpu/drm/i915/display/skl_universal_plane.c

1729

intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

1731

intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

2471

enum pipe pipe, enum plane_id plane_id)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2475

if (skl_plane_has_fbc(display, fbc_id, plane_id))

drivers/gpu/drm/i915/display/skl_universal_plane.c

2482

enum pipe pipe, enum plane_id plane_id)

drivers/gpu/drm/i915/display/skl_universal_plane.c

249

enum plane_id plane_id)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2491

return plane_id == PLANE_1 || plane_id == PLANE_2;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2495

enum pipe pipe, enum plane_id plane_id,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2498

if (skl_plane_has_planar(display, pipe, plane_id)) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

2508

enum pipe pipe, enum plane_id plane_id)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2510

return plane_id == PLANE_1 || plane_id == PLANE_2;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2514

enum pipe pipe, enum plane_id plane_id,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2517

if (glk_plane_has_planar(display, pipe, plane_id)) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

252

icl_nv12_y_plane_mask(display) & BIT(plane_id);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2527

enum pipe pipe, enum plane_id plane_id,

drivers/gpu/drm/i915/display/skl_universal_plane.c

2530

if (icl_is_hdr_plane(display, plane_id)) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

2533

} else if (icl_is_nv12_y_plane(display, plane_id)) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

260

bool icl_is_hdr_plane(struct intel_display *display, enum plane_id plane_id)

drivers/gpu/drm/i915/display/skl_universal_plane.c

263

icl_hdr_plane_mask() & BIT(plane_id);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2755

enum pipe pipe, enum plane_id plane_id)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2760

return plane_id == PLANE_1 || plane_id == PLANE_2;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2764

enum pipe pipe, enum plane_id plane_id)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2770

if (skl_plane_has_rc_ccs(display, pipe, plane_id))

drivers/gpu/drm/i915/display/skl_universal_plane.c

2783

enum pipe pipe, enum plane_id plane_id)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2796

enum pipe pipe, enum plane_id plane_id)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2805

enum plane_id plane_id)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2811

return plane_id < PLANE_6;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2815

enum pipe pipe, enum plane_id plane_id)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2826

if (tgl_plane_has_mc_ccs(display, plane_id))

drivers/gpu/drm/i915/display/skl_universal_plane.c

2863

enum pipe pipe, enum plane_id plane_id)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2881

plane->id = plane_id;

drivers/gpu/drm/i915/display/skl_universal_plane.c

2882

plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane_id);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2884

intel_fbc_add_plane(skl_plane_fbc(display, pipe, plane_id), plane);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2896

if (icl_is_hdr_plane(display, plane_id))

drivers/gpu/drm/i915/display/skl_universal_plane.c

2941

if (HAS_ASYNC_FLIPS(display) && plane_id == PLANE_1) {

drivers/gpu/drm/i915/display/skl_universal_plane.c

2957

plane_id, &num_formats);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2960

plane_id, &num_formats);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2963

plane_id, &num_formats);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2972

if (plane_id == PLANE_1)

drivers/gpu/drm/i915/display/skl_universal_plane.c

2978

caps = tgl_plane_caps(display, pipe, plane_id);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2980

caps = icl_plane_caps(display, pipe, plane_id);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2982

caps = glk_plane_caps(display, pipe, plane_id);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2984

caps = skl_plane_caps(display, pipe, plane_id);

drivers/gpu/drm/i915/display/skl_universal_plane.c

2992

"plane %d%c", plane_id + 1,

drivers/gpu/drm/i915/display/skl_universal_plane.c

3035

drm_plane_create_zpos_immutable_property(&plane->base, plane_id);

drivers/gpu/drm/i915/display/skl_universal_plane.c

3062

enum plane_id plane_id = plane->id;

drivers/gpu/drm/i915/display/skl_universal_plane.c

3093

val = intel_de_read(display, PLANE_CTL(pipe, plane_id));

drivers/gpu/drm/i915/display/skl_universal_plane.c

3103

color_ctl = intel_de_read(display, PLANE_COLOR_CTL(pipe, plane_id));

drivers/gpu/drm/i915/display/skl_universal_plane.c

3189

base = intel_de_read(display, PLANE_SURF(pipe, plane_id)) & PLANE_SURF_ADDR_MASK;

drivers/gpu/drm/i915/display/skl_universal_plane.c

3192

offset = intel_de_read(display, PLANE_OFFSET(pipe, plane_id));

drivers/gpu/drm/i915/display/skl_universal_plane.c

3195

val = intel_de_read(display, PLANE_SIZE(pipe, plane_id));

drivers/gpu/drm/i915/display/skl_universal_plane.c

3199

val = intel_de_read(display, PLANE_STRIDE(pipe, plane_id));

drivers/gpu/drm/i915/display/skl_universal_plane.c

3229

enum plane_id plane_id = plane->id;

drivers/gpu/drm/i915/display/skl_universal_plane.c

3242

intel_de_write(display, PLANE_SURF(pipe, plane_id), plane_state->surf);

drivers/gpu/drm/i915/display/skl_universal_plane.c

449

enum intel_fbc_id fbc_id, enum plane_id plane_id)

drivers/gpu/drm/i915/display/skl_universal_plane.c

455

return icl_is_hdr_plane(display, plane_id);

drivers/gpu/drm/i915/display/skl_universal_plane.c

457

return plane_id == PLANE_1;

drivers/gpu/drm/i915/display/skl_universal_plane.c

682

enum plane_id plane_id = plane->id;

drivers/gpu/drm/i915/display/skl_universal_plane.c

724

intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0),

drivers/gpu/drm/i915/display/skl_universal_plane.c

726

intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1),

drivers/gpu/drm/i915/display/skl_universal_plane.c

728

intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2),

drivers/gpu/drm/i915/display/skl_universal_plane.c

730

intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3),

drivers/gpu/drm/i915/display/skl_universal_plane.c

732

intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4),

drivers/gpu/drm/i915/display/skl_universal_plane.c

734

intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 5),

drivers/gpu/drm/i915/display/skl_universal_plane.c

737

intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0),

drivers/gpu/drm/i915/display/skl_universal_plane.c

739

intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1),

drivers/gpu/drm/i915/display/skl_universal_plane.c

741

intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2),

drivers/gpu/drm/i915/display/skl_universal_plane.c

744

PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 0), 0x0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

746

PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 1), 0x0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

748

PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

826

enum plane_id plane_id = plane->id;

drivers/gpu/drm/i915/display/skl_universal_plane.c

830

&crtc_state->wm.skl.plane_ddb[plane_id];

drivers/gpu/drm/i915/display/skl_universal_plane.c

832

&crtc_state->wm.skl.plane_ddb_y[plane_id];

drivers/gpu/drm/i915/display/skl_universal_plane.c

833

const u16 *min_ddb = &crtc_state->wm.skl.plane_min_ddb[plane_id];

drivers/gpu/drm/i915/display/skl_universal_plane.c

835

&crtc_state->wm.skl.plane_interim_ddb[plane_id];

drivers/gpu/drm/i915/display/skl_universal_plane.c

839

intel_de_write_dsb(display, dsb, PLANE_WM(pipe, plane_id, level),

drivers/gpu/drm/i915/display/skl_universal_plane.c

840

skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));

drivers/gpu/drm/i915/display/skl_universal_plane.c

842

intel_de_write_dsb(display, dsb, PLANE_WM_TRANS(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

843

skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id)));

drivers/gpu/drm/i915/display/skl_universal_plane.c

846

const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];

drivers/gpu/drm/i915/display/skl_universal_plane.c

848

intel_de_write_dsb(display, dsb, PLANE_WM_SAGV(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

850

intel_de_write_dsb(display, dsb, PLANE_WM_SAGV_TRANS(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

854

intel_de_write_dsb(display, dsb, PLANE_BUF_CFG(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

858

intel_de_write_dsb(display, dsb, PLANE_NV12_BUF_CFG(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

862

intel_de_write_dsb(display, dsb, PLANE_MIN_BUF_CFG(pipe, plane_id),

drivers/gpu/drm/i915/display/skl_universal_plane.c

872

enum plane_id plane_id = plane->id;

drivers/gpu/drm/i915/display/skl_universal_plane.c

877

intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id), 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

878

intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id), 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

916

enum plane_id plane_id = plane->id;

drivers/gpu/drm/i915/display/skl_universal_plane.c

919

if (icl_is_hdr_plane(display, plane_id))

drivers/gpu/drm/i915/display/skl_universal_plane.c

920

intel_de_write_dsb(display, dsb, PLANE_CUS_CTL(pipe, plane_id), 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

930

intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id), 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

931

intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id), 0);

drivers/gpu/drm/i915/display/skl_universal_plane.c

940

enum plane_id plane_id = plane->id;

drivers/gpu/drm/i915/display/skl_universal_plane.c

949

ret = intel_de_read(display, PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE;

drivers/gpu/drm/i915/display/skl_universal_plane.h

19

enum plane_id;

drivers/gpu/drm/i915/display/skl_universal_plane.h

23

enum pipe pipe, enum plane_id plane_id);

drivers/gpu/drm/i915/display/skl_universal_plane.h

39

enum plane_id plane_id);

drivers/gpu/drm/i915/display/skl_universal_plane.h

41

bool icl_is_hdr_plane(struct intel_display *display, enum plane_id plane_id);

drivers/gpu/drm/i915/display/skl_watermark.c

1295

enum plane_id plane_id;

drivers/gpu/drm/i915/display/skl_watermark.c

1298

for_each_plane_id_on_crtc(crtc, plane_id) {

drivers/gpu/drm/i915/display/skl_watermark.c

1299

if (plane_id == PLANE_CURSOR)

drivers/gpu/drm/i915/display/skl_watermark.c

1302

data_rate += crtc_state->rel_data_rate[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

1305

data_rate += crtc_state->rel_data_rate_y[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

1313

enum plane_id plane_id,

drivers/gpu/drm/i915/display/skl_watermark.c

1316

const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

1326

enum plane_id plane_id)

drivers/gpu/drm/i915/display/skl_watermark.c

1328

const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

1444

enum plane_id plane_id;

drivers/gpu/drm/i915/display/skl_watermark.c

1479

for_each_plane_id_on_crtc(crtc, plane_id) {

drivers/gpu/drm/i915/display/skl_watermark.c

1481

&crtc_state->wm.skl.optimal.planes[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

1483

if (plane_id == PLANE_CURSOR) {

drivers/gpu/drm/i915/display/skl_watermark.c

1485

&crtc_state->wm.skl.plane_ddb[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

1523

for_each_plane_id_on_crtc(crtc, plane_id) {

drivers/gpu/drm/i915/display/skl_watermark.c

1525

&crtc_state->wm.skl.plane_ddb[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

1527

&crtc_state->wm.skl.plane_ddb_y[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

1528

u16 *min_ddb = &crtc_state->wm.skl.plane_min_ddb[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

1530

&crtc_state->wm.skl.plane_interim_ddb[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

1532

&crtc_state->wm.skl.optimal.planes[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

1534

if (plane_id == PLANE_CURSOR)

drivers/gpu/drm/i915/display/skl_watermark.c

1538

crtc_state->nv12_planes & BIT(plane_id))

drivers/gpu/drm/i915/display/skl_watermark.c

1540

ddb_y, crtc_state->rel_data_rate_y[plane_id],

drivers/gpu/drm/i915/display/skl_watermark.c

1541

ddb, crtc_state->rel_data_rate[plane_id]);

drivers/gpu/drm/i915/display/skl_watermark.c

1544

ddb, crtc_state->rel_data_rate[plane_id]);

drivers/gpu/drm/i915/display/skl_watermark.c

1560

for_each_plane_id_on_crtc(crtc, plane_id) {

drivers/gpu/drm/i915/display/skl_watermark.c

1562

&crtc_state->wm.skl.plane_ddb[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

1564

&crtc_state->wm.skl.plane_ddb_y[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

1566

&crtc_state->wm.skl.optimal.planes[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

1569

crtc_state->nv12_planes & BIT(plane_id))

drivers/gpu/drm/i915/display/skl_watermark.c

1586

for_each_plane_id_on_crtc(crtc, plane_id) {

drivers/gpu/drm/i915/display/skl_watermark.c

1588

&crtc_state->wm.skl.plane_ddb[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

1590

&crtc_state->wm.skl.plane_ddb_y[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

1592

&crtc_state->wm.skl.plane_interim_ddb[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

1594

&crtc_state->wm.skl.optimal.planes[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

1597

crtc_state->nv12_planes & BIT(plane_id)) {

drivers/gpu/drm/i915/display/skl_watermark.c

2107

enum plane_id plane_id = plane->id;

drivers/gpu/drm/i915/display/skl_watermark.c

2108

struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

2137

enum plane_id plane_id = plane->id;

drivers/gpu/drm/i915/display/skl_watermark.c

2138

struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

2228

enum plane_id plane_id;

drivers/gpu/drm/i915/display/skl_watermark.c

2231

for_each_plane_id_on_crtc(crtc, plane_id) {

drivers/gpu/drm/i915/display/skl_watermark.c

2232

const struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

2310

enum plane_id plane_id;

drivers/gpu/drm/i915/display/skl_watermark.c

2312

for_each_plane_id_on_crtc(crtc, plane_id) {

drivers/gpu/drm/i915/display/skl_watermark.c

2314

&crtc_state->wm.skl.optimal.planes[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

2328

enum plane_id plane_id;

drivers/gpu/drm/i915/display/skl_watermark.c

2330

for_each_plane_id_on_crtc(crtc, plane_id) {

drivers/gpu/drm/i915/display/skl_watermark.c

2332

&crtc_state->wm.skl.optimal.planes[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

2446

enum plane_id plane_id = plane->id;

drivers/gpu/drm/i915/display/skl_watermark.c

2448

if (skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb[plane_id],

drivers/gpu/drm/i915/display/skl_watermark.c

2449

&new_crtc_state->wm.skl.plane_ddb[plane_id]) &&

drivers/gpu/drm/i915/display/skl_watermark.c

2450

skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_y[plane_id],

drivers/gpu/drm/i915/display/skl_watermark.c

2451

&new_crtc_state->wm.skl.plane_ddb_y[plane_id]))

drivers/gpu/drm/i915/display/skl_watermark.c

2464

new_crtc_state->update_planes |= BIT(plane_id);

drivers/gpu/drm/i915/display/skl_watermark.c

2701

enum plane_id plane_id = plane->id;

drivers/gpu/drm/i915/display/skl_watermark.c

2704

old = &old_crtc_state->wm.skl.plane_ddb[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

2705

new = &new_crtc_state->wm.skl.plane_ddb[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

2713

old = &old_crtc_state->wm.skl.plane_ddb_y[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

2714

new = &new_crtc_state->wm.skl.plane_ddb_y[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

2721

enum plane_id plane_id = plane->id;

drivers/gpu/drm/i915/display/skl_watermark.c

2724

old_wm = &old_pipe_wm->planes[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

2725

new_wm = &new_pipe_wm->planes[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

2795

enum plane_id plane_id = plane->id;

drivers/gpu/drm/i915/display/skl_watermark.c

2821

new_crtc_state->update_planes |= BIT(plane_id);

drivers/gpu/drm/i915/display/skl_watermark.c

2978

enum plane_id plane_id;

drivers/gpu/drm/i915/display/skl_watermark.c

2982

for_each_plane_id_on_crtc(crtc, plane_id) {

drivers/gpu/drm/i915/display/skl_watermark.c

2983

struct skl_plane_wm *wm = &out->planes[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

2986

if (plane_id != PLANE_CURSOR)

drivers/gpu/drm/i915/display/skl_watermark.c

2987

val = intel_de_read(display, PLANE_WM(pipe, plane_id, level));

drivers/gpu/drm/i915/display/skl_watermark.c

2994

if (plane_id != PLANE_CURSOR)

drivers/gpu/drm/i915/display/skl_watermark.c

2995

val = intel_de_read(display, PLANE_WM_TRANS(pipe, plane_id));

drivers/gpu/drm/i915/display/skl_watermark.c

3002

if (plane_id != PLANE_CURSOR)

drivers/gpu/drm/i915/display/skl_watermark.c

3003

val = intel_de_read(display, PLANE_WM_SAGV(pipe, plane_id));

drivers/gpu/drm/i915/display/skl_watermark.c

3009

if (plane_id != PLANE_CURSOR)

drivers/gpu/drm/i915/display/skl_watermark.c

3010

val = intel_de_read(display, PLANE_WM_SAGV_TRANS(pipe, plane_id));

drivers/gpu/drm/i915/display/skl_watermark.c

3039

enum plane_id plane_id;

drivers/gpu/drm/i915/display/skl_watermark.c

3052

for_each_plane_id_on_crtc(crtc, plane_id) {

drivers/gpu/drm/i915/display/skl_watermark.c

3054

&crtc_state->wm.skl.plane_ddb[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

3056

&crtc_state->wm.skl.plane_ddb_y[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

3058

&crtc_state->wm.skl.plane_min_ddb[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

3060

&crtc_state->wm.skl.plane_interim_ddb[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

3066

plane_id, ddb, ddb_y,

drivers/gpu/drm/i915/display/skl_watermark.c

308

enum plane_id plane_id;

drivers/gpu/drm/i915/display/skl_watermark.c

311

for_each_plane_id_on_crtc(crtc, plane_id) {

drivers/gpu/drm/i915/display/skl_watermark.c

313

&crtc_state->wm.skl.optimal.planes[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

333

for_each_plane_id_on_crtc(crtc, plane_id) {

drivers/gpu/drm/i915/display/skl_watermark.c

335

&crtc_state->wm.skl.optimal.planes[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

351

enum plane_id plane_id;

drivers/gpu/drm/i915/display/skl_watermark.c

353

for_each_plane_id_on_crtc(crtc, plane_id) {

drivers/gpu/drm/i915/display/skl_watermark.c

355

&crtc_state->wm.skl.optimal.planes[plane_id];

drivers/gpu/drm/i915/display/skl_watermark.c

678

const enum plane_id plane_id,

drivers/gpu/drm/i915/display/skl_watermark.c

686

if (plane_id == PLANE_CURSOR) {

drivers/gpu/drm/i915/display/skl_watermark.c

692

val = intel_de_read(display, PLANE_BUF_CFG(pipe, plane_id));

drivers/gpu/drm/i915/display/skl_watermark.c

696

val = intel_de_read(display, PLANE_MIN_BUF_CFG(pipe, plane_id));

drivers/gpu/drm/i915/display/skl_watermark.c

705

val = intel_de_read(display, PLANE_NV12_BUF_CFG(pipe, plane_id));

drivers/gpu/drm/i915/display/skl_watermark.c

718

enum plane_id plane_id;

drivers/gpu/drm/i915/display/skl_watermark.c

725

for_each_plane_id_on_crtc(crtc, plane_id)

drivers/gpu/drm/i915/display/skl_watermark.c

727

plane_id,

drivers/gpu/drm/i915/display/skl_watermark.c

728

&ddb[plane_id],

drivers/gpu/drm/i915/display/skl_watermark.c

729

&ddb_y[plane_id],

drivers/gpu/drm/i915/display/skl_watermark.c

730

&min_ddb[plane_id],

drivers/gpu/drm/i915/display/skl_watermark.c

731

&interim_ddb[plane_id]);

drivers/gpu/drm/i915/display/skl_watermark.h

11

enum plane_id;

drivers/gpu/drm/i915/display/skl_watermark.h

54

enum plane_id plane_id,

drivers/gpu/drm/i915/display/skl_watermark.h

57

enum plane_id plane_id);

drivers/gpu/drm/i915/gvt/dmabuf.c

258

int plane_id)

drivers/gpu/drm/i915/gvt/dmabuf.c

266

if (plane_id == DRM_PLANE_TYPE_PRIMARY) {

drivers/gpu/drm/i915/gvt/dmabuf.c

296

} else if (plane_id == DRM_PLANE_TYPE_CURSOR) {

drivers/gpu/drm/i915/gvt/dmabuf.c

318

gvt_vgpu_err("invalid plane id:%d\n", plane_id);

drivers/gpu/drm/i915/gvt/handlers.c

1077

enum plane_id plane = REG_50080_TO_PLANE(offset);

drivers/gpu/drm/ingenic/ingenic-drm-drv.c

668

unsigned int width, height, cpp, next_id, plane_id;

drivers/gpu/drm/ingenic/ingenic-drm-drv.c

680

plane_id = !!(priv->soc_info->has_osd && plane != &priv->f0);

drivers/gpu/drm/ingenic/ingenic-drm-drv.c

688

next_id = (priv_state && priv_state->use_palette) ? HWDESC_PALETTE : plane_id;

drivers/gpu/drm/ingenic/ingenic-drm-drv.c

690

hwdesc = &priv->dma_hwdescs->hwdesc[plane_id];

drivers/gpu/drm/kmb/kmb_drv.c

208

int plane_id, dma0_state, dma1_state;

drivers/gpu/drm/kmb/kmb_drv.c

224

for (plane_id = LAYER_0;

drivers/gpu/drm/kmb/kmb_drv.c

225

plane_id < KMB_MAX_PLANES; plane_id++) {

drivers/gpu/drm/kmb/kmb_drv.c

226

if (kmb->plane_status[plane_id].disable) {

drivers/gpu/drm/kmb/kmb_drv.c

229

(plane_id),

drivers/gpu/drm/kmb/kmb_drv.c

233

kmb->plane_status[plane_id].ctrl);

drivers/gpu/drm/kmb/kmb_drv.c

248

kmb->plane_status[plane_id].disable = false;

drivers/gpu/drm/kmb/kmb_plane.c

107

init_disp_cfg = kmb->init_disp_cfg[plane_id];

drivers/gpu/drm/kmb/kmb_plane.c

145

int plane_id = kmb_plane->id;

drivers/gpu/drm/kmb/kmb_plane.c

150

if (WARN_ON(plane_id >= KMB_MAX_PLANES))

drivers/gpu/drm/kmb/kmb_plane.c

153

switch (plane_id) {

drivers/gpu/drm/kmb/kmb_plane.c

155

kmb->plane_status[plane_id].ctrl = LCD_CTRL_VL1_ENABLE;

drivers/gpu/drm/kmb/kmb_plane.c

158

kmb->plane_status[plane_id].ctrl = LCD_CTRL_VL2_ENABLE;

drivers/gpu/drm/kmb/kmb_plane.c

162

kmb->plane_status[plane_id].disable = true;

drivers/gpu/drm/kmb/kmb_plane.c

286

static void config_csc(struct kmb_drm_private *kmb, int plane_id)

drivers/gpu/drm/kmb/kmb_plane.c

289

kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF11(plane_id), csc_coef_lcd[0]);

drivers/gpu/drm/kmb/kmb_plane.c

290

kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF12(plane_id), csc_coef_lcd[1]);

drivers/gpu/drm/kmb/kmb_plane.c

291

kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF13(plane_id), csc_coef_lcd[2]);

drivers/gpu/drm/kmb/kmb_plane.c

292

kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF21(plane_id), csc_coef_lcd[3]);

drivers/gpu/drm/kmb/kmb_plane.c

293

kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF22(plane_id), csc_coef_lcd[4]);

drivers/gpu/drm/kmb/kmb_plane.c

294

kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF23(plane_id), csc_coef_lcd[5]);

drivers/gpu/drm/kmb/kmb_plane.c

295

kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF31(plane_id), csc_coef_lcd[6]);

drivers/gpu/drm/kmb/kmb_plane.c

296

kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF32(plane_id), csc_coef_lcd[7]);

drivers/gpu/drm/kmb/kmb_plane.c

297

kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF33(plane_id), csc_coef_lcd[8]);

drivers/gpu/drm/kmb/kmb_plane.c

298

kmb_write_lcd(kmb, LCD_LAYERn_CSC_OFF1(plane_id), csc_coef_lcd[9]);

drivers/gpu/drm/kmb/kmb_plane.c

299

kmb_write_lcd(kmb, LCD_LAYERn_CSC_OFF2(plane_id), csc_coef_lcd[10]);

drivers/gpu/drm/kmb/kmb_plane.c

300

kmb_write_lcd(kmb, LCD_LAYERn_CSC_OFF3(plane_id), csc_coef_lcd[11]);

drivers/gpu/drm/kmb/kmb_plane.c

305

unsigned char plane_id,

drivers/gpu/drm/kmb/kmb_plane.c

338

kmb_write_lcd(kmb, LCD_LAYERn_ALPHA(plane_id), plane_alpha);

drivers/gpu/drm/kmb/kmb_plane.c

357

unsigned char plane_id;

drivers/gpu/drm/kmb/kmb_plane.c

373

plane_id = kmb_plane->id;

drivers/gpu/drm/kmb/kmb_plane.c

383

init_disp_cfg = &kmb->init_disp_cfg[plane_id];

drivers/gpu/drm/kmb/kmb_plane.c

397

kmb_write_lcd(kmb, LCD_LAYERn_DMA_LEN(plane_id), dma_len);

drivers/gpu/drm/kmb/kmb_plane.c

398

kmb_write_lcd(kmb, LCD_LAYERn_DMA_LEN_SHADOW(plane_id), dma_len);

drivers/gpu/drm/kmb/kmb_plane.c

399

kmb_write_lcd(kmb, LCD_LAYERn_DMA_LINE_VSTRIDE(plane_id),

drivers/gpu/drm/kmb/kmb_plane.c

401

kmb_write_lcd(kmb, LCD_LAYERn_DMA_LINE_WIDTH(plane_id),

drivers/gpu/drm/kmb/kmb_plane.c

405

kmb_write_lcd(kmb, LCD_LAYERn_DMA_START_ADDR(plane_id),

drivers/gpu/drm/kmb/kmb_plane.c

411

kmb_write_lcd(kmb, LCD_LAYERn_DMA_CB_LINE_VSTRIDE(plane_id),

drivers/gpu/drm/kmb/kmb_plane.c

413

kmb_write_lcd(kmb, LCD_LAYERn_DMA_CB_LINE_WIDTH(plane_id),

drivers/gpu/drm/kmb/kmb_plane.c

421

LCD_LAYERn_DMA_START_CR_ADR(plane_id),

drivers/gpu/drm/kmb/kmb_plane.c

425

LCD_LAYERn_DMA_START_CB_ADR(plane_id),

drivers/gpu/drm/kmb/kmb_plane.c

430

LCD_LAYERn_DMA_CR_LINE_VSTRIDE(plane_id),

drivers/gpu/drm/kmb/kmb_plane.c

434

LCD_LAYERn_DMA_CR_LINE_WIDTH(plane_id),

drivers/gpu/drm/kmb/kmb_plane.c

444

LCD_LAYERn_DMA_START_CB_ADR(plane_id),

drivers/gpu/drm/kmb/kmb_plane.c

448

LCD_LAYERn_DMA_START_CR_ADR(plane_id),

drivers/gpu/drm/kmb/kmb_plane.c

453

kmb_write_lcd(kmb, LCD_LAYERn_WIDTH(plane_id), src_w - 1);

drivers/gpu/drm/kmb/kmb_plane.c

454

kmb_write_lcd(kmb, LCD_LAYERn_HEIGHT(plane_id), src_h - 1);

drivers/gpu/drm/kmb/kmb_plane.c

455

kmb_write_lcd(kmb, LCD_LAYERn_COL_START(plane_id), crtc_x);

drivers/gpu/drm/kmb/kmb_plane.c

456

kmb_write_lcd(kmb, LCD_LAYERn_ROW_START(plane_id), crtc_y);

drivers/gpu/drm/kmb/kmb_plane.c

464

config_csc(kmb, plane_id);

drivers/gpu/drm/kmb/kmb_plane.c

467

kmb_plane_set_alpha(kmb, plane->state, plane_id, &val);

drivers/gpu/drm/kmb/kmb_plane.c

469

kmb_write_lcd(kmb, LCD_LAYERn_CFG(plane_id), val);

drivers/gpu/drm/kmb/kmb_plane.c

481

switch (plane_id) {

drivers/gpu/drm/kmb/kmb_plane.c

526

kmb_write_lcd(kmb, LCD_LAYERn_DMA_CFG(plane_id), dma_cfg);

drivers/gpu/drm/kmb/kmb_plane.c

538

kmb_read_lcd(kmb, LCD_LAYERn_DMA_CFG(plane_id)));

drivers/gpu/drm/kmb/kmb_plane.c

73

int plane_id = kmb_plane->id;

drivers/gpu/drm/kmb/kmb_plane.c

77

init_disp_cfg = kmb->init_disp_cfg[plane_id];

drivers/gpu/drm/kmb/kmb_plane.c

99

int plane_id = kmb_plane->id;

drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h

648

TP_PROTO(uint32_t crtc_id, uint32_t plane_id,

drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h

652

TP_ARGS(crtc_id, plane_id, state, pstate, stage_idx,

drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h

656

__field( uint32_t, plane_id )

drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h

670

__entry->plane_id = plane_id;

drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h

686

__entry->crtc_id, __entry->plane_id, __entry->fb_id,

drivers/gpu/drm/sti/sti_mixer.c

239

int plane_id, depth = plane->drm_plane.state->normalized_zpos;

drivers/gpu/drm/sti/sti_mixer.c

245

plane_id = GAM_DEPTH_GDP0_ID;

drivers/gpu/drm/sti/sti_mixer.c

248

plane_id = GAM_DEPTH_GDP1_ID;

drivers/gpu/drm/sti/sti_mixer.c

251

plane_id = GAM_DEPTH_GDP2_ID;

drivers/gpu/drm/sti/sti_mixer.c

254

plane_id = GAM_DEPTH_GDP3_ID;

drivers/gpu/drm/sti/sti_mixer.c

257

plane_id = GAM_DEPTH_VID0_ID;

drivers/gpu/drm/sti/sti_mixer.c

271

if ((val & mask) == plane_id << (3 * i))

drivers/gpu/drm/sti/sti_mixer.c

276

plane_id = plane_id << (3 * depth);

drivers/gpu/drm/sti/sti_mixer.c

281

plane_id, mask);

drivers/gpu/drm/sti/sti_mixer.c

284

val |= plane_id;

drivers/media/platform/nvidia/tegra-vde/h264.c

672

unsigned int plane_id,

drivers/media/platform/nvidia/tegra-vde/h264.c

675

u64 offset = vb->planes[plane_id].data_offset;

drivers/media/platform/nvidia/tegra-vde/h264.c

678

if (offset + min_size > vb2_plane_size(vb, plane_id)) {

drivers/media/platform/nvidia/tegra-vde/h264.c

680

plane_id, vb2_plane_size(vb, plane_id), offset, min_size);

include/uapi/drm/drm_mode.h

287

__u32 plane_id;

include/uapi/drm/drm_mode.h

324

__u32 plane_id;

include/uapi/drm/i915_drm.h

1926

__u32 plane_id;

tools/perf/trace/beauty/include/uapi/drm/i915_drm.h

1926

__u32 plane_id;