drivers/pci/controller/pci-aardvark.c

100

#define PCIE_ISR0_REG (CONTROL_BASE_ADDR + 0x40)

drivers/pci/controller/pci-aardvark.c

102

#define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44)

drivers/pci/controller/pci-aardvark.c

111

#define PCIE_ISR1_REG (CONTROL_BASE_ADDR + 0x48)

drivers/pci/controller/pci-aardvark.c

112

#define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C)

drivers/pci/controller/pci-aardvark.c

117

#define PCIE_MSI_ADDR_LOW_REG (CONTROL_BASE_ADDR + 0x50)

drivers/pci/controller/pci-aardvark.c

118

#define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54)

drivers/pci/controller/pci-aardvark.c

119

#define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58)

drivers/pci/controller/pci-aardvark.c

120

#define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C)

drivers/pci/controller/pci-aardvark.c

122

#define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C)

drivers/pci/controller/pci-aardvark.c

69

#define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0)

drivers/pci/controller/pci-aardvark.c

88

#define PCIE_CORE_CTRL1_REG (CONTROL_BASE_ADDR + 0x4)

drivers/pci/controller/pci-aardvark.c

90

#define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8)

drivers/pci/controller/pci-aardvark.c

96

#define PCIE_CORE_REF_CLK_REG (CONTROL_BASE_ADDR + 0x14)

drivers/pci/controller/pci-aardvark.c

99

#define PCIE_MSG_LOG_REG (CONTROL_BASE_ADDR + 0x30)