drivers/gpu/drm/i915/selftests/i915_vma.c

223

const struct pin_mode *mode,

drivers/gpu/drm/i915/selftests/i915_vma.c

229

const struct pin_mode *mode,

drivers/gpu/drm/i915/selftests/i915_vma.c

243

const struct pin_mode *mode,

drivers/gpu/drm/i915/selftests/i915_vma.c

251

const struct pin_mode *mode,

drivers/gpu/drm/i915/selftests/i915_vma.c

260

const struct pin_mode modes[] = {

drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c

1067

mode = MLX5_GET(mtpps_reg, out, pin_mode);

drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c

718

u8 pin_mode = 0;

drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c

737

pin_mode = MLX5_PIN_MODE_IN;

drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c

755

MLX5_SET(mtpps_reg, in, pin_mode, pin_mode);

drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c

905

u8 pin_mode = 0;

drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c

929

pin_mode = MLX5_PIN_MODE_OUT;

drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c

952

MLX5_SET(mtpps_reg, in, pin_mode, pin_mode);

drivers/net/ethernet/mellanox/mlxsw/reg.h

10339

MLXSW_ITEM32(reg, mtpps, pin_mode, 0x20, 8, 4);

drivers/pinctrl/pinctrl-keembay.c

77

#define KEEMBAY_MUX(pin_mode, pin_function) { \

drivers/pinctrl/pinctrl-keembay.c

78

.mode = pin_mode, \

drivers/pinctrl/pinctrl-keembay.c

941

u8 pin_mode;

drivers/pinctrl/pinctrl-keembay.c

954

pin_mode = *(u8 *)(func->data);

drivers/pinctrl/pinctrl-keembay.c

957

val = u32_replace_bits(val, pin_mode, KEEMBAY_GPIO_MODE_SELECT_MASK);

drivers/spi/spi-armada-3700.c

155

unsigned int pin_mode, bool receiving)

drivers/spi/spi-armada-3700.c

163

switch (pin_mode) {

drivers/spi/spi-armada-3700.c

176

dev_err(&a3700_spi->host->dev, "wrong pin mode %u", pin_mode);

include/linux/mlx5/mlx5_ifc.h

11508

u8 pin_mode[0x4];