drivers/net/phy/adin.c

517

phydev_err(phydev, "invalid adi,phy-output-clock\n");

drivers/net/phy/adin.c

641

phydev_err(phydev,

drivers/net/phy/air_an8801.c

992

phydev_err(phydev, "Cannot initialize LEDs: %d\n", ret);

drivers/net/phy/air_en8811h.c

1069

phydev_err(phydev, "Failed to disable leds: %d\n", ret);

drivers/net/phy/air_en8811h.c

1106

phydev_err(phydev, "Load firmware failed: %d\n", ret);

drivers/net/phy/air_en8811h.c

1276

phydev_err(phydev, "Failed to initialize leds: %d\n", ret);

drivers/net/phy/air_en8811h.c

1323

phydev_err(phydev, "Failed to initialize leds: %d\n", ret);

drivers/net/phy/air_en8811h.c

320

phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,

drivers/net/phy/air_en8811h.c

342

phydev_err(phydev, "MCU not ready: 0x%x\n", reg_value);

drivers/net/phy/air_en8811h.c

383

phydev_err(phydev, "CRC Check is not ready (%u)\n", pbus_value);

drivers/net/phy/air_en8811h.c

553

phydev_err(phydev, "Load firmware failed: %d\n", ret);

drivers/net/phy/air_en8811h.c

830

phydev_err(phydev, "LED mode %d is not supported\n", mode);

drivers/net/phy/air_en8811h.c

837

phydev_err(phydev, "LED%d init failed: %d\n", i, ret);

drivers/net/phy/air_phy_lib.c

149

phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,

drivers/net/phy/air_phy_lib.c

169

phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,

drivers/net/phy/air_phy_lib.c

189

phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,

drivers/net/phy/aquantia/aquantia_firmware.c

141

phydev_err(phydev, "CRC mismatch: calculated 0x%04x PHY 0x%04x\n",

drivers/net/phy/aquantia/aquantia_firmware.c

164

phydev_err(phydev, "bad firmware CRC in firmware\n");

drivers/net/phy/aquantia/aquantia_firmware.c

169

phydev_err(phydev, "bad firmware CRC: file 0x%04x calculated 0x%04x\n",

drivers/net/phy/aquantia/aquantia_firmware.c

177

phydev_err(phydev, "bad primary offset in firmware\n");

drivers/net/phy/aquantia/aquantia_firmware.c

187

phydev_err(phydev, "bad fw_header in firmware\n");

drivers/net/phy/aquantia/aquantia_firmware.c

196

phydev_err(phydev, "bad iram offset in firmware\n");

drivers/net/phy/aquantia/aquantia_firmware.c

203

phydev_err(phydev, "invalid iram size in firmware\n");

drivers/net/phy/aquantia/aquantia_firmware.c

210

phydev_err(phydev, "bad dram offset in firmware\n");

drivers/net/phy/aquantia/aquantia_firmware.c

217

phydev_err(phydev, "invalid dram size in firmware\n");

drivers/net/phy/aquantia/aquantia_firmware.c

226

phydev_err(phydev, "iram size if not aligned to word size. Please report this upstream!\n");

drivers/net/phy/aquantia/aquantia_firmware.c

230

phydev_err(phydev, "invalid iram offset for iram size\n");

drivers/net/phy/aquantia/aquantia_firmware.c

236

phydev_err(phydev, "dram size if not aligned to word size. Please report this upstream!\n");

drivers/net/phy/aquantia/aquantia_firmware.c

240

phydev_err(phydev, "invalid iram offset for iram size\n");

drivers/net/phy/aquantia/aquantia_firmware.c

249

phydev_err(phydev, "invalid version in firmware\n");

drivers/net/phy/aquantia/aquantia_firmware.c

255

phydev_err(phydev, "invalid version in firmware\n");

drivers/net/phy/aquantia/aquantia_firmware.c

315

phydev_err(phydev, "firmware loading failed: %d\n", ret);

drivers/net/phy/aquantia/aquantia_firmware.c

333

phydev_err(phydev, "failed to read firmware-name: %d\n", ret);

drivers/net/phy/aquantia/aquantia_firmware.c

339

phydev_err(phydev, "failed to find FW file %s (%d)\n",

drivers/net/phy/aquantia/aquantia_firmware.c

346

phydev_err(phydev, "firmware loading failed: %d\n", ret);

drivers/net/phy/aquantia/aquantia_main.c

1032

phydev_err(phydev, "timeout: processor-intensive MDIO operation\n");

drivers/net/phy/aquantia/aquantia_main.c

167

phydev_err(phydev, "Reading HW Statistics failed for %s\n",

drivers/net/phy/aquantia/aquantia_main.c

700

phydev_err(phydev, "Failed to read VEND1_GLOBAL_FW_ID: %pe\n",

drivers/net/phy/as21xxx.c

322

phydev_err(phydev, "wrong origin mdio_indirect_status: %x\n", val);

drivers/net/phy/as21xxx.c

366

phydev_err(phydev, "failed to find FW file %s (%d)\n",

drivers/net/phy/as21xxx.c

482

phydev_err(phydev, "failed to send ipc msg for %x: %d\n",

drivers/net/phy/as21xxx.c

562

phydev_err(phydev, "Invalid IPC status on sync parity: %x\n",

drivers/net/phy/as21xxx.c

685

phydev_err(phydev, "Master/Slave resolution failed, maybe conflicting manual settings?\n");

drivers/net/phy/as21xxx.c

687

phydev_err(phydev, "Master/Slave resolution failed\n");

drivers/net/phy/cortina.c

68

phydev_err(phydev, "Error matching phy with %s driver\n",

drivers/net/phy/dp83822.c

655

phydev_err(phydev, "Invalid value for ti,rmii-mode property (%s)\n",

drivers/net/phy/dp83822.c

789

phydev_err(phydev, "LED_0 and COL(GPIO2) cannot be used as LED output at the same time\n");

drivers/net/phy/dp83822.c

795

phydev_err(phydev, "COL(GPIO2) cannot be used as LED output, already used as clock output\n");

drivers/net/phy/dp83822.c

801

phydev_err(phydev, "RX_D3 can only be used as LED output when in RMII mode\n");

drivers/net/phy/dp83822.c

830

phydev_err(phydev,

drivers/net/phy/dp83822.c

851

phydev_err(phydev,

drivers/net/phy/dp83822.c

868

phydev_err(phydev,

drivers/net/phy/dp83867.c

479

phydev_err(phydev,

drivers/net/phy/dp83867.c

565

phydev_err(phydev, "nvmem cell 'io_impedance_ctrl' contents out of range\n");

drivers/net/phy/dp83867.c

594

phydev_err(phydev, "ti,clk-output-sel value %u out of range\n",

drivers/net/phy/dp83867.c

614

phydev_err(phydev,

drivers/net/phy/dp83867.c

624

phydev_err(phydev,

drivers/net/phy/dp83867.c

647

phydev_err(phydev, "tx-fifo-depth value %u out of range\n",

drivers/net/phy/dp83867.c

658

phydev_err(phydev, "rx-fifo-depth value %u out of range\n",

drivers/net/phy/dp83869.c

365

phydev_err(phydev, "Failed to read RX CFG\n");

drivers/net/phy/dp83869.c

382

phydev_err(phydev, "Failed to read RX SOP 1\n");

drivers/net/phy/dp83869.c

392

phydev_err(phydev, "Failed to read RX SOP 2\n");

drivers/net/phy/dp83869.c

402

phydev_err(phydev, "Failed to read RX SOP 3\n");

drivers/net/phy/dp83869.c

474

phydev_err(phydev,

drivers/net/phy/dp83869.c

714

phydev_err(phydev, "selected op-mode is not valid with MII mode\n");

drivers/net/phy/marvell.c

2233

phydev_err(phydev, "Timeout while waiting for cable test to finish\n");

drivers/net/phy/marvell10g.c

840

phydev_err(phydev, "MACTYPE configuration invalid\n");

drivers/net/phy/mediatek/mtk-ge-soc.c

1148

phydev_err(phydev, "cal %d failed\n", cal_item);

drivers/net/phy/mediatek/mtk-ge-soc.c

1175

phydev_err(phydev, "invalid efuse data\n");

drivers/net/phy/mediatek/mtk-ge-soc.c

403

phydev_err(phydev, "Calibration cycle timeout\n");

drivers/net/phy/micrel.c

1385

phydev_err(phydev, "failed to force the phy to master mode\n");

drivers/net/phy/micrel.c

2572

phydev_err(phydev, "invalid led mode: 0x%02x\n",

drivers/net/phy/micrel.c

2726

phydev_err(phydev, "Failed to enable rmii-ref clock\n");

drivers/net/phy/micrel.c

2743

phydev_err(phydev, "Clock rate out of range: %ld\n",

drivers/net/phy/micrel.c

3113

phydev_err(phydev, "Error: phy_write has returned error %d\n",

drivers/net/phy/micrel.c

3134

phydev_err(phydev, "__phy_modify_changed() failed: %pe\n",

drivers/net/phy/micrel.c

4554

phydev_err(phydev, "ptp_clock_register failed %pe\n",

drivers/net/phy/micrel.c

6023

phydev_err(phydev, "ptp_clock_register failed: %pe\n",

drivers/net/phy/micrel.c

674

phydev_err(phydev, "failed to set led mode\n");

drivers/net/phy/micrel.c

693

phydev_err(phydev, "failed to disable broadcast address\n");

drivers/net/phy/micrel.c

713

phydev_err(phydev, "failed to disable NAND tree mode\n");

drivers/net/phy/micrel.c

727

phydev_err(phydev,

drivers/net/phy/microchip.c

434

phydev_err(phydev, "Link change process failed %pe\n", ERR_PTR(ret));

drivers/net/phy/microchip_rds_ptp.c

974

phydev_err(phydev, "RX Timestamp is not valid!\n");

drivers/net/phy/microchip_t1s.c

321

phydev_err(phydev, "PHY reset failed\n");

drivers/net/phy/motorcomm.c

1249

phydev_err(phydev, "Master/Slave resolution failed, maybe conflicting manual settings?\n");

drivers/net/phy/motorcomm.c

1251

phydev_err(phydev, "Master/Slave resolution failed\n");

drivers/net/phy/motorcomm.c

2562

phydev_err(phydev, "Failed to select page: %d\n",

drivers/net/phy/motorcomm.c

2597

phydev_err(phydev, "Failed to select page: %d\n",

drivers/net/phy/motorcomm.c

2788

phydev_err(phydev, "Failed to select page: %d\n",

drivers/net/phy/mscc/mscc_main.c

285

phydev_err(phydev, "Downshift count should be 2,3,4 or 5\n");

drivers/net/phy/mscc/mscc_main.c

444

phydev_err(phydev, "DT %s invalid\n", led);

drivers/net/phy/mscc/mscc_ptp.c

1614

phydev_err(phydev, "Can't get load-save GPIO (%ld)\n",

drivers/net/phy/mxl-gpy.c

415

phydev_err(phydev, "Error: MDIO register access failed: %d\n",

drivers/net/phy/mxl-gpy.c

437

phydev_err(phydev, "Error: MMD register access failed: %d\n",

drivers/net/phy/mxl-gpy.c

603

phydev_err(phydev,

drivers/net/phy/nxp-c45-tja11xx.c

1413

phydev_err(phydev, "delay value smaller than %u\n", MIN_ID_PS);

drivers/net/phy/nxp-c45-tja11xx.c

1418

phydev_err(phydev, "delay value higher than %u\n", MAX_ID_PS);

drivers/net/phy/nxp-c45-tja11xx.c

1507

phydev_err(phydev,

drivers/net/phy/nxp-c45-tja11xx.c

1523

phydev_err(phydev,

drivers/net/phy/nxp-c45-tja11xx.c

1544

phydev_err(phydev, "rgmii mode not supported\n");

drivers/net/phy/nxp-c45-tja11xx.c

1555

phydev_err(phydev, "rgmii-id, rgmii-txid, rgmii-rxid modes are not supported\n");

drivers/net/phy/nxp-c45-tja11xx.c

1568

phydev_err(phydev, "mii mode not supported\n");

drivers/net/phy/nxp-c45-tja11xx.c

1576

phydev_err(phydev, "rev-mii mode not supported\n");

drivers/net/phy/nxp-c45-tja11xx.c

1584

phydev_err(phydev, "rmii mode not supported\n");

drivers/net/phy/nxp-c45-tja11xx.c

1599

phydev_err(phydev, "sgmii mode not supported\n");

drivers/net/phy/nxp-c45-tja11xx.c

1677

phydev_err(phydev, "Failed to enable config\n");

drivers/net/phy/nxp-c45-tja11xx.c

320

phydev_err(phydev, "Trying to read a reg field of size 0.\n");

drivers/net/phy/nxp-c45-tja11xx.c

345

phydev_err(phydev, "Trying to write a reg field of size 0.\n");

drivers/net/phy/nxp-c45-tja11xx.c

362

phydev_err(phydev, "Trying to set a reg field of size different than 1.\n");

drivers/net/phy/nxp-c45-tja11xx.c

373

phydev_err(phydev, "Trying to set a reg field of size different than 1.\n");

drivers/net/phy/phy.c

1342

phydev_err(phydev, "PHY-device data unsafe context\n");

drivers/net/phy/phy.c

540

phydev_err(phydev, "Error while aborting cable test");

drivers/net/phy/phy_device.c

1123

phydev_err(phydev, "failed to initialize\n");

drivers/net/phy/phy_device.c

1129

phydev_err(phydev, "failed to add\n");

drivers/net/phy/phy_device.c

1768

phydev_err(phydev, "failed to get the bus module\n");

drivers/net/phy/phy_device.c

1787

phydev_err(phydev, "failed to get the device driver module\n");

drivers/net/phy/phy_device.c

1836

phydev_err(phydev, "error creating 'phy_standalone' sysfs entry\n");

drivers/net/phy/phy_device.c

2498

phydev_err(phydev, "Master/Slave resolution failed, maybe conflicting manual settings?\n");

drivers/net/phy/phy_device.c

2500

phydev_err(phydev, "Master/Slave resolution failed\n");

drivers/net/phy/phy_device.c

3138

phydev_err(phydev, "Delay %d is out of range\n", delay);

drivers/net/phy/phy_device.c

3160

phydev_err(phydev, "error finding internal delay index for %d\n",

drivers/net/phy/phy_device.c

740

phydev_err(dev, "error %d loading PHY driver module for ID 0x%08lx\n",

drivers/net/phy/qcom/at803x.c

303

phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n");

drivers/net/phy/qcom/at803x.c

311

phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n");

drivers/net/phy/qcom/at803x.c

333

phydev_err(phydev, "invalid qca,clk-out-frequency\n");

drivers/net/phy/qcom/at803x.c

355

phydev_err(phydev, "invalid qca,clk-out-strength\n");

drivers/net/phy/qcom/at803x.c

760

phydev_err(phydev, "failed to register VDDIO regulator\n");

drivers/net/phy/qcom/at803x.c

766

phydev_err(phydev, "failed to register VDDH regulator\n");

drivers/net/phy/qcom/at803x.c

827

phydev_err(phydev, "failed to get VDDIO regulator\n");

drivers/net/phy/qcom/qca808x.c

617

phydev_err(phydev, "PHY polarity is global. Mismatched polarity on different LED\n");

drivers/net/phy/realtek/realtek_main.c

1562

phydev_err(phydev, "MDI swapping disabled, but PHY is already patched.\n");

drivers/net/phy/realtek/realtek_main.c

685

phydev_err(phydev, "Failed to update the TX delay register: %pe\n",

drivers/net/phy/realtek/realtek_main.c

702

phydev_err(phydev, "Failed to update the RX delay register: %pe\n",

drivers/net/phy/rockchip.c

116

phydev_err(phydev, "rockchip_integrated_phy_analog_init err: %d.\n",

include/linux/phy.h

1732

phydev_err(phydev, "%s failed: %d\n", __func__, __ret); \

include/linux/phy.h

1832

phydev_err(phydev, "%s failed: %d\n", __func__, __ret); \

net/ethtool/cabletest.c

53

phydev_err(phydev, "%s: Error %pe\n", __func__, ERR_PTR(err));