drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

178

enum phyd32clk_clock_source phyd32clk)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

281

enum phyd32clk_clock_source phyd32clk)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

84

static enum phyd32clk_clock_source get_phy_mux_symclk(

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

86

enum phyd32clk_clock_source src)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

176

enum phyd32clk_clock_source phyd32clk);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

185

enum phyd32clk_clock_source phyd32clk);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2521

enum phyd32clk_clock_source phyd32clk)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2534

enum phyd32clk_clock_source src)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

453

enum phyd32clk_clock_source phyd32clk)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

207

enum phyd32clk_clock_source phyd32clk);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3048

enum phyd32clk_clock_source phyd32clk;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

788

static enum phyd32clk_clock_source get_phyd32clk_src(struct dc_link *link)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1005

enum phyd32clk_clock_source phyd32clk = PHYD32CLKA;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

941

static enum phyd32clk_clock_source get_phyd32clk_src(struct dc_link *link)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

962

enum phyd32clk_clock_source *phyd32clk,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

255

enum phyd32clk_clock_source phyd32clk);

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

264

enum phyd32clk_clock_source phyd32clk);