drivers/net/ethernet/realtek/r8169_phy_config.c

444

phydev_warn(phydev, "chipset not ready for firmware\n");

drivers/net/phy/adin.c

266

phydev_warn(phydev,

drivers/net/phy/air_en8811h.c

1352

phydev_warn(phydev, "Disabling autoneg is not supported\n");

drivers/net/phy/aquantia/aquantia_main.c

874

phydev_warn(phydev, "unrecognised serdes mode %u\n",

drivers/net/phy/aquantia/aquantia_main.c

893

phydev_warn(phydev, "unrecognized rate adapt mode %u\n",

drivers/net/phy/bcm-phy-lib.c

1136

phydev_warn(phydev, "Unsupported Master/Slave mode\n");

drivers/net/phy/dp83640.c

558

phydev_warn(phydev,

drivers/net/phy/dp83640.c

565

phydev_warn(phydev, "failed to add mc address\n");

drivers/net/phy/dp83640.c

568

phydev_warn(phydev, "failed to delete mc address\n");

drivers/net/phy/intel-xway.c

208

phydev_warn(phydev,

drivers/net/phy/marvell.c

1563

phydev_warn(phydev, "Fast Link Down detection requires EEE to be disabled!\n");

drivers/net/phy/marvell.c

872

phydev_warn(phydev, "Fail to config marvell phy LED.\n");

drivers/net/phy/mediatek/mtk-ge-soc.c

781

phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n",

drivers/net/phy/mediatek/mtk-ge-soc.c

786

phydev_warn(phydev,

drivers/net/phy/micrel.c

1351

phydev_warn(phydev,

drivers/net/phy/microchip.c

112

phydev_warn(phydev, "Failed to Set Register[0x0F82]\n");

drivers/net/phy/microchip.c

120

phydev_warn(phydev, "Failed to Set Register[0x168C]\n");

drivers/net/phy/microchip.c

128

phydev_warn(phydev, "Failed to Set Register[0x17A2]\n");

drivers/net/phy/microchip.c

137

phydev_warn(phydev, "Failed to Set Register[0x16A0]\n");

drivers/net/phy/microchip.c

145

phydev_warn(phydev, "Failed to Set Register[0x16A6]\n");

drivers/net/phy/microchip.c

153

phydev_warn(phydev, "Failed to Set Register[0x16A4]\n");

drivers/net/phy/microchip.c

161

phydev_warn(phydev, "Failed to Set Register[0x16A8]\n");

drivers/net/phy/microchip.c

170

phydev_warn(phydev, "Failed to Set Register[0x0FE8]\n");

drivers/net/phy/microchip.c

179

phydev_warn(phydev, "Failed to Set Register[0x0FFC]\n");

drivers/net/phy/microchip.c

188

phydev_warn(phydev, "Failed to Set Register[0x0FEA]\n");

drivers/net/phy/microchip.c

195

phydev_warn(phydev, "Failed to Set Register[0x1686]\n");

drivers/net/phy/microchip.c

62

phydev_warn(phydev, "Failed to get current page\n");

drivers/net/phy/microchip.c

72

phydev_warn(phydev, "Failed to write TR low data\n");

drivers/net/phy/microchip.c

79

phydev_warn(phydev, "Failed to write TR high data\n");

drivers/net/phy/microchip.c

89

phydev_warn(phydev, "Failed to write data in reg\n");

drivers/net/phy/microchip.c

96

phydev_warn(phydev, "TR Register[0x%X] configuration failed\n",

drivers/net/phy/microchip_rds_ptp.c

90

phydev_warn(phydev, "perout period small, minimum is 200ns\n");

drivers/net/phy/microchip_t1.c

1053

phydev_warn(phydev, "Unsupported Master/Slave mode\n");

drivers/net/phy/motorcomm.c

1141

phydev_warn(phydev, "Freq err:%u\n", freq);

drivers/net/phy/motorcomm.c

1168

phydev_warn(phydev, "Freq err:%u\n", freq);

drivers/net/phy/motorcomm.c

1172

phydev_warn(phydev, "PHY id err\n");

drivers/net/phy/motorcomm.c

1209

phydev_warn(phydev, "Freq err:%u\n", freq);

drivers/net/phy/motorcomm.c

1938

phydev_warn(phydev, "Modify TX_CLK_SEL err:%d\n", ret);

drivers/net/phy/motorcomm.c

2120

phydev_warn(phydev, "Unsupported Master/Slave mode\n");

drivers/net/phy/motorcomm.c

2919

phydev_warn(phydev, "phy speed err :%d\n", phydev->speed);

drivers/net/phy/motorcomm.c

876

phydev_warn(phydev, "Unsupported value %d for %s using default (%u)\n",

drivers/net/phy/nxp-c45-tja11xx.c

692

phydev_warn(priv->phydev,

drivers/net/phy/nxp-c45-tja11xx.c

785

phydev_warn(phydev, "The period can be set only to 1 second.");

drivers/net/phy/nxp-c45-tja11xx.c

791

phydev_warn(phydev, "The start time is not configurable. Should be set to 0 seconds and 0 nanoseconds.");

drivers/net/phy/nxp-c45-tja11xx.c

797

phydev_warn(phydev, "The phase can be set only to 0 or 500000000 nanoseconds.");

drivers/net/phy/nxp-tja11xx.c

259

phydev_warn(phydev, "Unsupported Master/Slave mode\n");

drivers/net/phy/phy-c45.c

1559

phydev_warn(phydev, "At least some EEE link modes are not supported.\n");

drivers/net/phy/phy-c45.c

235

phydev_warn(phydev, "Unsupported Master/Slave mode\n");

drivers/net/phy/phy-c45.c

98

phydev_warn(phydev, "Unsupported Master/Slave mode\n");

drivers/net/phy/phy-core.c

309

phydev_warn(phydev, "Unknown master-slave mode %s\n", master);

drivers/net/phy/phy-core.c

389

phydev_warn(phydev, "Downshift occurred from negotiated speed %s to actual speed %s, check cabling!\n",

drivers/net/phy/phy.c

1487

phydev_warn(phydev, "Error %d requesting IRQ %d, falling back to polling\n",

drivers/net/phy/phy.c

1492

phydev_warn(phydev, "Can't enable interrupt, falling back to polling\n");

drivers/net/phy/phy_device.c

2202

phydev_warn(phydev, "Unsupported Master/Slave mode\n");

drivers/net/phy/phy_device.c

2926

phydev_warn(phydev, "Failed to disable autonomous EEE: %pe\n",

drivers/net/phy/realtek/realtek_main.c

2510

phydev_warn(phydev, "Unsupported Master/Slave mode\n");