drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

40

pg_cntl_dcn->pg_cntl_shift->field_name, pg_cntl_dcn->pg_cntl_mask->field_name

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

543

const struct pg_cntl_mask *pg_cntl_mask)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

559

pg_cntl_dcn->pg_cntl_mask = pg_cntl_mask;

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

169

const struct pg_cntl_mask *pg_cntl_mask;

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

191

const struct pg_cntl_mask *pg_cntl_mask);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

18

pg_cntl_dcn->pg_cntl_shift->field_name, pg_cntl_dcn->pg_cntl_mask->field_name

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

624

const struct pg_cntl_mask *pg_cntl_mask)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

640

pg_cntl_dcn->pg_cntl_mask = pg_cntl_mask;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.h

233

const struct pg_cntl_mask *pg_cntl_mask;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.h

257

const struct pg_cntl_mask *pg_cntl_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2183

pool->base.pg_cntl = pg_cntl35_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

579

static const struct pg_cntl_mask pg_cntl_mask = {

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2155

pool->base.pg_cntl = pg_cntl35_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

559

static const struct pg_cntl_mask pg_cntl_mask = {

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2153

pool->base.pg_cntl = pg_cntl35_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

566

static const struct pg_cntl_mask pg_cntl_mask = {

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2228

pool->base.pg_cntl = pg_cntl42_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

499

static const struct pg_cntl_mask pg_cntl_mask = {

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2180

pool->base.pg_cntl = pg_cntl42_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

523

static const struct pg_cntl_mask pg_cntl_mask = {