drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

40

pg_cntl_dcn->pg_cntl_shift->field_name, pg_cntl_dcn->pg_cntl_mask->field_name

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

542

const struct pg_cntl_shift *pg_cntl_shift,

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

558

pg_cntl_dcn->pg_cntl_shift = pg_cntl_shift;

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

168

const struct pg_cntl_shift *pg_cntl_shift;

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

190

const struct pg_cntl_shift *pg_cntl_shift,

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

18

pg_cntl_dcn->pg_cntl_shift->field_name, pg_cntl_dcn->pg_cntl_mask->field_name

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

623

const struct pg_cntl_shift *pg_cntl_shift,

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

639

pg_cntl_dcn->pg_cntl_shift = pg_cntl_shift;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.h

232

const struct pg_cntl_shift *pg_cntl_shift;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.h

256

const struct pg_cntl_shift *pg_cntl_shift,

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2183

pool->base.pg_cntl = pg_cntl35_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

575

static const struct pg_cntl_shift pg_cntl_shift = {

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2155

pool->base.pg_cntl = pg_cntl35_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

555

static const struct pg_cntl_shift pg_cntl_shift = {

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2153

pool->base.pg_cntl = pg_cntl35_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

562

static const struct pg_cntl_shift pg_cntl_shift = {

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2228

pool->base.pg_cntl = pg_cntl42_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

495

static const struct pg_cntl_shift pg_cntl_shift = {

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2180

pool->base.pg_cntl = pg_cntl42_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

519

static const struct pg_cntl_shift pg_cntl_shift = {