drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1979

struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2012

if (pg_cntl != NULL)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2013

pg_cntl->funcs->dsc_pg_control(pg_cntl, dsc->inst, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

122

if (dc->debug.enable_pg_cntl_debug_logs && dc->res_pool->pg_cntl) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1228

struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

123

if (dc->res_pool->pg_cntl->funcs->print_pg_status)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1230

if (!pg_cntl)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1236

if (pg_cntl->funcs->hpo_pg_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1237

pg_cntl->funcs->hpo_pg_control(pg_cntl, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

124

dc->res_pool->pg_cntl->funcs->print_pg_status(dc->res_pool->pg_cntl, debug_func, debug_log);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1244

if (pg_cntl->funcs->hubp_dpp_pg_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1245

pg_cntl->funcs->hubp_dpp_pg_control(pg_cntl, pipe_idx, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1251

if (pg_cntl->funcs->dsc_pg_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1252

pg_cntl->funcs->dsc_pg_control(pg_cntl, i, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1258

if (pg_cntl->funcs->dsc_pg_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1259

pg_cntl->funcs->dsc_pg_control(pg_cntl, i, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1264

if (pg_cntl->funcs->hubp_dpp_pg_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1265

pg_cntl->funcs->hubp_dpp_pg_control(pg_cntl, i, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1271

if (pg_cntl->funcs->plane_otg_pg_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1272

pg_cntl->funcs->plane_otg_pg_control(pg_cntl, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1305

struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1307

if (!pg_cntl)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1313

if (pg_cntl->funcs->plane_otg_pg_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1314

pg_cntl->funcs->plane_otg_pg_control(pg_cntl, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1319

if (pg_cntl->funcs->dsc_pg_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1320

pg_cntl->funcs->dsc_pg_control(pg_cntl, i, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1327

if (pg_cntl->funcs->hubp_dpp_pg_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1328

pg_cntl->funcs->hubp_dpp_pg_control(pg_cntl, i, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1333

if (pg_cntl->funcs->dsc_pg_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1334

pg_cntl->funcs->dsc_pg_control(pg_cntl, i, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1339

if (pg_cntl->funcs->hpo_pg_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1340

pg_cntl->funcs->hpo_pg_control(pg_cntl, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1347

struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1349

if (!pg_cntl)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

322

if (dc->res_pool->pg_cntl) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

323

if (dc->res_pool->pg_cntl->funcs->init_pg_status)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

324

dc->res_pool->pg_cntl->funcs->init_pg_status(dc->res_pool->pg_cntl);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

644

struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

787

if (pg_cntl != NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

788

if (pg_cntl->funcs->dsc_pg_control != NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

828

pg_cntl->funcs->dsc_pg_control(pg_cntl, dc->res_pool->dscs[i]->inst, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

103

struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

105

if (!pg_cntl || dc->debug.ignore_pg)

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

110

if (pg_cntl->funcs->dsc_pg_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

111

pg_cntl->funcs->dsc_pg_control(pg_cntl, i, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

116

if (pg_cntl->funcs->hubp_dpp_pg_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

117

pg_cntl->funcs->hubp_dpp_pg_control(pg_cntl, i, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

124

if (pg_cntl->funcs->plane_otg_pg_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

125

pg_cntl->funcs->plane_otg_pg_control(pg_cntl, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

156

struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

158

if (!pg_cntl || dc->debug.ignore_pg)

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

165

if (pg_cntl->funcs->plane_otg_pg_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

166

pg_cntl->funcs->plane_otg_pg_control(pg_cntl, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

173

if (pg_cntl->funcs->hubp_dpp_pg_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

174

pg_cntl->funcs->hubp_dpp_pg_control(pg_cntl, i, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

178

if (pg_cntl->funcs->dsc_pg_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

179

pg_cntl->funcs->dsc_pg_control(pg_cntl, i, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1052

if (dc->res_pool->pg_cntl->funcs->optc_pg_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1053

dc->res_pool->pg_cntl->funcs->optc_pg_control(dc->res_pool->pg_cntl, i, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1256

struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1259

if (!pg_cntl)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1265

if (pg_cntl->funcs->hpo_pg_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1266

pg_cntl->funcs->hpo_pg_control(pg_cntl, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1272

if (pg_cntl->funcs->hubp_dpp_pg_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1273

pg_cntl->funcs->hubp_dpp_pg_control(pg_cntl, i, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1278

if (pg_cntl->funcs->mem_pg_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1279

pg_cntl->funcs->mem_pg_control(pg_cntl, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1284

if (pg_cntl->funcs->dsc_pg_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1285

pg_cntl->funcs->dsc_pg_control(pg_cntl, i, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1299

if (pg_cntl->funcs->plane_otg_pg_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1300

pg_cntl->funcs->plane_otg_pg_control(pg_cntl, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1304

if (pg_cntl->funcs->dio_pg_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1305

pg_cntl->funcs->dio_pg_control(pg_cntl, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1312

if (pg_cntl->funcs->io_clk_pg_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1313

pg_cntl->funcs->io_clk_pg_control(pg_cntl, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1345

struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1348

if (!pg_cntl)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1356

if (pg_cntl->funcs->io_clk_pg_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1357

pg_cntl->funcs->io_clk_pg_control(pg_cntl, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1361

if (pg_cntl->funcs->dio_pg_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1362

pg_cntl->funcs->dio_pg_control(pg_cntl, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1374

if (pg_cntl->funcs->plane_otg_pg_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1375

pg_cntl->funcs->plane_otg_pg_control(pg_cntl, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1380

if (pg_cntl->funcs->dsc_pg_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1381

pg_cntl->funcs->dsc_pg_control(pg_cntl, i, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1386

if (pg_cntl->funcs->mem_pg_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1387

pg_cntl->funcs->mem_pg_control(pg_cntl, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1393

if (pg_cntl->funcs->hubp_dpp_pg_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1394

pg_cntl->funcs->hubp_dpp_pg_control(pg_cntl, i, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1398

if (pg_cntl->funcs->hpo_pg_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1399

pg_cntl->funcs->hpo_pg_control(pg_cntl, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1406

struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1408

if (!pg_cntl)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

291

if (dc->res_pool->pg_cntl) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

292

if (dc->res_pool->pg_cntl->funcs->init_pg_status)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

293

dc->res_pool->pg_cntl->funcs->init_pg_status(dc->res_pool->pg_cntl);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

56

if (dc->debug.enable_pg_cntl_debug_logs && dc->res_pool->pg_cntl) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

57

if (dc->res_pool->pg_cntl->funcs->print_pg_status)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

58

dc->res_pool->pg_cntl->funcs->print_pg_status(dc->res_pool->pg_cntl, debug_func, debug_log);

drivers/gpu/drm/amd/display/dc/inc/core_types.h

325

struct pg_cntl *pg_cntl;

drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h

40

void (*dsc_pg_control)(struct pg_cntl *pg_cntl, unsigned int dsc_inst, bool power_on);

drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h

41

void (*hubp_dpp_pg_control)(struct pg_cntl *pg_cntl, unsigned int hubp_dpp_inst, bool power_on);

drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h

42

void (*hpo_pg_control)(struct pg_cntl *pg_cntl, bool power_on);

drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h

43

void (*io_clk_pg_control)(struct pg_cntl *pg_cntl, bool power_on);

drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h

44

void (*plane_otg_pg_control)(struct pg_cntl *pg_cntl, bool power_on);

drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h

45

void (*mpcc_pg_control)(struct pg_cntl *pg_cntl, unsigned int mpcc_inst, bool power_on);

drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h

46

void (*opp_pg_control)(struct pg_cntl *pg_cntl, unsigned int opp_inst, bool power_on);

drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h

47

void (*optc_pg_control)(struct pg_cntl *pg_cntl, unsigned int optc_inst, bool power_on);

drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h

48

void (*dwb_pg_control)(struct pg_cntl *pg_cntl, bool power_on);

drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h

49

void (*mem_pg_control)(struct pg_cntl *pg_cntl, bool power_on);

drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h

50

void (*dio_pg_control)(struct pg_cntl *pg_cntl, bool power_on);

drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h

51

void (*init_pg_status)(struct pg_cntl *pg_cntl);

drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h

52

void (*print_pg_status)(struct pg_cntl *pg_cntl, const char *debug_func, const char *debug_log);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

142

pg_cntl->pg_pipe_res_enable[PG_DSC][dsc_inst] = power_on;

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

145

static bool pg_cntl35_hubp_dpp_pg_status(struct pg_cntl *pg_cntl, unsigned int hubp_dpp_inst)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

147

struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

175

void pg_cntl35_hubp_dpp_pg_control(struct pg_cntl *pg_cntl, unsigned int hubp_dpp_inst, bool power_on)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

177

struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

182

bool skip_pg = pg_cntl->ctx->dc->debug.ignore_pg ||

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

183

pg_cntl->ctx->dc->debug.disable_hubp_power_gate ||

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

184

pg_cntl->ctx->dc->debug.disable_dpp_power_gate ||

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

185

pg_cntl->ctx->dc->idle_optimizations_allowed;

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

190

block_enabled = pg_cntl35_hubp_dpp_pg_status(pg_cntl, hubp_dpp_inst);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

233

pg_cntl->pg_pipe_res_enable[PG_HUBP][hubp_dpp_inst] = power_on;

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

234

pg_cntl->pg_pipe_res_enable[PG_DPP][hubp_dpp_inst] = power_on;

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

238

static bool pg_cntl35_hpo_pg_status(struct pg_cntl *pg_cntl)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

240

struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

249

void pg_cntl35_hpo_pg_control(struct pg_cntl *pg_cntl, bool power_on)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

251

struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

258

if (pg_cntl->ctx->dc->debug.ignore_pg ||

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

259

pg_cntl->ctx->dc->debug.disable_hpo_power_gate ||

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

260

pg_cntl->ctx->dc->idle_optimizations_allowed)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

263

block_enabled = pg_cntl35_hpo_pg_status(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

283

pg_cntl->pg_res_enable[PG_HPO] = power_on;

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

286

static bool pg_cntl35_io_clk_status(struct pg_cntl *pg_cntl)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

288

struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

297

void pg_cntl35_io_clk_pg_control(struct pg_cntl *pg_cntl, bool power_on)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

299

struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

306

if (pg_cntl->ctx->dc->debug.ignore_pg ||

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

307

pg_cntl->ctx->dc->idle_optimizations_allowed)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

310

block_enabled = pg_cntl35_io_clk_status(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

32

#define TO_DCN_PG_CNTL(pg_cntl)\

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

33

container_of(pg_cntl, struct dcn_pg_cntl, base)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

331

pg_cntl->pg_res_enable[PG_DCCG] = power_on;

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

332

pg_cntl->pg_res_enable[PG_DIO] = power_on;

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

333

pg_cntl->pg_res_enable[PG_DCIO] = power_on;

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

336

static bool pg_cntl35_plane_otg_status(struct pg_cntl *pg_cntl)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

338

struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

347

void pg_cntl35_mpcc_pg_control(struct pg_cntl *pg_cntl,

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

350

if (pg_cntl->ctx->dc->idle_optimizations_allowed)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

354

pg_cntl->pg_pipe_res_enable[PG_MPCC][mpcc_inst] = power_on;

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

357

void pg_cntl35_opp_pg_control(struct pg_cntl *pg_cntl,

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

360

if (pg_cntl->ctx->dc->idle_optimizations_allowed)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

364

pg_cntl->pg_pipe_res_enable[PG_OPP][opp_inst] = power_on;

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

367

void pg_cntl35_optc_pg_control(struct pg_cntl *pg_cntl,

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

370

if (pg_cntl->ctx->dc->idle_optimizations_allowed)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

374

pg_cntl->pg_pipe_res_enable[PG_OPTC][optc_inst] = power_on;

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

377

void pg_cntl35_plane_otg_pg_control(struct pg_cntl *pg_cntl, bool power_on)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

379

struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

388

if (pg_cntl->ctx->dc->debug.ignore_pg ||

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

389

pg_cntl->ctx->dc->debug.disable_optc_power_gate ||

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

390

pg_cntl->ctx->dc->idle_optimizations_allowed)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

393

block_enabled = pg_cntl35_plane_otg_status(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

402

for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

403

struct pipe_ctx *pipe_ctx = &pg_cntl->ctx->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

410

if (pg_cntl->pg_pipe_res_enable[PG_MPCC][i])

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

413

if (pg_cntl->pg_pipe_res_enable[PG_OPP][i])

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

416

if (pg_cntl->pg_pipe_res_enable[PG_OPTC][i])

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

422

|| !all_stream_disabled || pg_cntl->pg_res_enable[PG_DWB])

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

434

for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

435

pg_cntl->pg_pipe_res_enable[PG_MPCC][i] = power_on;

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

436

pg_cntl->pg_pipe_res_enable[PG_OPP][i] = power_on;

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

437

pg_cntl->pg_pipe_res_enable[PG_OPTC][i] = power_on;

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

439

pg_cntl->pg_res_enable[PG_DWB] = power_on;

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

442

void pg_cntl35_dwb_pg_control(struct pg_cntl *pg_cntl, bool power_on)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

444

if (pg_cntl->ctx->dc->idle_optimizations_allowed)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

447

pg_cntl->pg_res_enable[PG_DWB] = power_on;

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

45

pg_cntl->ctx->logger

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

450

static bool pg_cntl35_mem_status(struct pg_cntl *pg_cntl)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

452

struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

461

void pg_cntl35_init_pg_status(struct pg_cntl *pg_cntl)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

466

pg_cntl->pg_res_enable[PG_HPO] = pg_cntl35_hpo_pg_status(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

468

block_enabled = pg_cntl35_io_clk_status(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

469

pg_cntl->pg_res_enable[PG_DCCG] = block_enabled;

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

47

static bool pg_cntl35_dsc_pg_status(struct pg_cntl *pg_cntl, unsigned int dsc_inst)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

470

pg_cntl->pg_res_enable[PG_DIO] = block_enabled;

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

471

pg_cntl->pg_res_enable[PG_DCIO] = block_enabled;

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

473

block_enabled = pg_cntl35_mem_status(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

474

pg_cntl->pg_res_enable[PG_DCHUBBUB] = block_enabled;

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

475

pg_cntl->pg_res_enable[PG_DCHVM] = block_enabled;

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

477

for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

478

block_enabled = pg_cntl35_hubp_dpp_pg_status(pg_cntl, i);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

479

pg_cntl->pg_pipe_res_enable[PG_HUBP][i] = block_enabled;

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

480

pg_cntl->pg_pipe_res_enable[PG_DPP][i] = block_enabled;

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

482

block_enabled = pg_cntl35_dsc_pg_status(pg_cntl, i);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

483

pg_cntl->pg_pipe_res_enable[PG_DSC][i] = block_enabled;

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

486

block_enabled = pg_cntl35_plane_otg_status(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

487

for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

488

pg_cntl->pg_pipe_res_enable[PG_MPCC][i] = block_enabled;

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

489

pg_cntl->pg_pipe_res_enable[PG_OPP][i] = block_enabled;

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

49

struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

490

pg_cntl->pg_pipe_res_enable[PG_OPTC][i] = block_enabled;

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

492

pg_cntl->pg_res_enable[PG_DWB] = block_enabled;

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

495

static void pg_cntl35_print_pg_status(struct pg_cntl *pg_cntl, const char *debug_func, const char *debug_log)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

504

block_enabled = pg_cntl35_io_clk_status(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

507

block_enabled = pg_cntl35_mem_status(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

510

block_enabled = pg_cntl35_plane_otg_status(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

513

block_enabled = pg_cntl35_hpo_pg_status(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

516

for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

517

block_enabled = pg_cntl35_hubp_dpp_pg_status(pg_cntl, i);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

52

if (pg_cntl->ctx->dc->debug.ignore_pg)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

520

block_enabled = pg_cntl35_dsc_pg_status(pg_cntl, i);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

539

struct pg_cntl *pg_cntl35_create(

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

546

struct pg_cntl *base;

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

567

void dcn_pg_cntl_destroy(struct pg_cntl **pg_cntl)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

569

struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(*pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

572

*pg_cntl = NULL;

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

76

void pg_cntl35_dsc_pg_control(struct pg_cntl *pg_cntl, unsigned int dsc_inst, bool power_on)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

78

struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

83

bool skip_pg = pg_cntl->ctx->dc->debug.ignore_pg ||

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

84

pg_cntl->ctx->dc->debug.disable_dsc_power_gate ||

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

85

pg_cntl->ctx->dc->idle_optimizations_allowed;

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

90

block_enabled = pg_cntl35_dsc_pg_status(pg_cntl, dsc_inst);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

166

struct pg_cntl base;

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

172

void pg_cntl35_dsc_pg_control(struct pg_cntl *pg_cntl, unsigned int dsc_inst, bool power_on);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

173

void pg_cntl35_hubp_dpp_pg_control(struct pg_cntl *pg_cntl,

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

175

void pg_cntl35_hpo_pg_control(struct pg_cntl *pg_cntl, bool power_on);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

176

void pg_cntl35_io_clk_pg_control(struct pg_cntl *pg_cntl, bool power_on);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

177

void pg_cntl35_plane_otg_pg_control(struct pg_cntl *pg_cntl, bool power_on);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

178

void pg_cntl35_mpcc_pg_control(struct pg_cntl *pg_cntl,

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

180

void pg_cntl35_opp_pg_control(struct pg_cntl *pg_cntl,

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

182

void pg_cntl35_optc_pg_control(struct pg_cntl *pg_cntl,

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

184

void pg_cntl35_dwb_pg_control(struct pg_cntl *pg_cntl, bool power_on);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

185

void pg_cntl35_init_pg_status(struct pg_cntl *pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

187

struct pg_cntl *pg_cntl35_create(

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

193

void dcn_pg_cntl_destroy(struct pg_cntl **pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

10

#define TO_DCN_PG_CNTL(pg_cntl)\

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

11

container_of(pg_cntl, struct dcn_pg_cntl, base)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

127

if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

128

pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, true);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

132

pg_cntl->pg_pipe_res_enable[PG_DSC][dsc_inst] = power_on;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

134

if (pg_cntl->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on) {

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

136

pg_cntl->ctx->dc->res_pool->dccg->funcs->disable_dsc(

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

137

pg_cntl->ctx->dc->res_pool->dccg, dsc_inst);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

141

static bool pg_cntl42_hubp_dpp_pg_status(struct pg_cntl *pg_cntl, unsigned int hubp_dpp_inst)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

143

struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

171

void pg_cntl42_hubp_dpp_pg_control(struct pg_cntl *pg_cntl, unsigned int hubp_dpp_inst, bool power_on)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

173

struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

178

bool skip_pg = pg_cntl->ctx->dc->debug.ignore_pg ||

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

179

pg_cntl->ctx->dc->debug.disable_hubp_power_gate ||

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

180

pg_cntl->ctx->dc->debug.disable_dpp_power_gate ||

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

181

pg_cntl->ctx->dc->idle_optimizations_allowed;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

186

block_enabled = pg_cntl42_hubp_dpp_pg_status(pg_cntl, hubp_dpp_inst);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

200

if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

201

pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, false);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

23

pg_cntl->ctx->logger

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

231

if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

232

pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, true);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

238

pg_cntl->pg_pipe_res_enable[PG_HUBP][hubp_dpp_inst] = power_on;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

239

pg_cntl->pg_pipe_res_enable[PG_DPP][hubp_dpp_inst] = power_on;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

243

static bool pg_cntl42_hpo_pg_status(struct pg_cntl *pg_cntl)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

245

struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

25

static bool pg_cntl42_dsc_pg_status(struct pg_cntl *pg_cntl, unsigned int dsc_inst)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

254

void pg_cntl42_hpo_pg_control(struct pg_cntl *pg_cntl, bool power_on)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

256

struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

263

bool skip_pg = pg_cntl->ctx->dc->debug.ignore_pg ||

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

264

pg_cntl->ctx->dc->debug.disable_hpo_power_gate ||

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

265

pg_cntl->ctx->dc->idle_optimizations_allowed;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

269

block_enabled = pg_cntl42_hpo_pg_status(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

27

struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

286

if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

287

pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, false);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

293

if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

294

pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, true);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

296

pg_cntl->pg_res_enable[PG_HPO] = power_on;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

299

static bool pg_cntl42_io_clk_status(struct pg_cntl *pg_cntl)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

301

struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

310

void pg_cntl42_io_clk_pg_control(struct pg_cntl *pg_cntl, bool power_on)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

312

struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

319

bool skip_pg = pg_cntl->ctx->dc->debug.ignore_pg ||

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

320

pg_cntl->ctx->dc->idle_optimizations_allowed ||

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

321

pg_cntl->ctx->dc->debug.disable_io_clk_power_gate;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

326

block_enabled = pg_cntl42_io_clk_status(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

340

if (!pg_cntl->pg_res_enable[PG_DCCG] || !pg_cntl->pg_res_enable[PG_DCIO] || !pg_cntl->pg_res_enable[PG_DCOH])

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

351

pg_cntl->pg_res_enable[PG_DCCG] = power_on;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

352

pg_cntl->pg_res_enable[PG_DCOH] = power_on;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

353

pg_cntl->pg_res_enable[PG_DCIO] = power_on;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

356

static bool pg_cntl42_plane_otg_status(struct pg_cntl *pg_cntl)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

358

struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

367

void pg_cntl42_mpcc_pg_control(struct pg_cntl *pg_cntl,

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

370

if (pg_cntl->ctx->dc->idle_optimizations_allowed)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

374

pg_cntl->pg_pipe_res_enable[PG_MPCC][mpcc_inst] = power_on;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

377

void pg_cntl42_opp_pg_control(struct pg_cntl *pg_cntl,

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

380

if (pg_cntl->ctx->dc->idle_optimizations_allowed)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

384

pg_cntl->pg_pipe_res_enable[PG_OPP][opp_inst] = power_on;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

387

void pg_cntl42_optc_pg_control(struct pg_cntl *pg_cntl,

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

391

if (pg_cntl->ctx->dc->idle_optimizations_allowed)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

395

pg_cntl->pg_pipe_res_enable[PG_OPTC][optc_inst] = power_on;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

397

static bool pg_cntl42_mem_status(struct pg_cntl *pg_cntl)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

399

struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

408

void pg_cntl42_mem_pg_control(struct pg_cntl *pg_cntl, bool power_on)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

410

struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

417

bool skip_pg = pg_cntl->ctx->dc->debug.ignore_pg ||

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

418

pg_cntl->ctx->dc->idle_optimizations_allowed ||

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

419

pg_cntl->ctx->dc->debug.disable_mem_power_gate;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

424

block_enabled = pg_cntl42_mem_status(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

438

if (!pg_cntl->pg_res_enable[PG_DCHUBBUB] || !pg_cntl->pg_res_enable[PG_DCHVM])

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

449

pg_cntl->pg_res_enable[PG_DCHUBBUB] = power_on;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

450

pg_cntl->pg_res_enable[PG_DCHVM] = power_on;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

452

static bool pg_cntl42_dio_pg_status(struct pg_cntl *pg_cntl)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

454

struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

463

void pg_cntl42_dio_pg_control(struct pg_cntl *pg_cntl, bool power_on)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

465

struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

471

bool skip_pg = pg_cntl->ctx->dc->debug.ignore_pg ||

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

472

pg_cntl->ctx->dc->idle_optimizations_allowed ||

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

473

pg_cntl->ctx->dc->debug.disable_dio_power_gate;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

477

block_enabled = pg_cntl42_dio_pg_status(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

490

if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

491

pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, false);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

498

if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

499

pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, true);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

501

pg_cntl->pg_res_enable[PG_DIO] = power_on;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

505

void pg_cntl42_plane_otg_pg_control(struct pg_cntl *pg_cntl, bool power_on)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

507

struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

51

void pg_cntl42_dsc_pg_control(struct pg_cntl *pg_cntl, unsigned int dsc_inst, bool power_on)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

516

if (pg_cntl->ctx->dc->debug.ignore_pg ||

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

517

pg_cntl->ctx->dc->debug.disable_optc_power_gate ||

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

518

pg_cntl->ctx->dc->idle_optimizations_allowed)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

521

block_enabled = pg_cntl42_plane_otg_status(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

53

struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

530

for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

531

struct pipe_ctx *pipe_ctx = &pg_cntl->ctx->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

538

if (pg_cntl->pg_pipe_res_enable[PG_MPCC][i])

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

541

if (pg_cntl->pg_pipe_res_enable[PG_OPP][i])

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

544

if (pg_cntl->pg_pipe_res_enable[PG_OPTC][i])

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

562

for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

563

pg_cntl->pg_pipe_res_enable[PG_MPCC][i] = power_on;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

564

pg_cntl->pg_pipe_res_enable[PG_OPP][i] = power_on;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

565

pg_cntl->pg_pipe_res_enable[PG_OPTC][i] = power_on;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

570

void pg_cntl42_init_pg_status(struct pg_cntl *pg_cntl)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

575

pg_cntl->pg_res_enable[PG_HPO] = pg_cntl42_hpo_pg_status(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

577

block_enabled = pg_cntl42_io_clk_status(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

578

pg_cntl->pg_res_enable[PG_DCCG] = block_enabled;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

579

pg_cntl->pg_res_enable[PG_DCIO] = block_enabled;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

580

pg_cntl->pg_res_enable[PG_DCOH] = block_enabled;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

582

block_enabled = pg_cntl42_dio_pg_status(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

583

pg_cntl->pg_res_enable[PG_DIO] = block_enabled;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

585

block_enabled = pg_cntl42_mem_status(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

586

pg_cntl->pg_res_enable[PG_DCHUBBUB] = block_enabled;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

587

pg_cntl->pg_res_enable[PG_DCHVM] = block_enabled;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

589

for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

590

block_enabled = pg_cntl42_hubp_dpp_pg_status(pg_cntl, i);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

591

pg_cntl->pg_pipe_res_enable[PG_HUBP][i] = block_enabled;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

592

pg_cntl->pg_pipe_res_enable[PG_DPP][i] = block_enabled;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

594

block_enabled = pg_cntl42_dsc_pg_status(pg_cntl, i);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

595

pg_cntl->pg_pipe_res_enable[PG_DSC][i] = block_enabled;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

598

block_enabled = pg_cntl42_plane_otg_status(pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

599

for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

60

if (pg_cntl->ctx->dc->res_pool->dccg->funcs->enable_dsc && power_on)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

600

pg_cntl->pg_pipe_res_enable[PG_MPCC][i] = block_enabled;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

601

pg_cntl->pg_pipe_res_enable[PG_OPP][i] = block_enabled;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

602

pg_cntl->pg_pipe_res_enable[PG_OPTC][i] = block_enabled;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

61

pg_cntl->ctx->dc->res_pool->dccg->funcs->enable_dsc(

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

62

pg_cntl->ctx->dc->res_pool->dccg, dsc_inst);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

620

struct pg_cntl *pg_cntl42_create(

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

627

struct pg_cntl *base;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

64

bool skip_pg = pg_cntl->ctx->dc->debug.ignore_pg ||

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

648

void dcn42_pg_cntl_destroy(struct pg_cntl **pg_cntl)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

65

pg_cntl->ctx->dc->debug.disable_dsc_power_gate ||

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

650

struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(*pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

653

*pg_cntl = NULL;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

66

pg_cntl->ctx->dc->idle_optimizations_allowed;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

71

block_enabled = pg_cntl42_dsc_pg_status(pg_cntl, dsc_inst);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

85

if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

86

pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, false);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.h

230

struct pg_cntl base;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.h

236

void pg_cntl42_dsc_pg_control(struct pg_cntl *pg_cntl, unsigned int dsc_inst, bool power_on);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.h

237

void pg_cntl42_hubp_dpp_pg_control(struct pg_cntl *pg_cntl,

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.h

239

void pg_cntl42_hpo_pg_control(struct pg_cntl *pg_cntl, bool power_on);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.h

240

void pg_cntl42_io_clk_pg_control(struct pg_cntl *pg_cntl, bool power_on);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.h

241

void pg_cntl42_plane_otg_pg_control(struct pg_cntl *pg_cntl, bool power_on);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.h

242

void pg_cntl42_mpcc_pg_control(struct pg_cntl *pg_cntl,

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.h

244

void pg_cntl42_opp_pg_control(struct pg_cntl *pg_cntl,

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.h

246

void pg_cntl42_optc_pg_control(struct pg_cntl *pg_cntl,

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.h

248

void pg_cntl42_mem_pg_control(struct pg_cntl *pg_cntl, bool power_on);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.h

249

void pg_cntl42_dio_pg_control(struct pg_cntl *pg_cntl, bool power_on);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.h

250

void dcn42_pg_cntl_destroy(struct pg_cntl **pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.h

251

void pg_cntl42_init_pg_status(struct pg_cntl *pg_cntl);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.h

253

struct pg_cntl *pg_cntl42_create(

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.h

259

void dcn_pg_cntl_destroy(struct pg_cntl **pg_cntl);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1709

if (pool->base.pg_cntl != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1710

dcn_pg_cntl_destroy(&pool->base.pg_cntl);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2183

pool->base.pg_cntl = pg_cntl35_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2184

if (pool->base.pg_cntl == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1689

if (pool->base.pg_cntl != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1690

dcn_pg_cntl_destroy(&pool->base.pg_cntl);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2155

pool->base.pg_cntl = pg_cntl35_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2156

if (pool->base.pg_cntl == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1696

if (pool->base.pg_cntl != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1697

dcn_pg_cntl_destroy(&pool->base.pg_cntl);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2153

pool->base.pg_cntl = pg_cntl35_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2154

if (pool->base.pg_cntl == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1639

if (pool->base.pg_cntl != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1640

dcn_pg_cntl_destroy(&pool->base.pg_cntl);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2228

pool->base.pg_cntl = pg_cntl42_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2229

if (pool->base.pg_cntl == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1606

if (pool->base.pg_cntl != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1607

dcn_pg_cntl_destroy(&pool->base.pg_cntl);

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2180

pool->base.pg_cntl = pg_cntl42_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2181

if (pool->base.pg_cntl == NULL) {