ppll
clk[ppll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "ppll", "ckih", base + MX35_CCM_PPCTL);
[ppll] = PLL(pll_rk3399, PLL_PPLL, "ppll", mux_pll_p, 0, RK3399_PMU_PLL_CON(0),
[ppll] = PLL(pll_rk3328, PLL_PPLL, "ppll", mux_pll_p,
[ppll] = PLL(pll_rk3328, PLL_PPLL, "ppll", mux_pll_p,
[ppll] = PLL(pll_rk3588_ddr, PLL_PPLL, "ppll", mux_pll_p,
[ppll] = PLL(pll_rk3588_core, PLL_PPLL, "ppll", mux_pll_p,
struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
struct amdgpu_pll *ppll = &adev->clock.ppll[0];
ppll->reference_freq =
ppll->reference_div = 0;
ppll->pll_out_min =
ppll->pll_out_max =
ppll->lcd_pll_out_min =
if (ppll->lcd_pll_out_min == 0)
ppll->lcd_pll_out_min = ppll->pll_out_min;
ppll->lcd_pll_out_max =
if (ppll->lcd_pll_out_max == 0)
ppll->lcd_pll_out_max = ppll->pll_out_max;
if (ppll->pll_out_min == 0)
ppll->pll_out_min = 64800;
ppll->pll_in_min =
ppll->pll_in_max =
ppll->min_post_div = 2;
ppll->max_post_div = 0x7f;
ppll->min_frac_feedback_div = 0;
ppll->max_frac_feedback_div = 9;
ppll->min_ref_div = 2;
ppll->max_ref_div = 0x3ff;
ppll->min_feedback_div = 4;
ppll->max_feedback_div = 0xfff;
ppll->best_vco = 0;
adev->clock.ppll[i] = *ppll;
pll = &adev->clock.ppll[0];
pll = &adev->clock.ppll[1];
pll = &adev->clock.ppll[2];