drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

466

static void pp_rv_set_wm_ranges(struct pp_smu *pp,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

515

static void pp_rv_set_pme_wa_enable(struct pp_smu *pp)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

523

static void pp_rv_set_active_display_count(struct pp_smu *pp, int count)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

531

static void pp_rv_set_min_deep_sleep_dcfclk(struct pp_smu *pp, int clock)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

539

static void pp_rv_set_hard_min_dcefclk_by_freq(struct pp_smu *pp, int clock)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

547

static void pp_rv_set_hard_min_fclk_by_freq(struct pp_smu *pp, int mhz)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

555

static enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

566

static enum pp_smu_status pp_nv_set_display_count(struct pp_smu *pp, int count)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

583

pp_nv_set_min_deep_sleep_dcfclk(struct pp_smu *pp, int mhz)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

600

struct pp_smu *pp, int mhz)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

623

pp_nv_set_hard_min_uclk_by_freq(struct pp_smu *pp, int mhz)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

646

struct pp_smu *pp, bool pstate_handshake_supported)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

658

static enum pp_smu_status pp_nv_set_voltage_by_freq(struct pp_smu *pp,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

694

struct pp_smu *pp, struct pp_smu_nv_clock_table *max_clocks)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

710

static enum pp_smu_status pp_nv_get_uclk_dpm_states(struct pp_smu *pp,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

729

struct pp_smu *pp, struct dpm_clocks *clock_table)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

744

static enum pp_smu_status pp_rn_set_wm_ranges(struct pp_smu *pp,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

763

funcs->rv_funcs.pp_smu.dm = ctx;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

777

funcs->nv_funcs.pp_smu.dm = ctx;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

800

funcs->rn_funcs.pp_smu.dm = ctx;

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

147

struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

232

rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

237

rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

241

rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

246

rv1_clk_mgr_construct(ctx, clk_mgr, pp_smu);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

259

dcn201_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

263

dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

267

dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

271

dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

274

dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

285

vg_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

298

dcn31_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

310

dcn315_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

322

dcn316_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

333

dcn32_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

345

dcn314_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

358

dcn351_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

360

dcn35_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

195

struct pp_smu_funcs_rv *pp_smu = NULL;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

202

ASSERT(clk_mgr->pp_smu);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

207

pp_smu = &clk_mgr->pp_smu->rv_funcs;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

220

if (pp_smu->set_display_count)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

221

pp_smu->set_display_count(&pp_smu->pp_smu, display_count);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

261

if (pp_smu->set_hard_min_fclk_by_freq &&

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

262

pp_smu->set_hard_min_dcfclk_by_freq &&

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

263

pp_smu->set_min_deep_sleep_dcfclk) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

264

pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->fclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

265

pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

266

pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_deep_sleep_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

281

if (pp_smu->set_hard_min_fclk_by_freq &&

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

282

pp_smu->set_hard_min_dcfclk_by_freq &&

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

283

pp_smu->set_min_deep_sleep_dcfclk) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

284

pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->fclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

285

pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

286

pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_deep_sleep_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

294

struct pp_smu_funcs_rv *pp_smu = NULL;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

296

if (clk_mgr->pp_smu) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

297

pp_smu = &clk_mgr->pp_smu->rv_funcs;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

299

if (pp_smu->set_pme_wa_enable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

300

pp_smu->set_pme_wa_enable(&pp_smu->pp_smu);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

316

void rv1_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

322

clk_mgr->pp_smu = pp_smu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.h

29

void rv1_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv2_clk_mgr.c

37

void rv2_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv2_clk_mgr.c

40

rv1_clk_mgr_construct(ctx, clk_mgr, pp_smu);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv2_clk_mgr.h

29

void rv2_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

223

struct pp_smu_funcs_nv *pp_smu = NULL;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

247

if (dc->res_pool->pp_smu)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

248

pp_smu = &dc->res_pool->pp_smu->nv_funcs;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

254

if (pp_smu && pp_smu->set_display_count)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

255

pp_smu->set_display_count(&pp_smu->pp_smu, display_count);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

264

if (pp_smu && pp_smu->set_hard_min_dcfclk_by_freq)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

265

pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

271

if (pp_smu && pp_smu->set_min_deep_sleep_dcfclk)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

272

pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

277

if (pp_smu && pp_smu->set_hard_min_socclk_by_freq)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

278

pp_smu->set_hard_min_socclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.socclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

286

if (pp_smu && pp_smu->set_pstate_handshake_support)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

287

pp_smu->set_pstate_handshake_support(&pp_smu->pp_smu, clk_mgr_base->clks.p_state_change_support);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

292

if (pp_smu && pp_smu->set_hard_min_uclk_by_freq)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

293

pp_smu->set_hard_min_uclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

317

if (pp_smu && pp_smu->set_voltage_by_freq)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

318

pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.disp_dpp_voltage_level_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

414

struct pp_smu_funcs_nv *pp_smu = NULL;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

416

if (clk_mgr->pp_smu) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

417

pp_smu = &clk_mgr->pp_smu->nv_funcs;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

419

if (pp_smu->set_pme_wa_enable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

420

pp_smu->set_pme_wa_enable(&pp_smu->pp_smu);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

497

struct pp_smu_funcs_nv *pp_smu = NULL;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

499

if (!clk_mgr->pp_smu || !clk_mgr->pp_smu->nv_funcs.set_voltage_by_freq)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

502

pp_smu = &clk_mgr->pp_smu->nv_funcs;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

513

pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PHYCLK, khz_to_mhz_ceil(clk_mgr_base->clks.phyclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

531

struct pp_smu_funcs *pp_smu,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

540

clk_mgr->pp_smu = pp_smu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h

43

struct pp_smu_funcs *pp_smu,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

181

struct pp_smu_funcs *pp_smu,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.h

31

struct pp_smu_funcs *pp_smu,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

516

struct pp_smu_funcs *pp_smu = clk_mgr->pp_smu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

522

if (pp_smu && pp_smu->rn_funcs.set_wm_ranges)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

523

pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &clk_mgr_base->ranges);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

703

struct pp_smu_funcs *pp_smu,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

717

clk_mgr->pp_smu = pp_smu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

771

if (pp_smu && pp_smu->rn_funcs.get_dpm_clock_table) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

772

status = pp_smu->rn_funcs.get_dpm_clock_table(&pp_smu->rn_funcs.pp_smu, &clock_table);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h

46

struct pp_smu_funcs *pp_smu,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

523

struct pp_smu_funcs *pp_smu,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.h

93

struct pp_smu_funcs *pp_smu,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

680

struct pp_smu_funcs *pp_smu,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

689

clk_mgr->base.pp_smu = pp_smu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.h

47

struct pp_smu_funcs *pp_smu,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

676

struct pp_smu_funcs *pp_smu,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

685

clk_mgr->base.pp_smu = pp_smu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.h

51

struct pp_smu_funcs *pp_smu,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

793

struct pp_smu_funcs *pp_smu,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

802

clk_mgr->base.pp_smu = pp_smu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h

63

struct pp_smu_funcs *pp_smu,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

606

struct pp_smu_funcs *pp_smu,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

615

clk_mgr->base.pp_smu = pp_smu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.h

44

struct pp_smu_funcs *pp_smu,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

581

struct pp_smu_funcs *pp_smu,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

590

clk_mgr->base.pp_smu = pp_smu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.h

44

struct pp_smu_funcs *pp_smu,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1147

struct pp_smu_funcs *pp_smu,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.h

32

struct pp_smu_funcs *pp_smu,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn351_clk_mgr.c

129

struct pp_smu_funcs *pp_smu,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn351_clk_mgr.c

137

dcn35_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1400

struct pp_smu_funcs *pp_smu,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1408

clk_mgr->base.pp_smu = pp_smu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.h

58

struct pp_smu_funcs *pp_smu,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.h

65

struct pp_smu_funcs *pp_smu,

drivers/gpu/drm/amd/display/dc/core/dc.c

1162

dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg);

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

104

void (*set_display_count)(struct pp_smu *pp, int count);

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

113

void (*set_wm_ranges)(struct pp_smu *pp,

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

119

void (*set_hard_min_dcfclk_by_freq)(struct pp_smu *pp, int mhz);

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

125

void (*set_min_deep_sleep_dcfclk)(struct pp_smu *pp, int mhz);

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

130

void (*set_hard_min_fclk_by_freq)(struct pp_smu *pp, int mhz);

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

135

void (*set_hard_min_socclk_by_freq)(struct pp_smu *pp, int mhz);

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

138

void (*set_pme_wa_enable)(struct pp_smu *pp);

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

169

struct pp_smu pp_smu;

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

174

enum pp_smu_status (*set_display_count)(struct pp_smu *pp, int count);

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

179

enum pp_smu_status (*set_hard_min_dcfclk_by_freq)(struct pp_smu *pp, int Mhz);

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

185

enum pp_smu_status (*set_min_deep_sleep_dcfclk)(struct pp_smu *pp, int Mhz);

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

190

enum pp_smu_status (*set_hard_min_uclk_by_freq)(struct pp_smu *pp, int Mhz);

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

195

enum pp_smu_status (*set_hard_min_socclk_by_freq)(struct pp_smu *pp, int Mhz);

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

198

enum pp_smu_status (*set_pme_wa_enable)(struct pp_smu *pp);

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

203

enum pp_smu_status (*set_voltage_by_freq)(struct pp_smu *pp,

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

218

enum pp_smu_status (*set_wm_ranges)(struct pp_smu *pp,

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

224

enum pp_smu_status (*get_maximum_sustainable_clocks)(struct pp_smu *pp,

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

229

enum pp_smu_status (*get_uclk_dpm_states)(struct pp_smu *pp,

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

241

enum pp_smu_status (*set_pstate_handshake_support)(struct pp_smu *pp,

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

272

struct pp_smu pp_smu;

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

282

enum pp_smu_status (*set_wm_ranges)(struct pp_smu *pp,

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

285

enum pp_smu_status (*get_dpm_clock_table) (struct pp_smu *pp,

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

290

struct pp_smu pp_smu;

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

301

enum pp_smu_status (*set_wm_ranges)(struct pp_smu *pp,

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

305

enum pp_smu_status (*get_dpm_clock_table) (struct pp_smu *pp,

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

308

enum pp_smu_status (*notify_smu_timeout) (struct pp_smu *pp);

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

312

struct pp_smu ctx;

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

98

struct pp_smu pp_smu;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1377

if (dc->res_pool->pp_smu)

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1378

pp = &dc->res_pool->pp_smu->rv_funcs;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1426

pp->set_wm_ranges(&pp->pp_smu, &ranges);

drivers/gpu/drm/amd/display/dc/inc/core_types.h

256

struct pp_smu_funcs *pp_smu;

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

363

struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

347

struct pp_smu_funcs *pp_smu;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1010

kfree(pool->base.pp_smu);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1527

pool->base.pp_smu = dcn10_pp_smu_create(ctx);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1533

if (pool->base.pp_smu != NULL

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1534

&& pool->base.pp_smu->rv_funcs.set_pme_wa_enable != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

920

struct pp_smu_funcs *pp_smu = kzalloc_obj(*pp_smu);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

922

if (!pp_smu)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

923

return pp_smu;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

925

dm_pp_get_funcs(ctx, pp_smu);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

926

return pp_smu;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1080

static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1221

if (pool->base.pp_smu != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1222

dcn20_pp_smu_destroy(&pool->base.pp_smu);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2322

struct pp_smu_funcs *pp_smu = kzalloc_obj(*pp_smu);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2324

if (!pp_smu)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2325

return pp_smu;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2327

dm_pp_get_funcs(ctx, pp_smu);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2329

if (pp_smu->ctx.ver != PP_SMU_VER_NV)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2330

pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2332

return pp_smu;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2335

static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2337

if (pp_smu && *pp_smu) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2338

kfree(*pp_smu);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2339

*pp_smu = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2380

if (pool->base.pp_smu) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2388

if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2389

status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2390

(&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2395

if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2396

status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2397

(&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2590

pool->base.pp_smu = dcn20_pp_smu_create(ctx);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2640

if (pool->base.pp_smu && pool->base.pp_smu->nv_funcs.set_wm_ranges)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2641

pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1132

struct pp_smu_funcs *pp_smu = kzalloc_obj(*pp_smu);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1134

if (!pp_smu)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1135

return pp_smu;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1137

dm_pp_get_funcs(ctx, pp_smu);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1139

if (pp_smu->ctx.ver != PP_SMU_VER_RN)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1140

pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1143

return pp_smu;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1146

static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1148

if (pp_smu && *pp_smu) {

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1149

kfree(*pp_smu);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1150

*pp_smu = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1579

pool->base.pp_smu = dcn21_pp_smu_create(ctx);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

501

static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

791

if (pool->base.pp_smu != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

792

dcn21_pp_smu_destroy(&pool->base.pp_smu);

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1356

struct pp_smu_funcs *pp_smu,

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1396

pp_smu->nv_funcs.set_wm_ranges(&pp_smu->nv_funcs.pp_smu, &ranges);

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1591

if (!dc->debug.disable_pplib_wm_range && pool->base.pp_smu->nv_funcs.set_wm_ranges)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1592

set_wm_ranges(pool->base.pp_smu, &dcn3_01_soc);