pm8001_cw32
pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1);
pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2);
pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3);
pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
pm8001_cw32(pm8001_ha, 0, MSIX_TABLE_BASE,
pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, 1);
pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
pm8001_cw32(pm8001_ha, 0, MSIX_TABLE_BASE,
pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL);
pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar,
pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset,
pm8001_cw32(pm8001_ha,
pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar,
pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue);
pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016);
pm8001_cw32(pm8001_ha, 2, offset, value);
pm8001_cw32(pm8001_ha, 2, offset, value);
pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE);
pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1);
pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0);
pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET);
pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET,
pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST);
pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0);
pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0);
pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0);
pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal);
pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0);
pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal);
pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature);
pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0);
pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0);
pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0);
pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal);
pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET);
pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE);
pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11);
pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, 1U << vec);
pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR_U, 1U << (vec - 32));
pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL);
pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 0xFFFFFFFF);
pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U, 0xFFFFFFFF);
pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 1U << vec);
pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U, 1U << (vec - 32));
pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
pm8001_cw32(pm8001_ha, 0,
pm8001_cw32(pm8001_ha, 0,
pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET,
pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value);
pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE);