pch_gbe_phy_write_reg_miic
pch_gbe_phy_write_reg_miic(hw, MII_BMCR, BMCR_RESET);
pch_gbe_phy_write_reg_miic(hw, PHY_CONTROL, phy_ctrl);
pch_gbe_phy_write_reg_miic(hw, PHY_CONTROL, PHY_CONTROL_DEFAULT);
pch_gbe_phy_write_reg_miic(hw, PHY_AUTONEG_ADV,
pch_gbe_phy_write_reg_miic(hw, PHY_NEXT_PAGE_TX,
pch_gbe_phy_write_reg_miic(hw, PHY_1000T_CTRL, PHY_1000T_CTRL_DEFAULT);
pch_gbe_phy_write_reg_miic(hw, PHY_PHYSP_CONTROL,
pch_gbe_phy_write_reg_miic(hw, PHY_CONTROL, mii_reg);
pch_gbe_phy_write_reg_miic(hw, PHY_CONTROL, mii_reg);
ret = pch_gbe_phy_write_reg_miic(hw, PHY_AR8031_DBG_OFF,
ret = pch_gbe_phy_write_reg_miic(hw, PHY_AR8031_DBG_DAT,
pch_gbe_phy_write_reg_miic(hw, MII_BMCR, BMCR_RESET);
pch_gbe_phy_write_reg_miic(hw, PHY_PHYSP_CONTROL, mii_reg);
ret = pch_gbe_phy_write_reg_miic(hw, PHY_AR8031_DBG_OFF,
ret = pch_gbe_phy_write_reg_miic(hw, PHY_AR8031_DBG_DAT,
s32 pch_gbe_phy_write_reg_miic(struct pch_gbe_hw *hw, u32 offset, u16 data);