drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

552

&otg_master->pll_settings);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1018

bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1046

pll_settings->use_external_clk;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1048

!pll_settings->use_external_clk;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1071

struct pll_settings *pll_settings)

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1109

if (pll_settings->actual_pix_clk_100hz > 6000000UL)

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1120

bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1148

pll_settings->use_external_clk;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1150

!pll_settings->use_external_clk;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1285

struct pll_settings *pll_settings)

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1290

dce112_program_pix_clk(clock_source, pix_clk_params, encoding, pll_settings);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1331

struct pll_settings *pll_settings)

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1347

REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1360

dce112_program_pix_clk(clock_source, pix_clk_params, encoding, pll_settings);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1368

struct pll_settings *pll_settings)

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1375

if (pix_clk_params == NULL || pll_settings == NULL

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1382

memset(pll_settings, 0, sizeof(*pll_settings));

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1399

pll_settings->actual_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1400

pll_settings->adjusted_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1401

pll_settings->calculated_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

197

struct pll_settings *pll_settings,

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

210

pll_settings->adjusted_pix_clk_100hz,

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

229

pll_settings->adjusted_pix_clk_100hz)

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

231

pll_settings->adjusted_pix_clk_100hz

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

232

: pll_settings->adjusted_pix_clk_100hz -

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

237

pll_settings->reference_freq = calc_pll_cs->ref_freq_khz;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

238

pll_settings->reference_divider = ref_divider;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

239

pll_settings->feedback_divider = feedback_divider;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

240

pll_settings->fract_feedback_divider = fract_feedback_divider;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

241

pll_settings->pix_clk_post_divider = post_divider;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

242

pll_settings->calculated_pix_clk_100hz =

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

244

pll_settings->vco_freq =

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

253

struct pll_settings *pll_settings,

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

266

tolerance = (pll_settings->adjusted_pix_clk_100hz * err_tolerance) /

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

281

pll_settings,

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

295

struct pll_settings *pll_settings)

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

303

if (pll_settings->adjusted_pix_clk_100hz == 0) {

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

310

if (pll_settings->pix_clk_post_divider) {

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

311

min_post_divider = pll_settings->pix_clk_post_divider;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

312

max_post_divider = pll_settings->pix_clk_post_divider;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

315

if (min_post_divider * pll_settings->adjusted_pix_clk_100hz <

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

318

pll_settings->adjusted_pix_clk_100hz;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

320

pll_settings->adjusted_pix_clk_100hz) <

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

326

if (max_post_divider * pll_settings->adjusted_pix_clk_100hz

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

329

pll_settings->adjusted_pix_clk_100hz;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

338

if (pll_settings->reference_divider) {

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

339

min_ref_divider = pll_settings->reference_divider;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

340

max_ref_divider = pll_settings->reference_divider;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

383

pll_settings,

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

399

struct pll_settings *pll_settings)

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

450

pll_settings->actual_pix_clk_100hz = actual_pix_clk_100hz;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

451

pll_settings->adjusted_pix_clk_100hz =

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

453

pll_settings->reference_divider =

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

455

pll_settings->pix_clk_post_divider =

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

477

struct pll_settings *pll_settings,

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

488

pll_settings->use_external_clk = (field > 1);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

499

pll_settings->adjusted_pix_clk_100hz / 10);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

502

pll_settings->ss_percentage = ss_data->percentage;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

506

if (!pll_adjust_pix_clk(clk_src, pix_clk_params, pll_settings)) {

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

511

pll_settings->actual_pix_clk_100hz =

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

513

pll_settings->adjusted_pix_clk_100hz =

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

517

pll_settings->adjusted_pix_clk_100hz = 1000000;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

526

pll_settings);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

532

pll_settings);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

539

struct pll_settings *pll_settings,

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

563

pll_settings->actual_pix_clk_100hz = actual_pixel_clock_100hz;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

564

pll_settings->adjusted_pix_clk_100hz = actual_pixel_clock_100hz;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

565

pll_settings->calculated_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

571

struct pll_settings *pll_settings)

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

577

if (pix_clk_params == NULL || pll_settings == NULL

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

584

memset(pll_settings, 0, sizeof(*pll_settings));

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

588

pll_settings->adjusted_pix_clk_100hz = clk_src->ext_clk_khz * 10;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

589

pll_settings->calculated_pix_clk_100hz = clk_src->ext_clk_khz * 10;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

590

pll_settings->actual_pix_clk_100hz =

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

596

pll_settings, pix_clk_params);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

604

struct pll_settings *pll_settings)

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

609

if (pix_clk_params == NULL || pll_settings == NULL

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

616

memset(pll_settings, 0, sizeof(*pll_settings));

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

620

pll_settings->adjusted_pix_clk_100hz = clk_src->ext_clk_khz * 10;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

621

pll_settings->calculated_pix_clk_100hz = clk_src->ext_clk_khz * 10;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

622

pll_settings->actual_pix_clk_100hz =

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

628

pll_settings, pix_clk_params);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

650

const struct pll_settings *pll_settings,

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

667

if (pll_settings == NULL)

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

675

pll_settings->fract_feedback_divider, 1000000);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

676

fb_div = dc_fixpt_add_int(fb_div, pll_settings->feedback_divider);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

698

pll_settings->reference_freq * (uint64_t)1000,

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

699

pll_settings->reference_divider * (uint64_t)ss_data->modulation_freq_hz);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

716

enum signal_type signal, struct pll_settings *pll_settings)

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

725

pll_settings->calculated_pix_clk_100hz / 10);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

730

if (ss_data != NULL && pll_settings->ss_percentage != 0) {

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

731

if (calculate_ss(pll_settings, ss_data, &d_s_data)) {

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

848

struct pll_settings *pll_settings)

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

865

bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

869

bp_pc_params.reference_divider = pll_settings->reference_divider;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

870

bp_pc_params.feedback_divider = pll_settings->feedback_divider;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

872

pll_settings->fract_feedback_divider;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

874

pll_settings->pix_clk_post_divider;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

876

pll_settings->use_external_clk;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

906

pll_settings))

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

922

struct pll_settings *pll_settings)

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

939

bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

945

pll_settings->use_external_clk;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

947

!pll_settings->use_external_clk;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

969

struct pll_settings *pll_settings)

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

993

REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1457

pipe_ctx->pll_settings.ss_percentage;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1532

&pipe_ctx->pll_settings)) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3315

&pipes[i].pll_settings);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1206

&pipe_ctx->pll_settings)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

875

&pipe_ctx->pll_settings)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

496

&pipe_ctx->pll_settings);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1394

&pipe_ctx->pll_settings);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1744

&pipe_ctx->pll_settings);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1042

&pipe_ctx->pll_settings);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

824

&pipe_ctx->pll_settings)) {

drivers/gpu/drm/amd/display/dc/inc/clock_source.h

168

struct pll_settings *);

drivers/gpu/drm/amd/display/dc/inc/clock_source.h

172

struct pll_settings *);

drivers/gpu/drm/amd/display/dc/inc/core_types.h

462

struct pll_settings pll_settings;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

112

&pipes[i]->pll_settings);

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

929

&pipe_ctx->pll_settings);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1071

&pipe_ctx->pll_settings);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1323

&pipe_ctx->pll_settings);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1773

&pipe_ctx->pll_settings);