drivers/accel/habanalabs/common/firmware_if.c

1239

pkt.pll_type = __cpu_to_le16((u16)used_pll_idx);

drivers/clk/clk-vt8500.c

684

static __init void vtwm_pll_clk_init(struct device_node *node, int pll_type)

drivers/clk/clk-vt8500.c

707

pll_clk->type = pll_type;

drivers/clk/clk-xgene.c

170

static void xgene_pllclk_init(struct device_node *np, enum xgene_pll_type pll_type)

drivers/clk/clk-xgene.c

185

0, reg, 0, pll_type, &clk_lock,

drivers/clk/qcom/apss-ipq-pll.c

132

int pll_type;

drivers/clk/qcom/apss-ipq-pll.c

138

.pll_type = CLK_ALPHA_PLL_TYPE_STROMER,

drivers/clk/qcom/apss-ipq-pll.c

144

.pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS,

drivers/clk/qcom/apss-ipq-pll.c

150

.pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA,

drivers/clk/qcom/apss-ipq-pll.c

156

.pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA,

drivers/clk/qcom/apss-ipq-pll.c

162

.pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA,

drivers/clk/qcom/apss-ipq-pll.c

194

if (data->pll_type == CLK_ALPHA_PLL_TYPE_HUAYRA)

drivers/clk/qcom/apss-ipq-pll.c

196

else if (data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER ||

drivers/clk/qcom/apss-ipq-pll.c

197

data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER_PLUS)

drivers/clk/rockchip/clk-pll.c

1056

enum rockchip_pll_type pll_type,

drivers/clk/rockchip/clk-pll.c

1070

if ((pll_type != pll_rk3328 && num_parents != 2) ||

drivers/clk/rockchip/clk-pll.c

1071

(pll_type == pll_rk3328 && num_parents != 1)) {

drivers/clk/rockchip/clk-pll.c

1088

if (pll_type == pll_rk3328)

drivers/clk/rockchip/clk-pll.c

1096

if (pll_type == pll_rk3036 ||

drivers/clk/rockchip/clk-pll.c

1097

pll_type == pll_rk3066 ||

drivers/clk/rockchip/clk-pll.c

1098

pll_type == pll_rk3328 ||

drivers/clk/rockchip/clk-pll.c

1099

pll_type == pll_rk3399 ||

drivers/clk/rockchip/clk-pll.c

1100

pll_type == pll_rk3588)

drivers/clk/rockchip/clk-pll.c

1112

if (pll_type == pll_rk3328)

drivers/clk/rockchip/clk-pll.c

1147

switch (pll_type) {

drivers/clk/rockchip/clk-pll.c

1182

pll->type = pll_type;

drivers/clk/rockchip/clk.h

653

enum rockchip_pll_type pll_type,

drivers/clk/x86/clk-cgu.h

113

enum pll_type type;

drivers/clk/x86/clk-cgu.h

94

enum pll_type type;

drivers/gpu/drm/i915/display/intel_lt_phy.c

1448

static void set_phy_vdr_addresses(struct lt_phy_params *p, int pll_type)

drivers/gpu/drm/i915/display/intel_lt_phy.c

1450

p->pll_reg4.addr = PLL_REG_ADDR(PLL_REG4_ADDR, pll_type);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1451

p->pll_reg3.addr = PLL_REG_ADDR(PLL_REG3_ADDR, pll_type);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1452

p->pll_reg5.addr = PLL_REG_ADDR(PLL_REG5_ADDR, pll_type);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1453

p->pll_reg57.addr = PLL_REG_ADDR(PLL_REG57_ADDR, pll_type);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1454

p->lf.addr = PLL_REG_ADDR(PLL_LF_ADDR, pll_type);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1455

p->tdc.addr = PLL_REG_ADDR(PLL_TDC_ADDR, pll_type);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1456

p->ssc.addr = PLL_REG_ADDR(PLL_SSC_ADDR, pll_type);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1457

p->bias2.addr = PLL_REG_ADDR(PLL_BIAS2_ADDR, pll_type);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1458

p->bias_trim.addr = PLL_REG_ADDR(PLL_BIAS_TRIM_ADDR, pll_type);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1459

p->dco_med.addr = PLL_REG_ADDR(PLL_DCO_MED_ADDR, pll_type);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1460

p->dco_fine.addr = PLL_REG_ADDR(PLL_DCO_FINE_ADDR, pll_type);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1461

p->ssc_inj.addr = PLL_REG_ADDR(PLL_SSC_INJ_ADDR, pll_type);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1462

p->surv_bonus.addr = PLL_REG_ADDR(PLL_SURV_BONUS_ADDR, pll_type);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1572

u32 pll_type = 0;

drivers/gpu/drm/i915/display/intel_lt_phy.c

1646

pll_type = ((frequency_khz == 10000) || (frequency_khz == 20000) ||

drivers/gpu/drm/i915/display/intel_lt_phy.c

1648

set_phy_vdr_addresses(&p, pll_type);

drivers/gpu/drm/i915/display/intel_lt_phy_regs.h

89

#define PLL_REG_ADDR(base, pll_type) ((pll_type) ? (base) + PLL_TYPE_OFFSET : (base))

drivers/gpu/drm/i915/display/intel_tc.c

1634

enum icl_port_dpll_id pll_type = ICL_PORT_DPLL_DEFAULT;

drivers/gpu/drm/i915/display/intel_tc.c

1641

pll_type = intel_ddi_port_pll_type(&dig_port->base, crtc_state);

drivers/gpu/drm/i915/display/intel_tc.c

1645

if (active_streams && !tc_phy_is_connected(tc, pll_type))

drivers/media/dvb-frontends/drxd.h

18

u8 pll_type;

drivers/media/pci/ngene/ngene-cards.c

1123

.pll_type = DVB_PLL_THOMSON_DTT7520X,

drivers/media/pci/ngene/ngene-cards.c

1134

.pll_type = DVB_PLL_THOMSON_DTT7520X,

drivers/media/pci/ngene/ngene-cards.c

753

feconf->pll_type)) {

drivers/media/pci/ngene/ngene-cards.c

754

dev_err(pdev, "No pll(%d) found!\n", feconf->pll_type);

drivers/media/usb/em28xx/em28xx-dvb.c

393

.pll_type = DRXD_PLL_NONE,

drivers/ssb/driver_extif.c

108

u32 *pll_type, u32 *n, u32 *m)

drivers/ssb/driver_extif.c

110

*pll_type = SSB_PLLTYPE_1;

drivers/ssb/driver_mipscore.c

268

u32 pll_type, n, m, rate = 0;

drivers/ssb/driver_mipscore.c

274

ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);

drivers/ssb/driver_mipscore.c

276

ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m);

drivers/ssb/driver_mipscore.c

280

if ((pll_type == SSB_PLLTYPE_5) || (bus->chip_id == 0x5365)) {

drivers/ssb/driver_mipscore.c

283

rate = ssb_calc_clock_rate(pll_type, n, m);

drivers/ssb/driver_mipscore.c

286

if (pll_type == SSB_PLLTYPE_6) {

include/linux/habanalabs/cpucp_if.h

843

__le16 pll_type;