drivers/clk/clk-stm32f4.c

728

int pll_state;

drivers/clk/clk-stm32f4.c

730

pll_state = stm32f4_pll_is_enabled(hw);

drivers/clk/clk-stm32f4.c

732

if (pll_state)

drivers/clk/clk-stm32f4.c

745

if (pll_state)

drivers/clk/clk-stm32f4.c

782

int pll_state, ret;

drivers/clk/clk-stm32f4.c

787

pll_state = stm32f4_pll_is_enabled(pll_div->hw_pll);

drivers/clk/clk-stm32f4.c

789

if (pll_state)

drivers/clk/clk-stm32f4.c

794

if (pll_state)

drivers/clk/clk-stm32f4.c

857

int pll_state;

drivers/clk/clk-stm32f4.c

871

pll_state = stm32f4_pll_is_enabled(hw);

drivers/clk/clk-stm32f4.c

873

if (pll_state)

drivers/clk/clk-stm32f4.c

885

if (pll_state)

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2049

struct intel_cx0pll_state *pll_state, bool is_dp)

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2056

pll_state->ssc_enabled =

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2065

static bool intel_c10pll_ssc_enabled(const struct intel_c10pll_state *pll_state)

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2067

return memchr_inv(&pll_state->pll[C10_PLL_SSC_REG_START_IDX],

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2068

0, sizeof(pll_state->pll[0]) * C10_PLL_SSC_REG_COUNT);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2072

struct intel_cx0pll_state *pll_state)

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2077

if (pll_state->ssc_enabled)

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2080

drm_WARN_ON(display->drm, ARRAY_SIZE(pll_state->c10.pll) <

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2085

pll_state->c10.pll[i] = 0;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2088

static bool c10pll_state_is_dp(const struct intel_c10pll_state *pll_state)

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2090

return !REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state->pll[15]);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2093

static bool c20pll_state_is_dp(const struct intel_c20pll_state *pll_state)

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2095

return pll_state->vdr.serdes_rate & PHY_C20_IS_DP;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2098

static bool cx0pll_state_is_dp(const struct intel_cx0pll_state *pll_state)

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2100

if (pll_state->use_c10)

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2101

return c10pll_state_is_dp(&pll_state->c10);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2103

return c20pll_state_is_dp(&pll_state->c20);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2113

struct intel_cx0pll_state *pll_state)

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2120

pll_state->c10 = *tables[i];

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2121

intel_cx0pll_update_ssc(encoder, pll_state, is_dp);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2122

intel_c10pll_update_pll(encoder, pll_state);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2124

pll_state->use_c10 = true;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2125

pll_state->lane_count = lane_count;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2127

drm_WARN_ON(display->drm, is_dp != c10pll_state_is_dp(&pll_state->c10));

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2170

const struct intel_c10pll_state *pll_state)

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2176

if (pll_state->pll[0] & C10_PLL0_FRACEN) {

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2177

frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11];

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2178

frac_rem = pll_state->pll[14] << 8 | pll_state->pll[13];

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2179

frac_den = pll_state->pll[10] << 8 | pll_state->pll[9];

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2182

multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, pll_state->pll[3]) << 8 |

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2183

pll_state->pll[2]) / 2 + 16;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2185

tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, pll_state->pll[15]);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2186

hdmi_div = REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state->pll[15]);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2251

struct intel_c10pll_state *pll_state = &cx0pll_state->c10;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2270

for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2271

pll_state->pll[i] = intel_cx0_read(encoder, lane, PHY_C10_VDR_PLL(i));

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2273

pll_state->cmn = intel_cx0_read(encoder, lane, PHY_C10_VDR_CMN(0));

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2274

pll_state->tx = intel_cx0_read(encoder, lane, PHY_C10_VDR_TX(0));

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2278

pll_state->clock = intel_c10pll_calc_port_clock(encoder, pll_state);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2282

if (cx0pll_state->ssc_enabled != intel_c10pll_ssc_enabled(pll_state))

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2287

str_enabled_disabled(intel_c10pll_ssc_enabled(pll_state)));

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2292

const struct intel_c10pll_state *pll_state)

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2299

for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2301

pll_state->pll[i],

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2304

intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_CMN(0), pll_state->cmn, MB_WRITE_COMMITTED);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2305

intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_TX(0), pll_state->tx, MB_WRITE_COMMITTED);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2392

struct intel_c20pll_state *pll_state)

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2430

pll_state->clock = crtc_state->port_clock;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2431

pll_state->tx[0] = 0xbe88;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2432

pll_state->tx[1] = intel_c20_hdmi_tmds_tx_cgf_1(crtc_state);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2433

pll_state->tx[2] = 0x0000;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2434

pll_state->cmn[0] = 0x0500;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2435

pll_state->cmn[1] = 0x0005;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2436

pll_state->cmn[2] = 0x0000;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2437

pll_state->cmn[3] = 0x0000;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2438

pll_state->mpllb[0] = (MPLL_TX_CLK_DIV(mpll_tx_clk_div) |

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2440

pll_state->mpllb[1] = (CAL_DAC_CODE(CAL_DAC_CODE_31) |

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2443

pll_state->mpllb[2] = (MPLLB_ANA_FREQ_VCO(mpllb_ana_freq_vco) |

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2446

pll_state->mpllb[3] = (V2I(V2I_2) |

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2449

pll_state->mpllb[4] = 0x0000;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2450

pll_state->mpllb[5] = 0x0000;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2451

pll_state->mpllb[6] = (C20_MPLLB_FRACEN | SSC_UP_SPREAD);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2452

pll_state->mpllb[7] = MPLL_FRACN_DEN;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2453

pll_state->mpllb[8] = mpll_fracn_quot;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2454

pll_state->mpllb[9] = mpll_fracn_rem;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2455

pll_state->mpllb[10] = HDMI_DIV(HDMI_DIV_1);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2648

struct intel_cx0pll_state *pll_state)

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2656

pll_state->c20 = *table;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2658

intel_cx0pll_update_ssc(encoder, pll_state, intel_crtc_has_dp_encoder(crtc_state));

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2714

const struct intel_c20pll_state *pll_state)

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2723

unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE, pll_state->tx[0]);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2725

if (intel_c20phy_use_mpllb(pll_state)) {

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2727

frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN, pll_state->mpllb[6]);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2728

frac_quot = pll_state->mpllb[8];

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2729

frac_rem = pll_state->mpllb[9];

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2730

frac_den = pll_state->mpllb[7];

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2731

multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mpllb[0]);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2732

tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK, pll_state->mpllb[0]);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2733

ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mpllb[6]);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2737

frac_en = REG_FIELD_GET(C20_MPLLA_FRACEN, pll_state->mplla[6]);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2738

frac_quot = pll_state->mplla[8];

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2739

frac_rem = pll_state->mplla[9];

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2740

frac_den = pll_state->mplla[7];

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2741

multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mplla[0]);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2742

tx_clk_div = REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK, pll_state->mplla[1]);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2743

ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mplla[6]);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2744

fb_clk_div4_en = REG_FIELD_GET(C20_FB_CLK_DIV4_EN, pll_state->mplla[0]);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2761

struct intel_c20pll_state *pll_state = &cx0pll_state->c20;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2774

intel_c20_readout_vdr_params(encoder, &pll_state->vdr, &cntx);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2777

for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) {

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2779

pll_state->tx[i] = intel_c20_sram_read(encoder,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2783

pll_state->tx[i] = intel_c20_sram_read(encoder,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2789

for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) {

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2791

pll_state->cmn[i] = intel_c20_sram_read(encoder,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2795

pll_state->cmn[i] = intel_c20_sram_read(encoder,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2800

if (intel_c20phy_use_mpllb(pll_state)) {

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2802

for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) {

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2804

pll_state->mpllb[i] = intel_c20_sram_read(encoder,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2808

pll_state->mpllb[i] = intel_c20_sram_read(encoder,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2814

for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) {

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2816

pll_state->mplla[i] = intel_c20_sram_read(encoder,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2820

pll_state->mplla[i] = intel_c20_sram_read(encoder,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2826

pll_state->clock = intel_c20pll_calc_port_clock(encoder, pll_state);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2830

cx0pll_state->ssc_enabled = readout_ssc_state(encoder, intel_c20phy_use_mpllb(pll_state));

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2888

const struct intel_c20pll_state *pll_state)

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2911

for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) {

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2915

pll_state->tx[i]);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2919

pll_state->tx[i]);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2923

for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) {

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2927

pll_state->cmn[i]);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2931

pll_state->cmn[i]);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2935

if (intel_c20phy_use_mpllb(pll_state)) {

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2936

for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) {

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2940

pll_state->mpllb[i]);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2944

pll_state->mpllb[i]);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2947

for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) {

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2951

pll_state->mplla[i]);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2955

pll_state->mplla[i]);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2963

intel_c20_program_vdr_params(encoder, &pll_state->vdr, owned_lane_mask);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2975

const struct intel_cx0pll_state *pll_state,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2980

bool is_dp = cx0pll_state_is_dp(pll_state);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3000

val |= pll_state->ssc_enabled ? XELPDP_SSC_ENABLE_PLLA : 0;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3002

val |= pll_state->ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3224

const struct intel_cx0pll_state *pll_state)

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3226

int port_clock = pll_state->use_c10 ? pll_state->c10.clock : pll_state->c20.clock;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3246

intel_program_port_clock_ctl(encoder, pll_state, port_clock, lane_reversal);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3266

intel_c10_pll_program(display, encoder, &pll_state->c10);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3268

intel_c20_pll_program(display, encoder, &pll_state->c20);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3274

intel_cx0_program_phy_lane(encoder, pll_state->lane_count, lane_reversal);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3316

if (!cx0pll_state_is_dp(pll_state) && pll_state->use_c10) {

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3662

struct intel_cx0pll_state *pll_state)

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3664

memset(pll_state, 0, sizeof(*pll_state));

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3670

intel_c10pll_readout_hw_state(encoder, pll_state);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3672

intel_c20pll_readout_hw_state(encoder, pll_state);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3730

const struct intel_cx0pll_state *pll_state)

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3733

return intel_c10pll_calc_port_clock(encoder, &pll_state->c10);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3735

return intel_c20pll_calc_port_clock(encoder, &pll_state->c20);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3759

struct intel_cx0pll_state pll_state = {};

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3775

&pll_state) < 0) {

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3785

intel_cx0pll_enable(encoder, &pll_state);

drivers/gpu/drm/i915/display/intel_cx0_phy.h

50

struct intel_cx0pll_state *pll_state);

drivers/gpu/drm/i915/display/intel_cx0_phy.h

52

const struct intel_cx0pll_state *pll_state);

drivers/gpu/drm/i915/display/intel_lt_phy.c

2231

struct intel_lt_phy_pll_state *pll_state)

drivers/gpu/drm/i915/display/intel_lt_phy.c

2238

pll_state->tbt_mode = intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder));

drivers/gpu/drm/i915/display/intel_lt_phy.c

2239

if (pll_state->tbt_mode)

drivers/gpu/drm/i915/display/intel_lt_phy.c

2246

pll_state->config[0] = intel_lt_phy_read(encoder, lane, LT_PHY_VDR_0_CONFIG);

drivers/gpu/drm/i915/display/intel_lt_phy.c

2247

pll_state->config[1] = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_1_CONFIG);

drivers/gpu/drm/i915/display/intel_lt_phy.c

2248

pll_state->config[2] = intel_lt_phy_read(encoder, lane, LT_PHY_VDR_2_CONFIG);

drivers/gpu/drm/i915/display/intel_lt_phy.c

2252

pll_state->data[i][k] =

drivers/gpu/drm/i915/display/intel_lt_phy.c

2257

pll_state->clock =

drivers/gpu/drm/i915/display/intel_lt_phy.h

35

struct intel_lt_phy_pll_state *pll_state);

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

219

void intel_snps_hdmi_pll_compute_mpllb(struct intel_mpllb_state *pll_state, u64 pixel_clock)

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

262

pll_state->clock = pixel_clock;

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

263

pll_state->ref_control =

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

265

pll_state->mpllb_cp =

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

270

pll_state->mpllb_div =

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

276

pll_state->mpllb_div2 =

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

280

pll_state->mpllb_fracn1 =

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

284

pll_state->mpllb_fracn2 =

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

287

pll_state->mpllb_sscen =

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

291

void intel_snps_hdmi_pll_compute_c10pll(struct intel_c10pll_state *pll_state, u64 pixel_clock)

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

335

pll_state->clock = pixel_clock;

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

337

pll_state->tx = 0x10;

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

338

pll_state->cmn = 0x1;

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

339

pll_state->pll[0] = REG_FIELD_PREP(C10_PLL0_DIV5CLK_EN, pll_params.mpll_div5_en) |

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

343

pll_state->pll[2] = REG_FIELD_PREP(C10_PLL2_MULTIPLIERL_MASK, pll_params.multiplier);

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

344

pll_state->pll[3] = REG_FIELD_PREP(C10_PLL3_MULTIPLIERH_MASK, pll_params.multiplier >> 8);

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

345

pll_state->pll[8] = REG_FIELD_PREP(C10_PLL8_SSC_UP_SPREAD, pll_params.ssc_up_spread);

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

346

pll_state->pll[9] = REG_FIELD_PREP(C10_PLL9_FRACN_DENL_MASK, pll_params.fracn_den);

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

347

pll_state->pll[10] = REG_FIELD_PREP(C10_PLL10_FRACN_DENH_MASK, pll_params.fracn_den >> 8);

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

348

pll_state->pll[11] = REG_FIELD_PREP(C10_PLL11_FRACN_QUOT_L_MASK, pll_params.fracn_quot);

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

349

pll_state->pll[12] = REG_FIELD_PREP(C10_PLL12_FRACN_QUOT_H_MASK,

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

352

pll_state->pll[13] = REG_FIELD_PREP(C10_PLL13_FRACN_REM_L_MASK, pll_params.fracn_rem);

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

353

pll_state->pll[14] = REG_FIELD_PREP(C10_PLL14_FRACN_REM_H_MASK, pll_params.fracn_rem >> 8);

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

354

pll_state->pll[15] = REG_FIELD_PREP(C10_PLL15_TXCLKDIV_MASK, pll_params.tx_clk_div) |

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

356

pll_state->pll[16] = REG_FIELD_PREP(C10_PLL16_ANA_CPINT, pll_params.ana_cp_int) |

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

358

pll_state->pll[17] = REG_FIELD_PREP(C10_PLL17_ANA_CPINTGS_H_MASK, ana_cp_int_gs >> 1) |

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

360

pll_state->pll[18] =

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

364

pll_state->pll[19] = REG_FIELD_PREP(C10_PLL19_ANA_CPPROPGS_H_MASK, ana_cp_prop_gs >> 3) |

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.h

14

void intel_snps_hdmi_pll_compute_mpllb(struct intel_mpllb_state *pll_state, u64 pixel_clock);

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.h

15

void intel_snps_hdmi_pll_compute_c10pll(struct intel_c10pll_state *pll_state, u64 pixel_clock);

drivers/gpu/drm/i915/display/intel_snps_phy.c

1823

const struct intel_mpllb_state *pll_state = &crtc_state->dpll_hw_state.mpllb;

drivers/gpu/drm/i915/display/intel_snps_phy.c

1832

intel_de_write(display, SNPS_PHY_MPLLB_CP(phy), pll_state->mpllb_cp);

drivers/gpu/drm/i915/display/intel_snps_phy.c

1833

intel_de_write(display, SNPS_PHY_MPLLB_DIV(phy), pll_state->mpllb_div);

drivers/gpu/drm/i915/display/intel_snps_phy.c

1834

intel_de_write(display, SNPS_PHY_MPLLB_DIV2(phy), pll_state->mpllb_div2);

drivers/gpu/drm/i915/display/intel_snps_phy.c

1835

intel_de_write(display, SNPS_PHY_MPLLB_SSCEN(phy), pll_state->mpllb_sscen);

drivers/gpu/drm/i915/display/intel_snps_phy.c

1836

intel_de_write(display, SNPS_PHY_MPLLB_SSCSTEP(phy), pll_state->mpllb_sscstep);

drivers/gpu/drm/i915/display/intel_snps_phy.c

1837

intel_de_write(display, SNPS_PHY_MPLLB_FRACN1(phy), pll_state->mpllb_fracn1);

drivers/gpu/drm/i915/display/intel_snps_phy.c

1838

intel_de_write(display, SNPS_PHY_MPLLB_FRACN2(phy), pll_state->mpllb_fracn2);

drivers/gpu/drm/i915/display/intel_snps_phy.c

1859

pll_state->mpllb_div | SNPS_PHY_MPLLB_FORCE_EN);

drivers/gpu/drm/i915/display/intel_snps_phy.c

1919

const struct intel_mpllb_state *pll_state)

drivers/gpu/drm/i915/display/intel_snps_phy.c

1930

refclk >>= REG_FIELD_GET(SNPS_PHY_MPLLB_REF_CLK_DIV, pll_state->mpllb_div2) - 1;

drivers/gpu/drm/i915/display/intel_snps_phy.c

1932

frac_en = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_EN, pll_state->mpllb_fracn1);

drivers/gpu/drm/i915/display/intel_snps_phy.c

1935

frac_quot = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_QUOT, pll_state->mpllb_fracn2);

drivers/gpu/drm/i915/display/intel_snps_phy.c

1936

frac_rem = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_REM, pll_state->mpllb_fracn2);

drivers/gpu/drm/i915/display/intel_snps_phy.c

1937

frac_den = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_DEN, pll_state->mpllb_fracn1);

drivers/gpu/drm/i915/display/intel_snps_phy.c

1940

multiplier = REG_FIELD_GET(SNPS_PHY_MPLLB_MULTIPLIER, pll_state->mpllb_div2) / 2 + 16;

drivers/gpu/drm/i915/display/intel_snps_phy.c

1942

tx_clk_div = REG_FIELD_GET(SNPS_PHY_MPLLB_TX_CLK_DIV, pll_state->mpllb_div);

drivers/gpu/drm/i915/display/intel_snps_phy.c

1950

struct intel_mpllb_state *pll_state)

drivers/gpu/drm/i915/display/intel_snps_phy.c

1955

pll_state->mpllb_cp = intel_de_read(display, SNPS_PHY_MPLLB_CP(phy));

drivers/gpu/drm/i915/display/intel_snps_phy.c

1956

pll_state->mpllb_div = intel_de_read(display, SNPS_PHY_MPLLB_DIV(phy));

drivers/gpu/drm/i915/display/intel_snps_phy.c

1957

pll_state->mpllb_div2 = intel_de_read(display, SNPS_PHY_MPLLB_DIV2(phy));

drivers/gpu/drm/i915/display/intel_snps_phy.c

1958

pll_state->mpllb_sscen = intel_de_read(display, SNPS_PHY_MPLLB_SSCEN(phy));

drivers/gpu/drm/i915/display/intel_snps_phy.c

1959

pll_state->mpllb_sscstep = intel_de_read(display, SNPS_PHY_MPLLB_SSCSTEP(phy));

drivers/gpu/drm/i915/display/intel_snps_phy.c

1960

pll_state->mpllb_fracn1 = intel_de_read(display, SNPS_PHY_MPLLB_FRACN1(phy));

drivers/gpu/drm/i915/display/intel_snps_phy.c

1961

pll_state->mpllb_fracn2 = intel_de_read(display, SNPS_PHY_MPLLB_FRACN2(phy));

drivers/gpu/drm/i915/display/intel_snps_phy.c

1969

pll_state->ref_control = intel_de_read(display, SNPS_PHY_REF_CONTROL(phy)) &

drivers/gpu/drm/i915/display/intel_snps_phy.c

1978

pll_state->mpllb_div &= ~SNPS_PHY_MPLLB_FORCE_EN;

drivers/gpu/drm/i915/display/intel_snps_phy.h

29

struct intel_mpllb_state *pll_state);

drivers/gpu/drm/i915/display/intel_snps_phy.h

31

const struct intel_mpllb_state *pll_state);

sound/soc/codecs/wm8580.c

248

struct pll_state a;

sound/soc/codecs/wm8580.c

249

struct pll_state b;

sound/soc/codecs/wm8580.c

466

struct pll_state *state;