pll_ratio
u32 pll_ratio = 0;
pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
u32 pll_ratio = 0;
pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
reg_910 = (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw->pll_range << 1) | bw->pll_reset;
reg_907 |= (bw->pll_ratio & 0x3f) << 9;
dib7000m_write_word(state, 907, (bw->pll_prediv << 8) | (bw->pll_ratio << 0));
dib7000p_write_word(state, 1856, (!bw->pll_reset << 13) | (bw->pll_range << 12) | (bw->pll_ratio << 6) | (bw->pll_prediv));
clk_cfg0 = (1 << 15) | ((bw->pll_ratio & 0x3f) << 9) |
dib7000p_write_word(state, 903, (bw->pll_prediv << 5) | (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw->pll_range << 1) | bw->pll_reset);
if (loopdiv && bw && (bw->pll_prediv != prediv || bw->pll_ratio != loopdiv)) {
dprintk("Updating pll (prediv: old = %d new = %d ; loopdiv : old = %d new = %d)\n", prediv, bw->pll_prediv, loopdiv, bw->pll_ratio);
dib7000p_write_word(state, 1856, reg_1856 | ((bw->pll_ratio & 0x3f) << 6) | (bw->pll_prediv & 0x3f));
internal = 1000 * (xtal / bw->pll_prediv) * bw->pll_ratio; /* new internal */
(pll->pll_prediv << 8) | (pll->pll_ratio << 0));
(pll->pll_range<<12) | (pll->pll_ratio<<6) |
pll->pll_ratio == loopdiv))
dprintk("Updating pll (prediv: old = %d new = %d ; loopdiv : old = %d new = %d)\n", prediv, pll->pll_prediv, loopdiv, pll->pll_ratio);
((pll->pll_ratio & 0x3f) << 6) |
internal = 1000 * (xtal/pll->pll_prediv) * pll->pll_ratio;
dprintk("PLL: New Setting for %d MHz Bandwidth (prediv: %d, ratio: %d)\n", bw/1000, state->cfg.pll->pll_prediv, state->cfg.pll->pll_ratio);
ratio = state->cfg.pll->pll_ratio;
u8 pll_ratio;
.pll_ratio = 20,
.pll_ratio = 20,
.pll_ratio = 20,
.pll_ratio = 18,
u8 pll_ratio;
for (pll_ratio = 17; pll_ratio <= 20; pll_ratio++) {
freq_adc = 12 * pll_ratio * (1 << 8) / 16;
deb_info("PLL ratio=%i rest=%i\n", pll_ratio, rest);
optimal_pll_ratio = pll_ratio;
u8 pll_ratio, band = BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000);
pll_ratio = dib8090_compute_pll_parameters(fe);
if (pll_ratio == 17)
else if (pll_ratio == 18)
else if (pll_ratio == 19)
state->dib8000_ops.update_pll(fe, &dib8090_pll_config_12mhz, fe->dtv_property_cache.bandwidth_hz / 1000, pll_ratio);
.pll_ratio = 9,
pll.pll_ratio = adc.pll_loopdiv;
.pll_ratio = 8,
pll.pll_ratio = adc.pll_loopdiv;
.pll_ratio = 5,
.pll_ratio = 8,
.pll_ratio = 8,
.pll_ratio = 8,
.pll_ratio = 20,
static struct pll_ratio sata_pll_ratio = {
static struct pll_ratio pcie_pll_ratio = {
static struct pll_ratio usb3_pll_ratio = {
struct pll_ratio *pll_ratio)
writeb_relaxed(pll_ratio->clk_ref, base + MIPHY_PLL_CLKREF_FREQ);
writeb_relaxed(pll_ratio->calset_1, base + MIPHY_PLL_CALSET_1);
writeb_relaxed(pll_ratio->calset_2, base + MIPHY_PLL_CALSET_2);
writeb_relaxed(pll_ratio->calset_3, base + MIPHY_PLL_CALSET_3);
writeb_relaxed(pll_ratio->calset_4, base + MIPHY_PLL_CALSET_4);
writeb_relaxed(pll_ratio->cal_ctrl, base + MIPHY_PLL_CALSET_CTRL);
struct pll_ratio *pll_ratio)
writeb_relaxed(pll_ratio->clk_ref, base + MIPHY_PLL_CLKREF_FREQ);
u64 f2, f2_max, pll_ratio;
pll_ratio = div_u64(f2 << 28, pll_in);
if (((pll_ratio >> 28) & 0xF) < NAU_PLL_OPTOP_MIN) {
pll_ratio <<= 1;
pll_param->pll_int = (pll_ratio >> 28) & 0xF;
pll_param->pll_frac = ((pll_ratio & 0xFFFFFFF) >> 4);
u64 f2, f2_max, pll_ratio;
pll_ratio = div_u64(f2 << 28, pll_in);
if (((pll_ratio >> 28) & 0xF) < NAU_PLL_OPTOP_MIN) {
pll_ratio <<= 1;
pll_param->pll_int = (pll_ratio >> 28) & 0xF;
pll_param->pll_frac = ((pll_ratio & 0xFFFFFFF) >> 4);