drivers/clk/tegra/clk-pll.c

1207

static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,

drivers/clk/tegra/clk-pll.c

1210

u16 mdiv = parent_rate / pll_params->cf_min;

drivers/clk/tegra/clk-pll.c

1212

if (pll_params->flags & TEGRA_MDIV_NEW)

drivers/clk/tegra/clk-pll.c

1213

return (!pll_params->mdiv_default ? mdiv :

drivers/clk/tegra/clk-pll.c

1214

min(mdiv, pll_params->mdiv_default));

drivers/clk/tegra/clk-pll.c

1216

if (pll_params->mdiv_default)

drivers/clk/tegra/clk-pll.c

1217

return pll_params->mdiv_default;

drivers/clk/tegra/clk-pll.c

1219

if (parent_rate > pll_params->cf_max)

drivers/clk/tegra/clk-pll.c

1272

static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,

drivers/clk/tegra/clk-pll.c

1301

val = step_a << pll_params->stepa_shift;

drivers/clk/tegra/clk-pll.c

1302

val |= step_b << pll_params->stepb_shift;

drivers/clk/tegra/clk-pll.c

1303

writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);

drivers/clk/tegra/clk-pll.c

1880

void __iomem *pmc, struct tegra_clk_pll_params *pll_params,

drivers/clk/tegra/clk-pll.c

1892

pll->params = pll_params;

drivers/clk/tegra/clk-pll.c

1895

if (!pll_params->div_nmp)

drivers/clk/tegra/clk-pll.c

1896

pll_params->div_nmp = &default_nmp;

drivers/clk/tegra/clk-pll.c

1932

unsigned long flags, struct tegra_clk_pll_params *pll_params,

drivers/clk/tegra/clk-pll.c

1938

pll_params->flags |= TEGRA_PLL_BYPASS;

drivers/clk/tegra/clk-pll.c

1940

pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);

drivers/clk/tegra/clk-pll.c

1963

unsigned long flags, struct tegra_clk_pll_params *pll_params,

drivers/clk/tegra/clk-pll.c

1969

pll_params->flags |= TEGRA_PLL_BYPASS;

drivers/clk/tegra/clk-pll.c

1971

if (!pll_params->div_nmp)

drivers/clk/tegra/clk-pll.c

1972

pll_params->div_nmp = &pll_e_nmp;

drivers/clk/tegra/clk-pll.c

1974

pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);

drivers/clk/tegra/clk-pll.c

1988

struct tegra_clk_pll_params *pll_params, spinlock_t *lock)

drivers/clk/tegra/clk-pll.c

1993

pll_params->flags |= TEGRA_PLLU;

drivers/clk/tegra/clk-pll.c

1995

pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);

drivers/clk/tegra/clk-pll.c

2055

struct tegra_clk_pll_params *pll_params,

drivers/clk/tegra/clk-pll.c

2070

if (!pll_params->pdiv_tohw)

drivers/clk/tegra/clk-pll.c

2075

pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);

drivers/clk/tegra/clk-pll.c

2077

if (pll_params->adjust_vco)

drivers/clk/tegra/clk-pll.c

2078

pll_params->vco_min = pll_params->adjust_vco(pll_params,

drivers/clk/tegra/clk-pll.c

2085

if (!pll_params->set_defaults) {

drivers/clk/tegra/clk-pll.c

2088

err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate);

drivers/clk/tegra/clk-pll.c

2092

val = readl_relaxed(clk_base + pll_params->base_reg);

drivers/clk/tegra/clk-pll.c

2093

val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);

drivers/clk/tegra/clk-pll.c

2096

WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));

drivers/clk/tegra/clk-pll.c

2098

val_iddq |= BIT(pll_params->iddq_bit_idx);

drivers/clk/tegra/clk-pll.c

2100

clk_base + pll_params->iddq_reg);

drivers/clk/tegra/clk-pll.c

2104

pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);

drivers/clk/tegra/clk-pll.c

2119

struct tegra_clk_pll_params *pll_params,

drivers/clk/tegra/clk-pll.c

2126

pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);

drivers/clk/tegra/clk-pll.c

2128

if (pll_params->adjust_vco)

drivers/clk/tegra/clk-pll.c

2129

pll_params->vco_min = pll_params->adjust_vco(pll_params,

drivers/clk/tegra/clk-pll.c

2132

pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);

drivers/clk/tegra/clk-pll.c

2140

WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) &

drivers/clk/tegra/clk-pll.c

2141

BIT(pll_params->iddq_bit_idx));

drivers/clk/tegra/clk-pll.c

2145

m = _pll_fixed_mdiv(pll_params, parent_rate);

drivers/clk/tegra/clk-pll.c

2147

val |= (pll_params->vco_min / parent_rate) << divn_shift(pll);

drivers/clk/tegra/clk-pll.c

2168

struct tegra_clk_pll_params *pll_params,

drivers/clk/tegra/clk-pll.c

2175

if (!pll_params->pdiv_tohw)

drivers/clk/tegra/clk-pll.c

2187

pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);

drivers/clk/tegra/clk-pll.c

2189

if (pll_params->adjust_vco)

drivers/clk/tegra/clk-pll.c

2190

pll_params->vco_min = pll_params->adjust_vco(pll_params,

drivers/clk/tegra/clk-pll.c

2193

pll_params->flags |= TEGRA_PLL_BYPASS;

drivers/clk/tegra/clk-pll.c

2194

pll_params->flags |= TEGRA_PLLM;

drivers/clk/tegra/clk-pll.c

2195

pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);

drivers/clk/tegra/clk-pll.c

2210

struct tegra_clk_pll_params *pll_params,

drivers/clk/tegra/clk-pll.c

2214

const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;

drivers/clk/tegra/clk-pll.c

2231

pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);

drivers/clk/tegra/clk-pll.c

2233

pll_params->flags |= TEGRA_PLL_BYPASS;

drivers/clk/tegra/clk-pll.c

2234

pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);

drivers/clk/tegra/clk-pll.c

2247

cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);

drivers/clk/tegra/clk-pll.c

2248

cfg.n = cfg.m * pll_params->vco_min / parent_rate;

drivers/clk/tegra/clk-pll.c

2267

pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);

drivers/clk/tegra/clk-pll.c

2268

pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);

drivers/clk/tegra/clk-pll.c

2269

pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);

drivers/clk/tegra/clk-pll.c

2284

struct tegra_clk_pll_params *pll_params,

drivers/clk/tegra/clk-pll.c

2290

pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);

drivers/clk/tegra/clk-pll.c

2307

struct tegra_clk_pll_params *pll_params,

drivers/clk/tegra/clk-pll.c

2313

pll_params->flags |= TEGRA_PLLU;

drivers/clk/tegra/clk-pll.c

2315

pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);

drivers/clk/tegra/clk-pll.c

2341

struct tegra_clk_pll_params *pll_params,

drivers/clk/tegra/clk-pll.c

2351

if (!pll_params->div_nmp)

drivers/clk/tegra/clk-pll.c

2361

pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);

drivers/clk/tegra/clk-pll.c

2371

pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);

drivers/clk/tegra/clk-pll.c

2375

cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);

drivers/clk/tegra/clk-pll.c

2376

cfg.n = cfg.m * pll_params->vco_min / parent_rate;

drivers/clk/tegra/clk-pll.c

2378

for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++)

drivers/clk/tegra/clk-pll.c

2385

cfg.p = pll_params->pdiv_tohw[i-1].hw_val;

drivers/clk/tegra/clk-pll.c

2390

pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll);

drivers/clk/tegra/clk-pll.c

2391

pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll);

drivers/clk/tegra/clk-pll.c

2392

pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);

drivers/clk/tegra/clk-pll.c

2395

val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);

drivers/clk/tegra/clk-pll.c

2397

if (val_iddq & BIT(pll_params->iddq_bit_idx)) {

drivers/clk/tegra/clk-pll.c

2403

val_iddq |= BIT(pll_params->iddq_bit_idx);

drivers/clk/tegra/clk-pll.c

2404

writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);

drivers/clk/tegra/clk-pll.c

2424

struct tegra_clk_pll_params *pll_params,

drivers/clk/tegra/clk-pll.c

2430

pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);

drivers/clk/tegra/clk-pll.c

2432

if (pll_params->adjust_vco)

drivers/clk/tegra/clk-pll.c

2433

pll_params->vco_min = pll_params->adjust_vco(pll_params,

drivers/clk/tegra/clk-pll.c

2436

pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);

drivers/clk/tegra/clk-pll.c

2587

struct tegra_clk_pll_params *pll_params,

drivers/clk/tegra/clk-pll.c

2593

pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);

drivers/clk/tegra/clk-pll.c

2610

struct tegra_clk_pll_params *pll_params,

drivers/clk/tegra/clk-pll.c

2614

const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;

drivers/clk/tegra/clk-pll.c

2630

pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);

drivers/clk/tegra/clk-pll.c

2632

if (pll_params->adjust_vco)

drivers/clk/tegra/clk-pll.c

2633

pll_params->vco_min = pll_params->adjust_vco(pll_params,

drivers/clk/tegra/clk-pll.c

2636

pll_params->flags |= TEGRA_PLL_BYPASS;

drivers/clk/tegra/clk-pll.c

2637

pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);

drivers/clk/tegra/clk-pll.c

2652

struct tegra_clk_pll_params *pll_params,

drivers/clk/tegra/clk-pll.c

2660

if (!pll_params->div_nmp)

drivers/clk/tegra/clk-pll.c

2670

val = readl_relaxed(clk_base + pll_params->base_reg);

drivers/clk/tegra/clk-pll.c

2678

pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);

drivers/clk/tegra/clk-pll.c

2680

if (pll_params->adjust_vco)

drivers/clk/tegra/clk-pll.c

2681

pll_params->vco_min = pll_params->adjust_vco(pll_params,

drivers/clk/tegra/clk-pll.c

2684

pll_params->flags |= TEGRA_PLL_BYPASS;

drivers/clk/tegra/clk-pll.c

2685

pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);

drivers/clk/tegra/clk-pll.c

2701

struct tegra_clk_pll_params *pll_params,

drivers/clk/tegra/clk-pll.c

2708

if (!pll_params->pdiv_tohw)

drivers/clk/tegra/clk-pll.c

2720

pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);

drivers/clk/tegra/clk-pll.c

2722

if (pll_params->adjust_vco)

drivers/clk/tegra/clk-pll.c

2723

pll_params->vco_min = pll_params->adjust_vco(pll_params,

drivers/clk/tegra/clk-pll.c

2726

pll_params->flags |= TEGRA_PLL_BYPASS;

drivers/clk/tegra/clk-pll.c

2727

pll_params->flags |= TEGRA_PLLMB;

drivers/clk/tegra/clk-pll.c

2728

pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);

drivers/clk/tegra/clk-tegra-audio.c

184

clk_base, pmc_base, 0, info->pll_params,

drivers/clk/tegra/clk-tegra-periph.c

1024

struct tegra_clk_pll_params *pll_params)

drivers/clk/tegra/clk-tegra-periph.c

1026

init_pllp(clk_base, pmc_base, tegra_clks, pll_params);

drivers/clk/tegra/clk-tegra-periph.c

941

struct tegra_clk_pll_params *pll_params)

drivers/clk/tegra/clk-tegra-periph.c

951

pmc_base, 0, pll_params, NULL);

drivers/clk/tegra/clk.h

344

unsigned long (*adjust_vco)(struct tegra_clk_pll_params *pll_params,

drivers/clk/tegra/clk.h

397

struct tegra_clk_pll_params *pll_params;

drivers/clk/tegra/clk.h

406

unsigned long flags, struct tegra_clk_pll_params *pll_params,

drivers/clk/tegra/clk.h

411

unsigned long flags, struct tegra_clk_pll_params *pll_params,

drivers/clk/tegra/clk.h

417

struct tegra_clk_pll_params *pll_params,

drivers/clk/tegra/clk.h

423

struct tegra_clk_pll_params *pll_params,

drivers/clk/tegra/clk.h

429

struct tegra_clk_pll_params *pll_params,

drivers/clk/tegra/clk.h

435

struct tegra_clk_pll_params *pll_params,

drivers/clk/tegra/clk.h

441

struct tegra_clk_pll_params *pll_params,

drivers/clk/tegra/clk.h

447

struct tegra_clk_pll_params *pll_params,

drivers/clk/tegra/clk.h

453

struct tegra_clk_pll_params *pll_params,

drivers/clk/tegra/clk.h

459

struct tegra_clk_pll_params *pll_params,

drivers/clk/tegra/clk.h

465

struct tegra_clk_pll_params *pll_params,

drivers/clk/tegra/clk.h

470

struct tegra_clk_pll_params *pll_params,

drivers/clk/tegra/clk.h

476

struct tegra_clk_pll_params *pll_params,

drivers/clk/tegra/clk.h

481

struct tegra_clk_pll_params *pll_params,

drivers/clk/tegra/clk.h

487

struct tegra_clk_pll_params *pll_params,

drivers/clk/tegra/clk.h

493

struct tegra_clk_pll_params *pll_params,

drivers/clk/tegra/clk.h

865

struct tegra_clk_pll_params *pll_params);

drivers/clk/tegra/clk.h

874

struct tegra_clk_pll_params *pll_params);

drivers/clk/tegra/clk.h

877

struct tegra_clk_pll_params *pll_params);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2723

struct skl_wrpll_params *pll_params)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2735

*pll_params = params[i].wrpll;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2745

struct skl_wrpll_params *pll_params)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2756

*pll_params = tgl_tbt_pll_19_2MHz_values;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2759

*pll_params = tgl_tbt_pll_24MHz_values;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2769

*pll_params = icl_tbt_pll_19_2MHz_values;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2772

*pll_params = icl_tbt_pll_24MHz_values;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2914

const struct skl_wrpll_params *pll_params,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2918

u32 dco_fraction = pll_params->dco_fraction;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2924

pll_params->dco_integer;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2926

hw_state->cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params->qdiv_ratio) |

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2927

DPLL_CFGCR1_QDIV_MODE(pll_params->qdiv_mode) |

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2928

DPLL_CFGCR1_KDIV(pll_params->kdiv) |

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2929

DPLL_CFGCR1_PDIV(pll_params->pdiv);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3344

struct skl_wrpll_params pll_params = {};

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3349

ret = icl_calc_wrpll(crtc_state, &pll_params);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3351

ret = icl_calc_dp_combo_pll(crtc_state, &pll_params);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3356

icl_calc_dpll_state(display, &pll_params, &port_dpll->hw_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3438

struct skl_wrpll_params pll_params = {};

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3442

ret = icl_calc_tbt_pll(crtc_state, &pll_params);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3446

icl_calc_dpll_state(display, &pll_params, &port_dpll->hw_state);

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

140

struct pll_output_params *pll_params)

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

202

pll_params->ssc_up_spread = ssc_up_spread;

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

203

pll_params->mpll_div5_en = mpll_div5_en;

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

204

pll_params->hdmi_div = hdmi_div;

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

205

pll_params->ana_cp_int = ana_cp_int;

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

206

pll_params->refclk_postscalar = refclk_postscalar;

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

207

pll_params->tx_clk_div = tx_clk_div;

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

208

pll_params->fracn_quot = fracn_quot;

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

209

pll_params->fracn_rem = fracn_rem;

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

210

pll_params->fracn_den = fracn_den;

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

211

pll_params->fracn_en = fracn_en;

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

212

pll_params->pmix_en = pmix_en;

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

213

pll_params->multiplier = multiplier;

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

214

pll_params->ana_cp_prop = ana_cp_prop;

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

215

pll_params->mpll_ana_v2i = mpll_ana_v2i;

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

216

pll_params->ana_freq_vco = ana_freq_vco;

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

251

struct pll_output_params pll_params;

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

260

prescaler_divider, &pll_params);

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

266

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, pll_params.ana_cp_int) |

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

267

REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, pll_params.ana_cp_prop) |

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

271

REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, pll_params.mpll_div5_en) |

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

272

REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, pll_params.tx_clk_div) |

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

273

REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, pll_params.pmix_en) |

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

274

REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, pll_params.mpll_ana_v2i) |

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

275

REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, pll_params.ana_freq_vco);

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

278

REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, pll_params.multiplier) |

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

279

REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, pll_params.hdmi_div);

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

282

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, pll_params.fracn_en) |

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

283

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, pll_params.fracn_den);

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

285

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, pll_params.fracn_quot) |

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

286

REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, pll_params.fracn_rem);

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

288

REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, pll_params.ssc_up_spread);

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

322

struct pll_output_params pll_params;

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

333

&pll_params);

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

339

pll_state->pll[0] = REG_FIELD_PREP(C10_PLL0_DIV5CLK_EN, pll_params.mpll_div5_en) |

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

340

REG_FIELD_PREP(C10_PLL0_FRACEN, pll_params.fracn_en) |

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

341

REG_FIELD_PREP(C10_PLL0_PMIX_EN, pll_params.pmix_en) |

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

342

REG_FIELD_PREP(C10_PLL0_ANA_FREQ_VCO_MASK, pll_params.ana_freq_vco);

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

343

pll_state->pll[2] = REG_FIELD_PREP(C10_PLL2_MULTIPLIERL_MASK, pll_params.multiplier);

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

344

pll_state->pll[3] = REG_FIELD_PREP(C10_PLL3_MULTIPLIERH_MASK, pll_params.multiplier >> 8);

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

345

pll_state->pll[8] = REG_FIELD_PREP(C10_PLL8_SSC_UP_SPREAD, pll_params.ssc_up_spread);

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

346

pll_state->pll[9] = REG_FIELD_PREP(C10_PLL9_FRACN_DENL_MASK, pll_params.fracn_den);

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

347

pll_state->pll[10] = REG_FIELD_PREP(C10_PLL10_FRACN_DENH_MASK, pll_params.fracn_den >> 8);

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

348

pll_state->pll[11] = REG_FIELD_PREP(C10_PLL11_FRACN_QUOT_L_MASK, pll_params.fracn_quot);

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

350

pll_params.fracn_quot >> 8);

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

352

pll_state->pll[13] = REG_FIELD_PREP(C10_PLL13_FRACN_REM_L_MASK, pll_params.fracn_rem);

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

353

pll_state->pll[14] = REG_FIELD_PREP(C10_PLL14_FRACN_REM_H_MASK, pll_params.fracn_rem >> 8);

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

354

pll_state->pll[15] = REG_FIELD_PREP(C10_PLL15_TXCLKDIV_MASK, pll_params.tx_clk_div) |

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

355

REG_FIELD_PREP(C10_PLL15_HDMIDIV_MASK, pll_params.hdmi_div);

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

356

pll_state->pll[16] = REG_FIELD_PREP(C10_PLL16_ANA_CPINT, pll_params.ana_cp_int) |

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

359

REG_FIELD_PREP(C10_PLL17_ANA_CPPROP_L_MASK, pll_params.ana_cp_prop);

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

361

REG_FIELD_PREP(C10_PLL18_ANA_CPPROP_H_MASK, pll_params.ana_cp_prop >> 2) |

drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

365

REG_FIELD_PREP(C10_PLL19_ANA_V2I_MASK, pll_params.mpll_ana_v2i);

drivers/phy/st/phy-stm32-usbphyc.c

205

struct pll_params *pll_params)

drivers/phy/st/phy-stm32-usbphyc.c

223

pll_params->ndiv = (u8)ndiv;

drivers/phy/st/phy-stm32-usbphyc.c

228

pll_params->frac = (u16)frac;

drivers/phy/st/phy-stm32-usbphyc.c

233

struct pll_params pll_params;

drivers/phy/st/phy-stm32-usbphyc.c

245

stm32_usbphyc_get_pll_params(clk_rate, &pll_params);

drivers/phy/st/phy-stm32-usbphyc.c

246

ndiv = FIELD_PREP(PLLNDIV, pll_params.ndiv);

drivers/phy/st/phy-stm32-usbphyc.c

247

frac = FIELD_PREP(PLLFRACIN, pll_params.frac);

drivers/phy/st/phy-stm32-usbphyc.c

251

if (pll_params.frac)