pll_mode
u32 pll_mode, pll_m, pll_n;
pll_mode = (readl(clkdata->syscon_base) >> 6) & 3;
switch (pll_mode) {
static inline enum pll_mode pll_frac_get_mode(struct clk_hw *hw)
static inline void pll_frac_set_mode(struct clk_hw *hw, enum pll_mode mode)
int ret, pll_mode;
ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &pll_mode);
if (pll_mode & PLL_OUTCTRL)
enum pll_mode mode;
static inline enum pll_mode zynqmp_pll_get_mode(struct clk_hw *hw)
w9116_features->pll_mode = common->w9116_features.pll_mode;
common->w9116_features.pll_mode = 0x0;
u8 pll_mode;
u8 pll_mode;
enum pll_mode *mode)
enum pll_mode mode)
enum pll_mode mode)
enum pll_mode mode = PLL_MODE_DISABLED;
enum pll_mode mode)
if (channel->pll_mode == mode)
channel->pll_mode = mode;
enum pll_mode pll_mode;
u8 pll_mode;
pll_ratio_table[i].pll_mode
u8 pll_mode;
FIELD_PREP(CS42L84_PLL_CTL1_MODE, pll_ratio_table[i].pll_mode));
u8 pll_mode;
pll_entry->pll_mode << CS43130_PLL_MODE_SHIFT);
static int adc3xxx_parse_pll_mode(uint32_t val, unsigned int *pll_mode)
*pll_mode = val;
params_rate(params), adc3xxx->pll_mode);
static const char *adc3xxx_pll_mode_text(int pll_mode)
switch (pll_mode) {
ret = adc3xxx_parse_pll_mode(clk_id, &adc3xxx->pll_mode);
freq, adc3xxx_pll_mode_text(adc3xxx->pll_mode));
unsigned int pll_mode;
static int adc3xxx_get_divs(struct device *dev, int mclk, int rate, int pll_mode)
mclk, rate, pll_mode);
if ((pll_mode == ADC3XXX_PLL_BYPASS && mode->pll_p) ||
(pll_mode == ADC3XXX_PLL_ENABLE && !mode->pll_p))