drivers/clk/baikal-t1/clk-ccu-pll.c

153

const struct ccu_pll_info *info = &pll_info[idx];

drivers/clk/baikal-t1/clk-ccu-pll.c

186

if (!!(pll_info[idx].features & CCU_PLL_BASIC) ^ defer)

drivers/clk/baikal-t1/clk-ccu-pll.c

201

if (!!(pll_info[idx].features & CCU_PLL_BASIC) ^ defer)

drivers/clk/baikal-t1/clk-ccu-pll.c

45

#define CCU_PLL_NUM ARRAY_SIZE(pll_info)

drivers/clk/baikal-t1/clk-ccu-pll.c

65

static const struct ccu_pll_info pll_info[] = {

drivers/clk/baikal-t1/clk-ccu-pll.c

92

if (pll_info[idx].id == clk_id)

drivers/clk/ingenic/cgu.c

100

if (pll_info->od_bits > 0) {

drivers/clk/ingenic/cgu.c

101

od_enc = ctl >> pll_info->od_shift;

drivers/clk/ingenic/cgu.c

102

od_enc &= GENMASK(pll_info->od_bits - 1, 0);

drivers/clk/ingenic/cgu.c

105

if (pll_info->bypass_bit >= 0) {

drivers/clk/ingenic/cgu.c

106

ctl = readl(cgu->base + pll_info->bypass_reg);

drivers/clk/ingenic/cgu.c

108

bypass = !!(ctl & BIT(pll_info->bypass_bit));

drivers/clk/ingenic/cgu.c

114

for (od = 0; od < pll_info->od_max; od++)

drivers/clk/ingenic/cgu.c

115

if (pll_info->od_encoding[od] == od_enc)

drivers/clk/ingenic/cgu.c

119

if (pll_info->od_max == 0)

drivers/clk/ingenic/cgu.c

120

BUG_ON(pll_info->od_bits != 0);

drivers/clk/ingenic/cgu.c

122

BUG_ON(od == pll_info->od_max);

drivers/clk/ingenic/cgu.c

125

return div_u64((u64)parent_rate * m * pll_info->rate_multiplier,

drivers/clk/ingenic/cgu.c

130

ingenic_pll_calc_m_n_od(const struct ingenic_cgu_pll_info *pll_info,

drivers/clk/ingenic/cgu.c

141

n = min_t(unsigned int, n, 1 << pll_info->n_bits);

drivers/clk/ingenic/cgu.c

142

n = max_t(unsigned int, n, pll_info->n_offset);

drivers/clk/ingenic/cgu.c

145

m = min_t(unsigned int, m, 1 << pll_info->m_bits);

drivers/clk/ingenic/cgu.c

146

m = max_t(unsigned int, m, pll_info->m_offset);

drivers/clk/ingenic/cgu.c

158

const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;

drivers/clk/ingenic/cgu.c

161

if (pll_info->calc_m_n_od)

drivers/clk/ingenic/cgu.c

162

(*pll_info->calc_m_n_od)(pll_info, rate, parent_rate, &m, &n, &od);

drivers/clk/ingenic/cgu.c

164

ingenic_pll_calc_m_n_od(pll_info, rate, parent_rate, &m, &n, &od);

drivers/clk/ingenic/cgu.c

173

return div_u64((u64)parent_rate * m * pll_info->rate_multiplier,

drivers/clk/ingenic/cgu.c

190

const struct ingenic_cgu_pll_info *pll_info)

drivers/clk/ingenic/cgu.c

194

if (pll_info->stable_bit < 0)

drivers/clk/ingenic/cgu.c

197

return readl_poll_timeout(cgu->base + pll_info->reg, ctl,

drivers/clk/ingenic/cgu.c

198

ctl & BIT(pll_info->stable_bit),

drivers/clk/ingenic/cgu.c

209

const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;

drivers/clk/ingenic/cgu.c

222

ctl = readl(cgu->base + pll_info->reg);

drivers/clk/ingenic/cgu.c

224

ctl &= ~(GENMASK(pll_info->m_bits - 1, 0) << pll_info->m_shift);

drivers/clk/ingenic/cgu.c

225

ctl |= (m - pll_info->m_offset) << pll_info->m_shift;

drivers/clk/ingenic/cgu.c

227

ctl &= ~(GENMASK(pll_info->n_bits - 1, 0) << pll_info->n_shift);

drivers/clk/ingenic/cgu.c

228

ctl |= (n - pll_info->n_offset) << pll_info->n_shift;

drivers/clk/ingenic/cgu.c

230

if (pll_info->od_bits > 0) {

drivers/clk/ingenic/cgu.c

231

ctl &= ~(GENMASK(pll_info->od_bits - 1, 0) << pll_info->od_shift);

drivers/clk/ingenic/cgu.c

232

ctl |= pll_info->od_encoding[od - 1] << pll_info->od_shift;

drivers/clk/ingenic/cgu.c

235

writel(ctl, cgu->base + pll_info->reg);

drivers/clk/ingenic/cgu.c

237

if (pll_info->set_rate_hook)

drivers/clk/ingenic/cgu.c

238

pll_info->set_rate_hook(pll_info, rate, parent_rate);

drivers/clk/ingenic/cgu.c

241

if (pll_info->enable_bit >= 0 && (ctl & BIT(pll_info->enable_bit)))

drivers/clk/ingenic/cgu.c

242

ret = ingenic_pll_check_stable(cgu, pll_info);

drivers/clk/ingenic/cgu.c

254

const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;

drivers/clk/ingenic/cgu.c

259

if (pll_info->enable_bit < 0)

drivers/clk/ingenic/cgu.c

263

if (pll_info->bypass_bit >= 0) {

drivers/clk/ingenic/cgu.c

264

ctl = readl(cgu->base + pll_info->bypass_reg);

drivers/clk/ingenic/cgu.c

266

ctl &= ~BIT(pll_info->bypass_bit);

drivers/clk/ingenic/cgu.c

268

writel(ctl, cgu->base + pll_info->bypass_reg);

drivers/clk/ingenic/cgu.c

271

ctl = readl(cgu->base + pll_info->reg);

drivers/clk/ingenic/cgu.c

273

ctl |= BIT(pll_info->enable_bit);

drivers/clk/ingenic/cgu.c

275

writel(ctl, cgu->base + pll_info->reg);

drivers/clk/ingenic/cgu.c

277

ret = ingenic_pll_check_stable(cgu, pll_info);

drivers/clk/ingenic/cgu.c

288

const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;

drivers/clk/ingenic/cgu.c

292

if (pll_info->enable_bit < 0)

drivers/clk/ingenic/cgu.c

296

ctl = readl(cgu->base + pll_info->reg);

drivers/clk/ingenic/cgu.c

298

ctl &= ~BIT(pll_info->enable_bit);

drivers/clk/ingenic/cgu.c

300

writel(ctl, cgu->base + pll_info->reg);

drivers/clk/ingenic/cgu.c

309

const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;

drivers/clk/ingenic/cgu.c

312

if (pll_info->enable_bit < 0)

drivers/clk/ingenic/cgu.c

315

ctl = readl(cgu->base + pll_info->reg);

drivers/clk/ingenic/cgu.c

317

return !!(ctl & BIT(pll_info->enable_bit));

drivers/clk/ingenic/cgu.c

85

const struct ingenic_cgu_pll_info *pll_info;

drivers/clk/ingenic/cgu.c

91

pll_info = &clk_info->pll;

drivers/clk/ingenic/cgu.c

93

ctl = readl(cgu->base + pll_info->reg);

drivers/clk/ingenic/cgu.c

95

m = (ctl >> pll_info->m_shift) & GENMASK(pll_info->m_bits - 1, 0);

drivers/clk/ingenic/cgu.c

96

m += pll_info->m_offset;

drivers/clk/ingenic/cgu.c

97

n = (ctl >> pll_info->n_shift) & GENMASK(pll_info->n_bits - 1, 0);

drivers/clk/ingenic/cgu.c

98

n += pll_info->n_offset;

drivers/clk/ingenic/cgu.h

63

void (*calc_m_n_od)(const struct ingenic_cgu_pll_info *pll_info,

drivers/clk/ingenic/cgu.h

66

void (*set_rate_hook)(const struct ingenic_cgu_pll_info *pll_info,

drivers/clk/ingenic/jz4760-cgu.c

57

jz4760_cgu_calc_m_n_od(const struct ingenic_cgu_pll_info *pll_info,

drivers/clk/ingenic/jz4760-cgu.c

61

unsigned int m, n, od, m_max = (1 << pll_info->m_bits) - 1;

drivers/clk/ingenic/jz4760-cgu.c

67

n = clamp_val(n, 2, 1 << pll_info->n_bits);

drivers/clk/ingenic/x1000-cgu.c

174

x1000_i2spll_calc_m_n_od(const struct ingenic_cgu_pll_info *pll_info,

drivers/clk/ingenic/x1000-cgu.c

178

const unsigned long m_max = GENMASK(pll_info->m_bits - 1, 0);

drivers/clk/ingenic/x1000-cgu.c

179

const unsigned long n_max = GENMASK(pll_info->n_bits - 1, 0);

drivers/clk/ingenic/x1000-cgu.c

194

x1000_i2spll_set_rate_hook(const struct ingenic_cgu_pll_info *pll_info,

drivers/clk/visconti/pll-tmpv770x.c

56

static const struct visconti_pll_info pll_info[] __initconst = {

drivers/clk/visconti/pll-tmpv770x.c

85

visconti_register_plls(ctx, pll_info, ARRAY_SIZE(pll_info), &tmpv770x_pll_lock);

drivers/gpu/drm/amd/display/dc/bios/bios_parser.c

436

info->pll_info.crystal_frequency =

drivers/gpu/drm/amd/display/dc/bios/bios_parser.c

438

info->pll_info.min_input_pxl_clk_pll_frequency =

drivers/gpu/drm/amd/display/dc/bios/bios_parser.c

440

info->pll_info.max_input_pxl_clk_pll_frequency =

drivers/gpu/drm/amd/display/dc/bios/bios_parser.c

442

info->pll_info.min_output_pxl_clk_pll_frequency =

drivers/gpu/drm/amd/display/dc/bios/bios_parser.c

444

info->pll_info.max_output_pxl_clk_pll_frequency =

drivers/gpu/drm/amd/display/dc/bios/bios_parser.c

488

info->pll_info.crystal_frequency =

drivers/gpu/drm/amd/display/dc/bios/bios_parser.c

490

info->pll_info.min_input_pxl_clk_pll_frequency =

drivers/gpu/drm/amd/display/dc/bios/bios_parser.c

492

info->pll_info.max_input_pxl_clk_pll_frequency =

drivers/gpu/drm/amd/display/dc/bios/bios_parser.c

494

info->pll_info.min_output_pxl_clk_pll_frequency =

drivers/gpu/drm/amd/display/dc/bios/bios_parser.c

496

info->pll_info.max_output_pxl_clk_pll_frequency =

drivers/gpu/drm/amd/display/dc/bios/bios_parser.c

575

info->pll_info.crystal_frequency =

drivers/gpu/drm/amd/display/dc/bios/bios_parser.c

577

info->pll_info.min_input_pxl_clk_pll_frequency =

drivers/gpu/drm/amd/display/dc/bios/bios_parser.c

579

info->pll_info.max_input_pxl_clk_pll_frequency =

drivers/gpu/drm/amd/display/dc/bios/bios_parser.c

581

info->pll_info.min_output_pxl_clk_pll_frequency =

drivers/gpu/drm/amd/display/dc/bios/bios_parser.c

583

info->pll_info.max_output_pxl_clk_pll_frequency =

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

1806

info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

1809

if (info->pll_info.crystal_frequency == 0)

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

1810

info->pll_info.crystal_frequency = 27000;

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

1891

info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

1893

if (info->pll_info.crystal_frequency == 0) {

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

1895

info->pll_info.crystal_frequency = 27000;

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

1897

info->pll_info.crystal_frequency = 100000;

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

1964

info->pll_info.crystal_frequency = dce_info_v4_5->dce_refclk_10khz * 10;

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

1980

info->pll_info.crystal_frequency = dce_info_v4_4->dce_refclk_10khz * 10;

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

1997

info->pll_info.crystal_frequency = dce_info_v4_1->dce_refclk_10khz * 10;

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

2108

info->pll_info.crystal_frequency = dce_info_v4_5->dce_refclk_10khz * 10;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

379

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

1043

const struct audio_pll_info *pll_info,

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

1058

pll_info->audio_dto_source_clock_in_khz * 10;

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

1065

const struct audio_pll_info *pll_info)

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

1101

src_sel = pll_info->dto_source - DTO_SOURCE_ID0;

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

1123

pll_info,

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

1158

const struct audio_pll_info *pll_info)

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

1194

src_sel = pll_info->dto_source - DTO_SOURCE_ID0;

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

1216

pll_info,

drivers/gpu/drm/amd/display/dc/dce/dce_audio.h

180

const struct audio_pll_info *pll_info);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1603

calc_pll_cs->ref_freq_khz = fw_info->pll_info.crystal_frequency;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1605

fw_info->pll_info.min_output_pxl_clk_pll_frequency;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1607

fw_info->pll_info.max_output_pxl_clk_pll_frequency;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1614

fw_info->pll_info.max_input_pxl_clk_pll_frequency;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1621

fw_info->pll_info.min_input_pxl_clk_pll_frequency;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1730

clk_src->ref_freq_khz = clk_src->bios->fw_info.pll_info.crystal_frequency;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c

675

dce_i2c_hw->reference_frequency = (ctx->dc_bios->fw_info.pll_info.crystal_frequency) >> 1;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3146

dc->dml2_options.bbox_overrides.xtalclk_mhz = dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

704

dc->dml2_options.bbox_overrides.xtalclk_mhz = dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency / 1000.0;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1444

audio_output->pll_info.audio_dto_source_clock_in_khz =

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1449

audio_output->pll_info.dto_source =

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1454

audio_output->pll_info.ss_enabled = true;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1456

audio_output->pll_info.ss_percentage =

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2404

&audio_output.pll_info);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2410

&audio_output.pll_info);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2438

&audio_output.pll_info);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1794

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1799

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

244

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

248

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

684

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

689

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

137

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

142

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

821

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

825

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

170

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

175

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

183

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

187

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,

drivers/gpu/drm/amd/display/dc/inc/hw/audio.h

54

const struct audio_pll_info *pll_info);

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

226

soc_bb->xtalclk_mhz = dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency / 1000;

drivers/gpu/drm/amd/display/include/audio_types.h

112

struct audio_pll_info pll_info;

drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h

165

} pll_info;

drivers/gpu/drm/radeon/radeon_combios.c

717

uint16_t pll_info;

drivers/gpu/drm/radeon/radeon_combios.c

725

pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);

drivers/gpu/drm/radeon/radeon_combios.c

726

if (pll_info) {

drivers/gpu/drm/radeon/radeon_combios.c

727

rev = RBIOS8(pll_info);

drivers/gpu/drm/radeon/radeon_combios.c

730

p1pll->reference_freq = RBIOS16(pll_info + 0xe);

drivers/gpu/drm/radeon/radeon_combios.c

731

p1pll->reference_div = RBIOS16(pll_info + 0x10);

drivers/gpu/drm/radeon/radeon_combios.c

732

p1pll->pll_out_min = RBIOS32(pll_info + 0x12);

drivers/gpu/drm/radeon/radeon_combios.c

733

p1pll->pll_out_max = RBIOS32(pll_info + 0x16);

drivers/gpu/drm/radeon/radeon_combios.c

738

p1pll->pll_in_min = RBIOS32(pll_info + 0x36);

drivers/gpu/drm/radeon/radeon_combios.c

739

p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);

drivers/gpu/drm/radeon/radeon_combios.c

747

spll->reference_freq = RBIOS16(pll_info + 0x1a);

drivers/gpu/drm/radeon/radeon_combios.c

748

spll->reference_div = RBIOS16(pll_info + 0x1c);

drivers/gpu/drm/radeon/radeon_combios.c

749

spll->pll_out_min = RBIOS32(pll_info + 0x1e);

drivers/gpu/drm/radeon/radeon_combios.c

750

spll->pll_out_max = RBIOS32(pll_info + 0x22);

drivers/gpu/drm/radeon/radeon_combios.c

753

spll->pll_in_min = RBIOS32(pll_info + 0x48);

drivers/gpu/drm/radeon/radeon_combios.c

754

spll->pll_in_max = RBIOS32(pll_info + 0x4c);

drivers/gpu/drm/radeon/radeon_combios.c

762

mpll->reference_freq = RBIOS16(pll_info + 0x26);

drivers/gpu/drm/radeon/radeon_combios.c

763

mpll->reference_div = RBIOS16(pll_info + 0x28);

drivers/gpu/drm/radeon/radeon_combios.c

764

mpll->pll_out_min = RBIOS32(pll_info + 0x2a);

drivers/gpu/drm/radeon/radeon_combios.c

765

mpll->pll_out_max = RBIOS32(pll_info + 0x2e);

drivers/gpu/drm/radeon/radeon_combios.c

768

mpll->pll_in_min = RBIOS32(pll_info + 0x5a);

drivers/gpu/drm/radeon/radeon_combios.c

769

mpll->pll_in_max = RBIOS32(pll_info + 0x5e);

drivers/gpu/drm/radeon/radeon_combios.c

777

sclk = RBIOS16(pll_info + 0xa);

drivers/gpu/drm/radeon/radeon_combios.c

778

mclk = RBIOS16(pll_info + 0x8);

drivers/gpu/drm/radeon/radeon_combios.c

787

if (RBIOS32(pll_info + 0x16))

drivers/gpu/drm/radeon/radeon_combios.c

788

rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16);

drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c

142

unsigned long target, struct pll_info *pll,

drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c

275

struct pll_info pll = { .diff = (unsigned long)-1 };

drivers/video/fbdev/aty/atyfb.h

140

struct pll_info pll_limits;

drivers/video/fbdev/aty/radeonfb.h

342

struct pll_info pll;