arch/sh/kernel/cpu/sh2a/clock-sh7264.c

108

CLKDEV_CON_ID("pll_clk", &pll_clk),

arch/sh/kernel/cpu/sh2a/clock-sh7264.c

51

static struct clk pll_clk = {

arch/sh/kernel/cpu/sh2a/clock-sh7264.c

60

&pll_clk,

arch/sh/kernel/cpu/sh2a/clock-sh7264.c

78

SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)

arch/sh/kernel/cpu/sh2a/clock-sh7269.c

106

SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)

arch/sh/kernel/cpu/sh2a/clock-sh7269.c

142

CLKDEV_CON_ID("pll_clk", &pll_clk),

arch/sh/kernel/cpu/sh2a/clock-sh7269.c

47

static struct clk pll_clk = {

arch/sh/kernel/cpu/sh2a/clock-sh7269.c

64

.parent = &pll_clk,

arch/sh/kernel/cpu/sh2a/clock-sh7269.c

79

.parent = &pll_clk,

arch/sh/kernel/cpu/sh2a/clock-sh7269.c

86

&pll_clk,

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

106

SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

122

[DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

190

CLKDEV_CON_ID("pll_clk", &pll_clk),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

258

pll_clk.parent = &dll_clk;

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

260

pll_clk.parent = &extal_clk;

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

76

static struct clk pll_clk = {

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

85

&pll_clk,

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

109

SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

125

[DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

188

CLKDEV_CON_ID("pll_clk", &pll_clk),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

251

pll_clk.parent = &dll_clk;

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

253

pll_clk.parent = &extal_clk;

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

79

static struct clk pll_clk = {

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

88

&pll_clk,

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

109

SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

138

[DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

174

CLKDEV_CON_ID("pll_clk", &pll_clk),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

226

pll_clk.parent = &dll_clk;

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

228

pll_clk.parent = &extal_clk;

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

82

static struct clk pll_clk = {

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

91

&pll_clk,

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

112

SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

138

[DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

199

CLKDEV_CON_ID("pll_clk", &pll_clk),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

274

pll_clk.parent = &dll_clk;

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

276

pll_clk.parent = &extal_clk;

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

83

static struct clk pll_clk = {

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

92

&pll_clk,

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

102

.parent = &pll_clk,

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

119

&pll_clk,

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

151

SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

264

CLKDEV_CON_ID("pll_clk", &pll_clk),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

348

pll_clk.parent = &fll_clk;

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

350

pll_clk.parent = &extal_clk;

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

85

static struct clk pll_clk = {

arch/sh/kernel/cpu/sh4a/clock-sh7734.c

181

CLKDEV_CON_ID("pll_clk", &pll_clk),

arch/sh/kernel/cpu/sh4a/clock-sh7734.c

42

static struct clk pll_clk = {

arch/sh/kernel/cpu/sh4a/clock-sh7734.c

50

&pll_clk,

arch/sh/kernel/cpu/sh4a/clock-sh7734.c

70

SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)

arch/sh/kernel/cpu/sh4a/clock-sh7757.c

105

CLKDEV_CON_ID("pll_clk", &pll_clk),

arch/sh/kernel/cpu/sh4a/clock-sh7757.c

37

static struct clk pll_clk = {

arch/sh/kernel/cpu/sh4a/clock-sh7757.c

45

&pll_clk,

arch/sh/kernel/cpu/sh4a/clock-sh7757.c

63

SH_CLK_DIV4(&pll_clk, FRQCR, _bit, _mask, _flags)

arch/sh/kernel/cpu/sh4a/clock-sh7785.c

119

CLKDEV_CON_ID("pll_clk", &pll_clk),

arch/sh/kernel/cpu/sh4a/clock-sh7785.c

40

static struct clk pll_clk = {

arch/sh/kernel/cpu/sh4a/clock-sh7785.c

48

&pll_clk,

arch/sh/kernel/cpu/sh4a/clock-sh7785.c

67

SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)

arch/sh/kernel/cpu/sh4a/clock-sh7786.c

128

CLKDEV_CON_ID("pll_clk", &pll_clk),

arch/sh/kernel/cpu/sh4a/clock-sh7786.c

42

static struct clk pll_clk = {

arch/sh/kernel/cpu/sh4a/clock-sh7786.c

50

&pll_clk,

arch/sh/kernel/cpu/sh4a/clock-sh7786.c

68

SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)

arch/sh/kernel/cpu/sh4a/clock-shx3.c

103

CLKDEV_CON_ID("pll_clk", &pll_clk),

arch/sh/kernel/cpu/sh4a/clock-shx3.c

36

static struct clk pll_clk = {

arch/sh/kernel/cpu/sh4a/clock-shx3.c

44

&pll_clk,

arch/sh/kernel/cpu/sh4a/clock-shx3.c

62

SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)

drivers/accel/habanalabs/gaudi/gaudi.c

909

u32 nr = 0, nf = 0, od = 0, div_fctr = 0, pll_clk, div_sel;

drivers/accel/habanalabs/gaudi/gaudi.c

943

pll_clk = PLL_REF_CLK * (nf + 1) /

drivers/accel/habanalabs/gaudi/gaudi.c

946

freq = pll_clk;

drivers/accel/habanalabs/gaudi/gaudi.c

948

freq = pll_clk / (div_fctr + 1);

drivers/accel/habanalabs/goya/goya.c

747

u32 nr = 0, nf = 0, od = 0, div_fctr = 0, pll_clk, div_sel;

drivers/accel/habanalabs/goya/goya.c

779

pll_clk = PLL_REF_CLK * (nf + 1) /

drivers/accel/habanalabs/goya/goya.c

782

freq = pll_clk;

drivers/accel/habanalabs/goya/goya.c

784

freq = pll_clk / (div_fctr + 1);

drivers/clk/axs10x/i2s_pll_clock.c

170

struct i2s_pll_clk *pll_clk;

drivers/clk/axs10x/i2s_pll_clock.c

173

pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL);

drivers/clk/axs10x/i2s_pll_clock.c

174

if (!pll_clk)

drivers/clk/axs10x/i2s_pll_clock.c

177

pll_clk->base = devm_platform_ioremap_resource(pdev, 0);

drivers/clk/axs10x/i2s_pll_clock.c

178

if (IS_ERR(pll_clk->base))

drivers/clk/axs10x/i2s_pll_clock.c

179

return PTR_ERR(pll_clk->base);

drivers/clk/axs10x/i2s_pll_clock.c

188

pll_clk->hw.init = &init;

drivers/clk/axs10x/i2s_pll_clock.c

189

pll_clk->dev = dev;

drivers/clk/axs10x/i2s_pll_clock.c

191

clk = devm_clk_register(dev, &pll_clk->hw);

drivers/clk/axs10x/pll_clock.c

221

struct axs10x_pll_clk *pll_clk;

drivers/clk/axs10x/pll_clock.c

225

pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL);

drivers/clk/axs10x/pll_clock.c

226

if (!pll_clk)

drivers/clk/axs10x/pll_clock.c

229

pll_clk->base = devm_platform_ioremap_resource(pdev, 0);

drivers/clk/axs10x/pll_clock.c

230

if (IS_ERR(pll_clk->base))

drivers/clk/axs10x/pll_clock.c

231

return PTR_ERR(pll_clk->base);

drivers/clk/axs10x/pll_clock.c

233

pll_clk->lock = devm_platform_ioremap_resource(pdev, 1);

drivers/clk/axs10x/pll_clock.c

234

if (IS_ERR(pll_clk->lock))

drivers/clk/axs10x/pll_clock.c

235

return PTR_ERR(pll_clk->lock);

drivers/clk/axs10x/pll_clock.c

242

pll_clk->hw.init = &init;

drivers/clk/axs10x/pll_clock.c

243

pll_clk->dev = dev;

drivers/clk/axs10x/pll_clock.c

244

pll_clk->pll_cfg = of_device_get_match_data(dev);

drivers/clk/axs10x/pll_clock.c

246

if (!pll_clk->pll_cfg) {

drivers/clk/axs10x/pll_clock.c

251

ret = devm_clk_hw_register(dev, &pll_clk->hw);

drivers/clk/axs10x/pll_clock.c

258

&pll_clk->hw);

drivers/clk/axs10x/pll_clock.c

264

struct axs10x_pll_clk *pll_clk;

drivers/clk/axs10x/pll_clock.c

268

pll_clk = kzalloc_obj(*pll_clk);

drivers/clk/axs10x/pll_clock.c

269

if (!pll_clk)

drivers/clk/axs10x/pll_clock.c

272

pll_clk->base = of_iomap(node, 0);

drivers/clk/axs10x/pll_clock.c

273

if (!pll_clk->base) {

drivers/clk/axs10x/pll_clock.c

278

pll_clk->lock = of_iomap(node, 1);

drivers/clk/axs10x/pll_clock.c

279

if (!pll_clk->lock) {

drivers/clk/axs10x/pll_clock.c

289

pll_clk->hw.init = &init;

drivers/clk/axs10x/pll_clock.c

290

pll_clk->pll_cfg = arc_pll_cfg;

drivers/clk/axs10x/pll_clock.c

292

ret = clk_hw_register(NULL, &pll_clk->hw);

drivers/clk/axs10x/pll_clock.c

298

ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll_clk->hw);

drivers/clk/axs10x/pll_clock.c

307

clk_hw_unregister(&pll_clk->hw);

drivers/clk/axs10x/pll_clock.c

309

iounmap(pll_clk->lock);

drivers/clk/axs10x/pll_clock.c

311

iounmap(pll_clk->base);

drivers/clk/axs10x/pll_clock.c

313

kfree(pll_clk);

drivers/clk/clk-asm9260.c

260

const char *pll_clk = "pll";

drivers/clk/clk-asm9260.c

278

pll_hw = clk_hw_register_fixed_rate_parent_accuracy(NULL, pll_clk, &pll_parent_data,

drivers/clk/clk-bm1880.c

509

static struct clk_hw *bm1880_clk_register_pll(struct bm1880_pll_hw_clock *pll_clk,

drivers/clk/clk-bm1880.c

515

pll_clk->base = sys_base;

drivers/clk/clk-bm1880.c

516

hw = &pll_clk->hw;

drivers/clk/clk-hsdk-pll.c

310

struct hsdk_pll_clk *pll_clk;

drivers/clk/clk-hsdk-pll.c

314

pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL);

drivers/clk/clk-hsdk-pll.c

315

if (!pll_clk)

drivers/clk/clk-hsdk-pll.c

318

pll_clk->regs = devm_platform_ioremap_resource(pdev, 0);

drivers/clk/clk-hsdk-pll.c

319

if (IS_ERR(pll_clk->regs))

drivers/clk/clk-hsdk-pll.c

320

return PTR_ERR(pll_clk->regs);

drivers/clk/clk-hsdk-pll.c

333

pll_clk->hw.init = &init;

drivers/clk/clk-hsdk-pll.c

334

pll_clk->dev = dev;

drivers/clk/clk-hsdk-pll.c

335

pll_clk->pll_devdata = of_device_get_match_data(dev);

drivers/clk/clk-hsdk-pll.c

337

if (!pll_clk->pll_devdata) {

drivers/clk/clk-hsdk-pll.c

342

ret = devm_clk_hw_register(dev, &pll_clk->hw);

drivers/clk/clk-hsdk-pll.c

349

&pll_clk->hw);

drivers/clk/clk-hsdk-pll.c

357

struct hsdk_pll_clk *pll_clk;

drivers/clk/clk-hsdk-pll.c

360

pll_clk = kzalloc_obj(*pll_clk);

drivers/clk/clk-hsdk-pll.c

361

if (!pll_clk)

drivers/clk/clk-hsdk-pll.c

364

pll_clk->regs = of_iomap(node, 0);

drivers/clk/clk-hsdk-pll.c

365

if (!pll_clk->regs) {

drivers/clk/clk-hsdk-pll.c

370

pll_clk->spec_regs = of_iomap(node, 1);

drivers/clk/clk-hsdk-pll.c

371

if (!pll_clk->spec_regs) {

drivers/clk/clk-hsdk-pll.c

387

pll_clk->hw.init = &init;

drivers/clk/clk-hsdk-pll.c

388

pll_clk->pll_devdata = &core_pll_devdata;

drivers/clk/clk-hsdk-pll.c

390

ret = clk_hw_register(NULL, &pll_clk->hw);

drivers/clk/clk-hsdk-pll.c

396

ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll_clk->hw);

drivers/clk/clk-hsdk-pll.c

405

iounmap(pll_clk->spec_regs);

drivers/clk/clk-hsdk-pll.c

407

iounmap(pll_clk->regs);

drivers/clk/clk-hsdk-pll.c

409

kfree(pll_clk);

drivers/clk/clk-moxart.c

59

struct clk *pll_clk;

drivers/clk/clk-moxart.c

81

pll_clk = of_clk_get(node, 0);

drivers/clk/clk-moxart.c

82

if (IS_ERR(pll_clk)) {

drivers/clk/clk-npcm8xx.c

309

struct npcm8xx_clk_pll_data *pll_clk = &npcm8xx_pll_clks[i];

drivers/clk/clk-npcm8xx.c

311

hw = npcm8xx_clk_register_pll(dev, clk_base + pll_clk->reg,

drivers/clk/clk-npcm8xx.c

312

pll_clk->name, &pll_clk->parent,

drivers/clk/clk-npcm8xx.c

313

pll_clk->flags);

drivers/clk/clk-npcm8xx.c

316

pll_clk->hw = *hw;

drivers/clk/clk-vt8500.c

688

struct clk_pll *pll_clk;

drivers/clk/clk-vt8500.c

701

pll_clk = kzalloc_obj(*pll_clk);

drivers/clk/clk-vt8500.c

702

if (WARN_ON(!pll_clk))

drivers/clk/clk-vt8500.c

705

pll_clk->reg = pmc_base + reg;

drivers/clk/clk-vt8500.c

706

pll_clk->lock = &_lock;

drivers/clk/clk-vt8500.c

707

pll_clk->type = pll_type;

drivers/clk/clk-vt8500.c

718

pll_clk->hw.init = &init;

drivers/clk/clk-vt8500.c

720

hw = &pll_clk->hw;

drivers/clk/clk-vt8500.c

721

rc = clk_hw_register(NULL, &pll_clk->hw);

drivers/clk/clk-vt8500.c

723

kfree(pll_clk);

drivers/clk/imx/clk-fracn-gppll.c

361

const struct imx_fracn_gppll_clk *pll_clk,

drivers/clk/imx/clk-fracn-gppll.c

374

init.flags = pll_clk->flags;

drivers/clk/imx/clk-fracn-gppll.c

381

pll->rate_table = pll_clk->rate_table;

drivers/clk/imx/clk-fracn-gppll.c

382

pll->rate_count = pll_clk->rate_count;

drivers/clk/imx/clk-fracn-gppll.c

398

const struct imx_fracn_gppll_clk *pll_clk)

drivers/clk/imx/clk-fracn-gppll.c

400

return _imx_clk_fracn_gppll(name, parent_name, base, pll_clk, CLK_FRACN_GPPLL_FRACN);

drivers/clk/imx/clk-fracn-gppll.c

406

const struct imx_fracn_gppll_clk *pll_clk)

drivers/clk/imx/clk-fracn-gppll.c

408

return _imx_clk_fracn_gppll(name, parent_name, base, pll_clk, CLK_FRACN_GPPLL_INTEGER);

drivers/clk/imx/clk-pll14xx.c

499

const struct imx_pll14xx_clk *pll_clk)

drivers/clk/imx/clk-pll14xx.c

512

init.flags = pll_clk->flags;

drivers/clk/imx/clk-pll14xx.c

516

switch (pll_clk->type) {

drivers/clk/imx/clk-pll14xx.c

518

if (!pll_clk->rate_table)

drivers/clk/imx/clk-pll14xx.c

534

pll->type = pll_clk->type;

drivers/clk/imx/clk-pll14xx.c

535

pll->rate_table = pll_clk->rate_table;

drivers/clk/imx/clk-pll14xx.c

536

pll->rate_count = pll_clk->rate_count;

drivers/clk/imx/clk.h

224

#define imx_clk_hw_pll14xx(name, parent_name, base, pll_clk) \

drivers/clk/imx/clk.h

225

imx_dev_clk_hw_pll14xx(NULL, name, parent_name, base, pll_clk)

drivers/clk/imx/clk.h

229

const struct imx_pll14xx_clk *pll_clk);

drivers/clk/imx/clk.h

96

const struct imx_fracn_gppll_clk *pll_clk);

drivers/clk/imx/clk.h

99

const struct imx_fracn_gppll_clk *pll_clk);

drivers/clk/renesas/rcar-gen3-cpg.c

122

struct cpg_pll_clk *pll_clk;

drivers/clk/renesas/rcar-gen3-cpg.c

126

pll_clk = kzalloc_obj(*pll_clk);

drivers/clk/renesas/rcar-gen3-cpg.c

127

if (!pll_clk)

drivers/clk/renesas/rcar-gen3-cpg.c

135

pll_clk->hw.init = &init;

drivers/clk/renesas/rcar-gen3-cpg.c

136

pll_clk->pllcr_reg = base + offset;

drivers/clk/renesas/rcar-gen3-cpg.c

137

pll_clk->pllecr_reg = base + CPG_PLLECR;

drivers/clk/renesas/rcar-gen3-cpg.c

138

pll_clk->fixed_mult = mult; /* PLL refclk x (setting + 1) x mult */

drivers/clk/renesas/rcar-gen3-cpg.c

139

pll_clk->pllecr_pllst_mask = CPG_PLLECR_PLLST(index);

drivers/clk/renesas/rcar-gen3-cpg.c

141

clk = clk_register(NULL, &pll_clk->hw);

drivers/clk/renesas/rcar-gen3-cpg.c

143

kfree(pll_clk);

drivers/clk/renesas/rcar-gen3-cpg.c

55

struct cpg_pll_clk *pll_clk = to_pll_clk(hw);

drivers/clk/renesas/rcar-gen3-cpg.c

58

mult = FIELD_GET(CPG_PLLnCR_STC_MASK, readl(pll_clk->pllcr_reg)) + 1;

drivers/clk/renesas/rcar-gen3-cpg.c

60

return parent_rate * mult * pll_clk->fixed_mult;

drivers/clk/renesas/rcar-gen3-cpg.c

66

struct cpg_pll_clk *pll_clk = to_pll_clk(hw);

drivers/clk/renesas/rcar-gen3-cpg.c

70

prate = req->best_parent_rate * pll_clk->fixed_mult;

drivers/clk/renesas/rcar-gen3-cpg.c

86

struct cpg_pll_clk *pll_clk = to_pll_clk(hw);

drivers/clk/renesas/rcar-gen3-cpg.c

90

mult = DIV_ROUND_CLOSEST_ULL(rate, parent_rate * pll_clk->fixed_mult);

drivers/clk/renesas/rcar-gen3-cpg.c

93

val = readl(pll_clk->pllcr_reg);

drivers/clk/renesas/rcar-gen3-cpg.c

96

writel(val, pll_clk->pllcr_reg);

drivers/clk/renesas/rcar-gen3-cpg.c

99

if (readl(pll_clk->pllecr_reg) & pll_clk->pllecr_pllst_mask)

drivers/clk/renesas/rcar-gen4-cpg.c

103

struct cpg_pll_clk *pll_clk = to_pll_clk(hw);

drivers/clk/renesas/rcar-gen4-cpg.c

105

u32 cr0 = readl(pll_clk->pllcr0_reg);

drivers/clk/renesas/rcar-gen4-cpg.c

137

struct cpg_pll_clk *pll_clk = to_pll_clk(hw);

drivers/clk/renesas/rcar-gen4-cpg.c

139

u32 cr0 = readl(pll_clk->pllcr0_reg);

drivers/clk/renesas/rcar-gen4-cpg.c

158

if (readl(pll_clk->pllcr0_reg) & CPG_PLLxCR0_KICK)

drivers/clk/renesas/rcar-gen4-cpg.c

161

cpg_reg_modify(pll_clk->pllcr0_reg, CPG_PLLxCR0_NI8,

drivers/clk/renesas/rcar-gen4-cpg.c

164

cpg_reg_modify(pll_clk->pllcr1_reg, CPG_PLLxCR1_NF25,

drivers/clk/renesas/rcar-gen4-cpg.c

171

cpg_reg_modify(pll_clk->pllcr0_reg, 0, CPG_PLLxCR0_KICK);

drivers/clk/renesas/rcar-gen4-cpg.c

182

return readl_poll_timeout(pll_clk->pllecr_reg, val,

drivers/clk/renesas/rcar-gen4-cpg.c

183

val & pll_clk->pllecr_pllst_mask, 0, 1000);

drivers/clk/renesas/rcar-gen4-cpg.c

199

struct cpg_pll_clk *pll_clk = to_pll_clk(hw);

drivers/clk/renesas/rcar-gen4-cpg.c

200

u32 cr0 = readl(pll_clk->pllcr0_reg);

drivers/clk/renesas/rcar-gen4-cpg.c

207

nf = FIELD_GET(CPG_PLLxCR1_NF24, readl(pll_clk->pllcr1_reg));

drivers/clk/renesas/rcar-gen4-cpg.c

234

struct cpg_pll_clk *pll_clk;

drivers/clk/renesas/rcar-gen4-cpg.c

237

pll_clk = kzalloc_obj(*pll_clk);

drivers/clk/renesas/rcar-gen4-cpg.c

238

if (!pll_clk)

drivers/clk/renesas/rcar-gen4-cpg.c

246

pll_clk->hw.init = &init;

drivers/clk/renesas/rcar-gen4-cpg.c

247

pll_clk->pllcr0_reg = base + pll_cr_offsets[index - 1].cr0;

drivers/clk/renesas/rcar-gen4-cpg.c

248

pll_clk->pllcr1_reg = base + pll_cr_offsets[index - 1].cr1;

drivers/clk/renesas/rcar-gen4-cpg.c

249

pll_clk->pllecr_reg = base + CPG_PLLECR;

drivers/clk/renesas/rcar-gen4-cpg.c

250

pll_clk->pllecr_pllst_mask = CPG_PLLECR_PLLST(index);

drivers/clk/renesas/rcar-gen4-cpg.c

252

clk = clk_register(NULL, &pll_clk->hw);

drivers/clk/renesas/rcar-gen4-cpg.c

254

kfree(pll_clk);

drivers/clk/renesas/rcar-gen4-cpg.c

85

struct cpg_pll_clk *pll_clk = to_pll_clk(hw);

drivers/clk/renesas/rcar-gen4-cpg.c

86

u32 cr0 = readl(pll_clk->pllcr0_reg);

drivers/clk/renesas/rcar-gen4-cpg.c

93

nf = FIELD_GET(CPG_PLLxCR1_NF25, readl(pll_clk->pllcr1_reg));

drivers/clk/renesas/rzg2l-cpg.c

1076

#define to_pll(_hw) container_of(_hw, struct pll_clk, hw)

drivers/clk/renesas/rzg2l-cpg.c

1081

struct pll_clk *pll_clk = to_pll(hw);

drivers/clk/renesas/rzg2l-cpg.c

1082

struct rzg2l_cpg_priv *priv = pll_clk->priv;

drivers/clk/renesas/rzg2l-cpg.c

1086

if (pll_clk->type != CLK_TYPE_SAM_PLL)

drivers/clk/renesas/rzg2l-cpg.c

1089

val1 = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf));

drivers/clk/renesas/rzg2l-cpg.c

1090

val2 = readl(priv->base + GET_REG_SAMPLL_CLK2(pll_clk->conf));

drivers/clk/renesas/rzg2l-cpg.c

1105

struct pll_clk *pll_clk = to_pll(hw);

drivers/clk/renesas/rzg2l-cpg.c

1106

struct rzg2l_cpg_priv *priv = pll_clk->priv;

drivers/clk/renesas/rzg2l-cpg.c

1110

if (pll_clk->type != CLK_TYPE_G3S_PLL)

drivers/clk/renesas/rzg2l-cpg.c

1113

setting = GET_REG_SAMPLL_SETTING(pll_clk->conf);

drivers/clk/renesas/rzg2l-cpg.c

1117

return pll_clk->default_rate;

drivers/clk/renesas/rzg2l-cpg.c

1120

val = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf));

drivers/clk/renesas/rzg2l-cpg.c

1149

struct pll_clk *pll_clk;

drivers/clk/renesas/rzg2l-cpg.c

1156

pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL);

drivers/clk/renesas/rzg2l-cpg.c

1157

if (!pll_clk)

drivers/clk/renesas/rzg2l-cpg.c

1167

pll_clk->hw.init = &init;

drivers/clk/renesas/rzg2l-cpg.c

1168

pll_clk->conf = core->conf;

drivers/clk/renesas/rzg2l-cpg.c

1169

pll_clk->base = priv->base;

drivers/clk/renesas/rzg2l-cpg.c

1170

pll_clk->priv = priv;

drivers/clk/renesas/rzg2l-cpg.c

1171

pll_clk->type = core->type;

drivers/clk/renesas/rzg2l-cpg.c

1172

pll_clk->default_rate = core->default_rate;

drivers/clk/renesas/rzg2l-cpg.c

1174

ret = devm_clk_hw_register(dev, &pll_clk->hw);

drivers/clk/renesas/rzg2l-cpg.c

1178

return pll_clk->hw.clk;

drivers/clk/renesas/rzv2h-cpg.c

138

#define to_pll(_hw) container_of(_hw, struct pll_clk, hw)

drivers/clk/renesas/rzv2h-cpg.c

441

struct pll_clk *pll_clk = to_pll(clk_hw_get_parent(hw));

drivers/clk/renesas/rzv2h-cpg.c

450

dsi_info = &priv->pll_dsi_info[pll_clk->pll.instance];

drivers/clk/renesas/rzv2h-cpg.c

483

struct pll_clk *pll_clk = to_pll(clk_hw_get_parent(hw));

drivers/clk/renesas/rzv2h-cpg.c

492

dsi_info = &priv->pll_dsi_info[pll_clk->pll.instance];

drivers/clk/renesas/rzv2h-cpg.c

564

struct pll_clk *pll_clk = to_pll(hw);

drivers/clk/renesas/rzv2h-cpg.c

565

struct rzv2h_cpg_priv *priv = pll_clk->priv;

drivers/clk/renesas/rzv2h-cpg.c

569

dsi_info = &priv->pll_dsi_info[pll_clk->pll.instance];

drivers/clk/renesas/rzv2h-cpg.c

590

static int rzv2h_cpg_pll_set_rate(struct pll_clk *pll_clk,

drivers/clk/renesas/rzv2h-cpg.c

594

struct rzv2h_cpg_priv *priv = pll_clk->priv;

drivers/clk/renesas/rzv2h-cpg.c

595

u16 offset = pll_clk->pll.offset;

drivers/clk/renesas/rzv2h-cpg.c

643

struct pll_clk *pll_clk = to_pll(hw);

drivers/clk/renesas/rzv2h-cpg.c

645

struct rzv2h_cpg_priv *priv = pll_clk->priv;

drivers/clk/renesas/rzv2h-cpg.c

647

dsi_info = &priv->pll_dsi_info[pll_clk->pll.instance];

drivers/clk/renesas/rzv2h-cpg.c

649

return rzv2h_cpg_pll_set_rate(pll_clk, &dsi_info->pll_dsi_parameters.pll, true);

drivers/clk/renesas/rzv2h-cpg.c

654

struct pll_clk *pll_clk = to_pll(hw);

drivers/clk/renesas/rzv2h-cpg.c

655

struct rzv2h_cpg_priv *priv = pll_clk->priv;

drivers/clk/renesas/rzv2h-cpg.c

656

u32 val = readl(priv->base + CPG_PLL_MON(pll_clk->pll.offset));

drivers/clk/renesas/rzv2h-cpg.c

665

struct pll_clk *pll_clk = to_pll(hw);

drivers/clk/renesas/rzv2h-cpg.c

666

struct rzv2h_cpg_priv *priv = pll_clk->priv;

drivers/clk/renesas/rzv2h-cpg.c

667

struct pll pll = pll_clk->pll;

drivers/clk/renesas/rzv2h-cpg.c

703

struct pll_clk *pll_clk = to_pll(hw);

drivers/clk/renesas/rzv2h-cpg.c

704

struct rzv2h_cpg_priv *priv = pll_clk->priv;

drivers/clk/renesas/rzv2h-cpg.c

705

struct pll pll = pll_clk->pll;

drivers/clk/renesas/rzv2h-cpg.c

743

struct pll_clk *pll_clk;

drivers/clk/renesas/rzv2h-cpg.c

750

pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL);

drivers/clk/renesas/rzv2h-cpg.c

751

if (!pll_clk)

drivers/clk/renesas/rzv2h-cpg.c

765

pll_clk->hw.init = &init;

drivers/clk/renesas/rzv2h-cpg.c

766

pll_clk->pll = core->cfg.pll;

drivers/clk/renesas/rzv2h-cpg.c

767

pll_clk->priv = priv;

drivers/clk/renesas/rzv2h-cpg.c

769

ret = devm_clk_hw_register(dev, &pll_clk->hw);

drivers/clk/renesas/rzv2h-cpg.c

773

return pll_clk->hw.clk;

drivers/clk/rockchip/clk-pll.c

1067

struct clk *pll_clk, *mux_clk;

drivers/clk/rockchip/clk-pll.c

1190

pll_clk = clk_register(NULL, &pll->hw);

drivers/clk/rockchip/clk-pll.c

1191

if (IS_ERR(pll_clk)) {

drivers/clk/rockchip/clk-pll.c

1193

__func__, name, PTR_ERR(pll_clk));

drivers/clk/rockchip/clk-pll.c

1202

mux_clk = pll_clk;

drivers/clk/samsung/clk-pll.c

1432

const struct samsung_pll_clock *pll_clk)

drivers/clk/samsung/clk-pll.c

1441

__func__, pll_clk->name);

drivers/clk/samsung/clk-pll.c

1445

init.name = pll_clk->name;

drivers/clk/samsung/clk-pll.c

1446

init.flags = pll_clk->flags;

drivers/clk/samsung/clk-pll.c

1447

init.parent_names = &pll_clk->parent_name;

drivers/clk/samsung/clk-pll.c

1450

if (pll_clk->rate_table) {

drivers/clk/samsung/clk-pll.c

1452

for (len = 0; pll_clk->rate_table[len].rate != 0; )

drivers/clk/samsung/clk-pll.c

1456

pll->rate_table = kmemdup_array(pll_clk->rate_table,

drivers/clk/samsung/clk-pll.c

1462

__func__, pll_clk->name);

drivers/clk/samsung/clk-pll.c

1465

switch (pll_clk->type) {

drivers/clk/samsung/clk-pll.c

1583

__func__, pll_clk->name);

drivers/clk/samsung/clk-pll.c

1587

pll->type = pll_clk->type;

drivers/clk/samsung/clk-pll.c

1588

pll->lock_reg = ctx->reg_base + pll_clk->lock_offset;

drivers/clk/samsung/clk-pll.c

1589

pll->con_reg = ctx->reg_base + pll_clk->con_offset;

drivers/clk/samsung/clk-pll.c

1594

__func__, pll_clk->name, ret);

drivers/clk/samsung/clk-pll.c

1600

samsung_clk_add_lookup(ctx, &pll->hw, pll_clk->id);

drivers/clk/socfpga/clk-pll-a10.c

102

pll_clk->hw.hw.init = &init;

drivers/clk/socfpga/clk-pll-a10.c

104

pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;

drivers/clk/socfpga/clk-pll-a10.c

105

hw_clk = &pll_clk->hw.hw;

drivers/clk/socfpga/clk-pll-a10.c

125

kfree(pll_clk);

drivers/clk/socfpga/clk-pll-a10.c

71

struct socfpga_pll *pll_clk;

drivers/clk/socfpga/clk-pll-a10.c

81

pll_clk = kzalloc_obj(*pll_clk);

drivers/clk/socfpga/clk-pll-a10.c

82

if (WARN_ON(!pll_clk))

drivers/clk/socfpga/clk-pll-a10.c

89

pll_clk->hw.reg = clk_mgr_a10_base_addr + reg;

drivers/clk/socfpga/clk-pll-s10.c

194

struct socfpga_pll *pll_clk;

drivers/clk/socfpga/clk-pll-s10.c

199

pll_clk = kzalloc_obj(*pll_clk);

drivers/clk/socfpga/clk-pll-s10.c

200

if (WARN_ON(!pll_clk))

drivers/clk/socfpga/clk-pll-s10.c

203

pll_clk->hw.reg = reg + clks->offset;

drivers/clk/socfpga/clk-pll-s10.c

216

pll_clk->hw.hw.init = &init;

drivers/clk/socfpga/clk-pll-s10.c

218

pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;

drivers/clk/socfpga/clk-pll-s10.c

220

hw_clk = &pll_clk->hw.hw;

drivers/clk/socfpga/clk-pll-s10.c

224

kfree(pll_clk);

drivers/clk/socfpga/clk-pll-s10.c

234

struct socfpga_pll *pll_clk;

drivers/clk/socfpga/clk-pll-s10.c

239

pll_clk = kzalloc_obj(*pll_clk);

drivers/clk/socfpga/clk-pll-s10.c

240

if (WARN_ON(!pll_clk))

drivers/clk/socfpga/clk-pll-s10.c

243

pll_clk->hw.reg = reg + clks->offset;

drivers/clk/socfpga/clk-pll-s10.c

256

pll_clk->hw.hw.init = &init;

drivers/clk/socfpga/clk-pll-s10.c

258

pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;

drivers/clk/socfpga/clk-pll-s10.c

259

hw_clk = &pll_clk->hw.hw;

drivers/clk/socfpga/clk-pll-s10.c

263

kfree(pll_clk);

drivers/clk/socfpga/clk-pll-s10.c

273

struct socfpga_pll *pll_clk;

drivers/clk/socfpga/clk-pll-s10.c

278

pll_clk = kzalloc_obj(*pll_clk);

drivers/clk/socfpga/clk-pll-s10.c

279

if (WARN_ON(!pll_clk))

drivers/clk/socfpga/clk-pll-s10.c

282

pll_clk->hw.reg = reg + clks->offset;

drivers/clk/socfpga/clk-pll-s10.c

295

pll_clk->hw.hw.init = &init;

drivers/clk/socfpga/clk-pll-s10.c

297

pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;

drivers/clk/socfpga/clk-pll-s10.c

298

hw_clk = &pll_clk->hw.hw;

drivers/clk/socfpga/clk-pll-s10.c

302

kfree(pll_clk);

drivers/clk/socfpga/clk-pll-s10.c

312

struct socfpga_pll *pll_clk;

drivers/clk/socfpga/clk-pll-s10.c

317

pll_clk = kzalloc_obj(*pll_clk);

drivers/clk/socfpga/clk-pll-s10.c

318

if (WARN_ON(!pll_clk))

drivers/clk/socfpga/clk-pll-s10.c

321

pll_clk->hw.reg = reg + clks->offset;

drivers/clk/socfpga/clk-pll-s10.c

332

pll_clk->hw.hw.init = &init;

drivers/clk/socfpga/clk-pll-s10.c

333

pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;

drivers/clk/socfpga/clk-pll-s10.c

334

hw_clk = &pll_clk->hw.hw;

drivers/clk/socfpga/clk-pll-s10.c

338

kfree(pll_clk);

drivers/clk/socfpga/clk-pll.c

105

pll_clk->hw.hw.init = &init;

drivers/clk/socfpga/clk-pll.c

107

pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;

drivers/clk/socfpga/clk-pll.c

109

hw_clk = &pll_clk->hw.hw;

drivers/clk/socfpga/clk-pll.c

129

kfree(pll_clk);

drivers/clk/socfpga/clk-pll.c

78

struct socfpga_pll *pll_clk;

drivers/clk/socfpga/clk-pll.c

87

pll_clk = kzalloc_obj(*pll_clk);

drivers/clk/socfpga/clk-pll.c

88

if (WARN_ON(!pll_clk))

drivers/clk/socfpga/clk-pll.c

95

pll_clk->hw.reg = clk_mgr_base_addr + reg;

drivers/clk/spear/clk-vco-pll.c

281

spinlock_t *lock, struct clk **pll_clk,

drivers/clk/spear/clk-vco-pll.c

348

if (pll_clk)

drivers/clk/spear/clk-vco-pll.c

349

*pll_clk = tpll_clk;

drivers/clk/spear/clk.h

124

spinlock_t *lock, struct clk **pll_clk,

drivers/clk/ti/fapll.c

496

struct clk *pll_clk)

drivers/clk/ti/fapll.c

521

synth->clk_pll = pll_clk;

drivers/clk/ti/fapll.c

543

struct clk *pll_clk;

drivers/clk/ti/fapll.c

599

pll_clk = clk_register(NULL, &fd->hw);

drivers/clk/ti/fapll.c

600

if (IS_ERR(pll_clk))

drivers/clk/ti/fapll.c

603

fd->outputs.clks[0] = pll_clk;

drivers/clk/ti/fapll.c

642

output_name, name, pll_clk);

drivers/gpu/drm/bridge/samsung-dsim.c

2076

dsi->pll_clk = devm_clk_get(dev, "sclk_mipi");

drivers/gpu/drm/bridge/samsung-dsim.c

2077

if (IS_ERR(dsi->pll_clk))

drivers/gpu/drm/bridge/samsung-dsim.c

2078

return PTR_ERR(dsi->pll_clk);

drivers/gpu/drm/bridge/samsung-dsim.c

796

if (dsi->pll_clk) {

drivers/gpu/drm/bridge/samsung-dsim.c

802

fin = clk_get_rate(clk_get_parent(dsi->pll_clk));

drivers/gpu/drm/bridge/samsung-dsim.c

805

clk_set_rate(dsi->pll_clk, fin);

drivers/gpu/drm/bridge/samsung-dsim.c

807

fin = clk_get_rate(dsi->pll_clk);

drivers/gpu/drm/bridge/tc358768.c

313

static u32 tc358768_pll_to_pclk(struct tc358768_priv *priv, u32 pll_clk)

drivers/gpu/drm/bridge/tc358768.c

315

return (u32)div_u64((u64)pll_clk * priv->dsi_lanes, priv->dsi_bpp);

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

239

struct clk *pll_clk;

drivers/pinctrl/qcom/pinctrl-qcs8300.c

1116

[74] = PINGROUP(74, pll_clk, qdss_gpio, atest_usb2, _, _, _, _, _, _, _, _),

drivers/pinctrl/qcom/pinctrl-qcs8300.c

991

MSM_PIN_FUNCTION(pll_clk),

drivers/pinctrl/qcom/pinctrl-qdu1000.c

1157

[98] = PINGROUP(98, pll_clk, _, _, _, _, _, _, _, _),

drivers/pinctrl/qcom/pinctrl-qdu1000.c

937

MSM_PIN_FUNCTION(pll_clk),

drivers/pinctrl/qcom/pinctrl-sa8775p.c

1280

MSM_PIN_FUNCTION(pll_clk),

drivers/pinctrl/qcom/pinctrl-sa8775p.c

1427

[87] = PINGROUP(87, qup2_se2, pll_clk, atest_usb2, ddr_pxi3, _, _, _, _, _),

drivers/pinctrl/qcom/pinctrl-sar2130p.c

1198

MSM_PIN_FUNCTION(pll_clk),

drivers/pinctrl/qcom/pinctrl-sar2130p.c

1331

[54] = PINGROUP(54, pll_clk, _, _, _, _, _, _, _, _),

drivers/pinctrl/qcom/pinctrl-sc7280.c

1206

MSM_PIN_FUNCTION(pll_clk),

drivers/pinctrl/qcom/pinctrl-sc7280.c

1411

[140] = PINGROUP(140, usb_phy, pll_clk, _, _, _, _, _, _, _),

drivers/pinctrl/qcom/pinctrl-sc8280xp.c

1577

MSM_PIN_FUNCTION(pll_clk),

drivers/pinctrl/qcom/pinctrl-sc8280xp.c

1724

[84] = PINGROUP(84, qup21, qup22, pll_bist, pll_clk, _, _, _),

drivers/pinctrl/qcom/pinctrl-sc8280xp.c

1726

[86] = PINGROUP(86, qup22, _, pll_clk, _, _, _, _),

drivers/pinctrl/qcom/pinctrl-sm6375.c

1230

MSM_PIN_FUNCTION(pll_clk),

drivers/pinctrl/qcom/pinctrl-sm6375.c

1410

[98] = PINGROUP(98, _, atest_char2, _, _, prng_rosc1, pll_clk, _, _, _),

drivers/pinctrl/qcom/pinctrl-sm8250.c

1063

MSM_PIN_FUNCTION(pll_clk),

drivers/pinctrl/qcom/pinctrl-sm8250.c

1199

[65] = PINGROUP(65, SOUTH, usb_phy, pll_clk, _, _, _, _, _, _, _),

drivers/pinctrl/qcom/pinctrl-sm8350.c

1310

MSM_PIN_FUNCTION(pll_clk),

drivers/pinctrl/qcom/pinctrl-sm8350.c

1470

[81] = PINGROUP(81, usb_phy, pll_bist, pll_clk, atest_usb, _, _, _, _, _),

drivers/pinctrl/qcom/pinctrl-sm8450.c

1331

MSM_PIN_FUNCTION(pll_clk),

drivers/pinctrl/qcom/pinctrl-sm8450.c

1523

[107] = PINGROUP(107, cam_mclk, qdss_gpio, pll_clk, _, _, _, _, _, _),

drivers/pinctrl/qcom/pinctrl-x1e80100.c

1485

MSM_PIN_FUNCTION(pll_clk),

drivers/pinctrl/qcom/pinctrl-x1e80100.c

1605

[35] = PINGROUP(35, qup1_se0, qup1_se3, pll_clk, atest_usb, _, _, _, _, _),

drivers/spi/spi-bcm63xx-hsspi.c

136

struct clk *pll_clk;

drivers/spi/spi-bcm63xx-hsspi.c

748

struct clk *clk, *pll_clk = NULL;

drivers/spi/spi-bcm63xx-hsspi.c

782

pll_clk = devm_clk_get(dev, "pll");

drivers/spi/spi-bcm63xx-hsspi.c

784

if (IS_ERR(pll_clk)) {

drivers/spi/spi-bcm63xx-hsspi.c

785

ret = PTR_ERR(pll_clk);

drivers/spi/spi-bcm63xx-hsspi.c

789

ret = clk_prepare_enable(pll_clk);

drivers/spi/spi-bcm63xx-hsspi.c

793

rate = clk_get_rate(pll_clk);

drivers/spi/spi-bcm63xx-hsspi.c

809

bs->pll_clk = pll_clk;

drivers/spi/spi-bcm63xx-hsspi.c

891

clk_disable_unprepare(pll_clk);

drivers/spi/spi-bcm63xx-hsspi.c

905

clk_disable_unprepare(bs->pll_clk);

drivers/spi/spi-bcm63xx-hsspi.c

917

clk_disable_unprepare(bs->pll_clk);

drivers/spi/spi-bcm63xx-hsspi.c

933

if (bs->pll_clk) {

drivers/spi/spi-bcm63xx-hsspi.c

934

ret = clk_prepare_enable(bs->pll_clk);

drivers/spi/spi-bcmbca-hsspi.c

117

struct clk *pll_clk;

drivers/spi/spi-bcmbca-hsspi.c

439

struct clk *clk, *pll_clk = NULL;

drivers/spi/spi-bcmbca-hsspi.c

465

pll_clk = devm_clk_get(dev, "pll");

drivers/spi/spi-bcmbca-hsspi.c

467

if (IS_ERR(pll_clk)) {

drivers/spi/spi-bcmbca-hsspi.c

468

ret = PTR_ERR(pll_clk);

drivers/spi/spi-bcmbca-hsspi.c

472

ret = clk_prepare_enable(pll_clk);

drivers/spi/spi-bcmbca-hsspi.c

476

rate = clk_get_rate(pll_clk);

drivers/spi/spi-bcmbca-hsspi.c

492

bs->pll_clk = pll_clk;

drivers/spi/spi-bcmbca-hsspi.c

563

clk_disable_unprepare(pll_clk);

drivers/spi/spi-bcmbca-hsspi.c

576

clk_disable_unprepare(bs->pll_clk);

drivers/spi/spi-bcmbca-hsspi.c

588

clk_disable_unprepare(bs->pll_clk);

drivers/spi/spi-bcmbca-hsspi.c

604

if (bs->pll_clk) {

drivers/spi/spi-bcmbca-hsspi.c

605

ret = clk_prepare_enable(bs->pll_clk);

include/drm/bridge/samsung-dsim.h

108

struct clk *pll_clk;

sound/soc/codecs/lm49453.c

1198

u16 pll_clk = 0;

sound/soc/codecs/lm49453.c

1205

pll_clk = 0;

sound/soc/codecs/lm49453.c

1214

snd_soc_component_update_bits(component, LM49453_P0_PMC_SETUP_REG, BIT(4), pll_clk);

sound/soc/codecs/tas2552.c

160

unsigned int pll_clk = params_rate(params) * 512;

sound/soc/codecs/tas2552.c

175

if (pll_clkin == pll_clk)

sound/soc/codecs/tas2552.c

195

t = (pll_clk * 2) << p;