pl011_read
while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy)
cr = pl011_read(uap, REG_CR);
cr = pl011_read(uap, REG_CR);
pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
pl011_read(uap, REG_ICR);
pl011_read(uap, REG_ICR);
status = pl011_read(uap, REG_RIS) & uap->im;
status = pl011_read(uap, REG_RIS) & uap->im;
unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr;
unsigned int status = pl011_read(uap, REG_FR);
cr = pl011_read(uap, REG_CR);
lcr_h = pl011_read(uap, REG_LCRH_TX);
pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR);
pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap,
status = pl011_read(uap, REG_FR);
return pl011_read(uap, REG_DR);
while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
uap->im = pl011_read(uap, REG_IMSC);
if (pl011_read(uap, REG_FR) & UART01x_FR_RXFE)
pl011_read(uap, REG_DR);
cr = pl011_read(uap, REG_CR);
uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
val = pl011_read(uap, lcrh);
cr = pl011_read(uap, REG_CR);
old_cr = pl011_read(uap, REG_CR);
u32 cr = pl011_read(uap, REG_CR);
while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
if (!(pl011_read(uap, REG_CR) & UART01x_CR_UARTEN))
lcr_h = pl011_read(uap, REG_LCRH_TX);
ibrd = pl011_read(uap, REG_IBRD);
fbrd = pl011_read(uap, REG_FBRD);
(pl011_read(uap, REG_CR) & ST_UART011_CR_OVSFACT))
old_cr = pl011_read(uap, REG_CR);
while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr) & uap->vendor->fr_busy)
old_cr = pl011_read(uap, REG_CR);
while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr) & uap->vendor->fr_busy)
status = pl011_read(uap, REG_FR);
ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX;
if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) {