pipe_index
fams_pipe_data->pipe_index[pipe_idx++] = head_pipe->plane_res.hubp->inst;
fams_pipe_data->pipe_index[pipe_idx++] = split_pipe->plane_res.hubp->inst;
struct dml2_dchub_per_pipe_register_set *out, int pipe_index)
rq_dlg_get_rq_reg(&out->rq_regs, display_cfg, mode_lib, pipe_index);
rq_dlg_get_dlg_reg(&mode_lib->scratch, &out->dlg_regs, &out->ttu_regs, display_cfg, mode_lib, pipe_index);
out->det_size = dml_get_det_buffer_size_kbytes(mode_lib, pipe_index) / mode_lib->ip.config_return_buffer_segment_size_in_kbytes;
void dml2_core_calcs_get_global_sync_programming(const struct dml2_core_internal_display_mode_lib *mode_lib, union dml2_global_sync_programming *out, int pipe_index)
out->dcn4x.vready_offset_pixels = dml_get_vready_offset(mode_lib, pipe_index);
out->dcn4x.vstartup_lines = dml_get_vstartup_calculated(mode_lib, pipe_index);
out->dcn4x.vupdate_offset_pixels = dml_get_vupdate_offset(mode_lib, pipe_index);
out->dcn4x.vupdate_vupdate_width_pixels = dml_get_vupdate_width(mode_lib, pipe_index);
out->dcn4x.pstate_keepout_start_lines = dml_get_pstate_keepout_dst_lines(mode_lib, pipe_index);
void dml2_core_calcs_get_stream_programming(const struct dml2_core_internal_display_mode_lib *mode_lib, struct dml2_per_stream_programming *out, int pipe_index)
dml2_core_calcs_get_global_sync_programming(mode_lib, &out->global_sync, pipe_index);
void dml2_core_calcs_get_mall_allocation(struct dml2_core_internal_display_mode_lib *mode_lib, unsigned int *out, int pipe_index)
*out = dml_get_surface_size_in_mall_bytes(mode_lib, pipe_index);
void dml2_core_calcs_get_pipe_regs(const struct dml2_display_cfg *dml2_display_cfg, struct dml2_core_internal_display_mode_lib *mode_lib, struct dml2_dchub_per_pipe_register_set *out, int pipe_index);
void dml2_core_calcs_get_stream_programming(const struct dml2_core_internal_display_mode_lib *mode_lib, struct dml2_per_stream_programming *out, int pipe_index);
void dml2_core_calcs_get_global_sync_programming(const struct dml2_core_internal_display_mode_lib *mode_lib, union dml2_global_sync_programming *out, int pipe_index);
void dml2_core_calcs_get_mall_allocation(struct dml2_core_internal_display_mode_lib *mode_lib, unsigned int *out, int pipe_index);
int config_index, pipe_index;
for (pipe_index = 0; pipe_index < params->mcache_configurations[config_index].num_pipes; pipe_index++) {
params->per_plane_pipe_mcache_regs[config_index][pipe_index] = ¶ms->mcache_regs_set[free_per_plane_reg_index++];
reset_mcache_allocations(params->per_plane_pipe_mcache_regs[config_index][pipe_index]);
params->mcache_configurations[config_index].pipe_configurations[pipe_index].plane0.viewport_x_start,
params->mcache_configurations[config_index].pipe_configurations[pipe_index].plane0.viewport_x_start +
params->mcache_configurations[config_index].pipe_configurations[pipe_index].plane0.viewport_width - 1,
params->per_plane_pipe_mcache_regs[config_index][pipe_index]->main.p0.mcache_id_first =
params->per_plane_pipe_mcache_regs[config_index][pipe_index]->mall.p0.mcache_id_first =
params->per_plane_pipe_mcache_regs[config_index][pipe_index]->main.p0.mcache_id_second =
params->per_plane_pipe_mcache_regs[config_index][pipe_index]->main.p0.split_location =
params->per_plane_pipe_mcache_regs[config_index][pipe_index]->mall.p0.mcache_id_second =
params->per_plane_pipe_mcache_regs[config_index][pipe_index]->mall.p0.split_location =
if (params->mcache_configurations[config_index].pipe_configurations[pipe_index].plane1_enabled) {
params->mcache_configurations[config_index].pipe_configurations[pipe_index].plane1.viewport_x_start,
params->mcache_configurations[config_index].pipe_configurations[pipe_index].plane1.viewport_x_start +
params->mcache_configurations[config_index].pipe_configurations[pipe_index].plane1.viewport_width - 1,
params->per_plane_pipe_mcache_regs[config_index][pipe_index]->main.p1.mcache_id_first =
params->per_plane_pipe_mcache_regs[config_index][pipe_index]->mall.p1.mcache_id_first =
params->per_plane_pipe_mcache_regs[config_index][pipe_index]->main.p1.mcache_id_second =
params->per_plane_pipe_mcache_regs[config_index][pipe_index]->main.p1.split_location =
params->per_plane_pipe_mcache_regs[config_index][pipe_index]->mall.p1.mcache_id_second =
params->per_plane_pipe_mcache_regs[config_index][pipe_index]->mall.p1.split_location =
unsigned int pipe_index;
for (pipe_index = 0; pipe_index < pipe_count; pipe_index++) {
pipe_vp_startx[pipe_index], pipe_vp_endx[pipe_index], 0, 0)) {
unsigned int pipe_index = 0;
pipe_index = pipe->pipe_idx;
if (pipe->stream && dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index_valid[pipe_index] == false) {
dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index[pipe_index] = plane_index;
dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index_valid[pipe_index] = true;
uint8_t pipe_index[4];
unsigned int pipe_index;
pipe_index = high_pipe >> _DRM_VBLANK_HIGH_CRTC_SHIFT;
pipe_index = flags & _DRM_VBLANK_SECONDARY ? 1 : 0;
if (pipe_index == 0)
pipe_index--;
pipe = pipe_index;
unsigned int pipe_index)
if (vsp_plane->index == pipe_index)
unsigned int pipe_index);
unsigned int pipe_index)
int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
if (pipe_index >= vsp1->info->lif_count)
drm_pipe = &vsp1->drm->pipe[pipe_index];
__func__, pipe_index, cfg->width, cfg->height,
vsp1_write(vsp1, VI6_DISP_IRQ_STA(pipe_index), 0);
vsp1_write(vsp1, VI6_DISP_IRQ_ENB(pipe_index), 0);
void vsp1_du_atomic_begin(struct device *dev, unsigned int pipe_index)
int vsp1_du_atomic_update(struct device *dev, unsigned int pipe_index,
struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[pipe_index];
void vsp1_du_atomic_flush(struct device *dev, unsigned int pipe_index,
struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[pipe_index];
pipe->buffers_ready |= 1 << video->pipe_index;
rwpf->video->pipe_index = ++pipe->num_inputs;
rwpf->video->pipe_index = 0;
pipe->buffers_ready |= 1 << video->pipe_index;
pipe->buffers_ready &= ~(1 << video->pipe_index);
unsigned int pipe_index;
int pipe_index = atomisp_get_pipe_index(asd);
stream_index = (pipe_index == IA_CSS_PIPE_ID_YUVPP) ?
.pipes[pipe_index], &info)) {
int pipe_index = 0, i;
multi_pipes[pipe_index++] = stream_env->pipes[i];
if (pipe_index == 0)
pipe_index, multi_pipes, &stream_env->stream) != 0)
union pipe_index idx = { .head_tail = READ_ONCE(pipe->head_tail) };
union pipe_index idx = { .head_tail = READ_ONCE(pipe->head_tail) };
union pipe_index idx;
union pipe_index;
void vsp1_du_atomic_begin(struct device *dev, unsigned int pipe_index);
int vsp1_du_atomic_update(struct device *dev, unsigned int pipe_index,
void vsp1_du_atomic_flush(struct device *dev, unsigned int pipe_index,
int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
int pipe_index, int interleave)
err = allocate_pipes(chip, pipe, pipe_index, interleave);
pipe_index, err);
dev_dbg(chip->card->dev, "allocate_pipes()=%d\n", pipe_index);
chip->substream[pipe_index] = substream;
int pipe_index = ((struct audiopipe *)runtime->private_data)->index;
if (snd_BUG_ON(pipe_index >= px_num(chip)))
if (snd_BUG_ON(!is_pipe_allocated(chip, pipe_index)))
set_audio_format(chip, pipe_index, &format);
int pipe_index, int interleave)
"allocate_pipes: ch=%d int=%d\n", pipe_index, interleave);
channel_mask |= 1 << (pipe_index + i);
chip->comm_page->position[pipe_index] = 0;
pipe->index = pipe_index;
pipe->dma_counter = (__le32 *)&chip->comm_page->position[pipe_index];
return pipe_index;
static void set_audio_format(struct echoaudio *chip, u16 pipe_index,
"set_audio_format[%d] = %x\n", pipe_index, dsp_format);
chip->comm_page->audio_format[pipe_index] = cpu_to_le16(dsp_format);
static inline int is_pipe_allocated(struct echoaudio *chip, u16 pipe_index)
return (chip->pipe_alloc_mask & (1 << pipe_index));