phy_set_bits_mmd
return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
rc = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_CDIAG_RUN,
ret = phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_B10L_PMA_CTRL,
return phy_set_bits_mmd(phydev, MDIO_MMD_AN, ADIN_FORCED_MODE, ADIN_FORCED_MODE_EN);
ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H,
return phy_set_bits_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_10T1L_CTRL,
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ADIN_CRSM_SFT_RST, ADIN_CRSM_SFT_RST_EN);
err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1,
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PTP_CLK,
err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR,
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR,
phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
return phy_set_bits_mmd(phydev, DP83869_DEVADDR,
phy_set_bits_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_CTRL,
ret = phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL,
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_CTRL,
return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_CFG,
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_TDR_CFG,
return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
ret = phy_set_bits_mmd(phydev, MDIO_MMD_PCS,
int ret = phy_set_bits_mmd(phydev, MDIO_MMD_PCS, MV_1GBX_CTRL,
return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_TXDIS,
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
err = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2,
return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_BLINK_CTRL,
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323,
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326,
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DIR, BIT(pin));
return phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));
ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL1,
ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL2,
ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
return phy_set_bits_mmd(clock->phydev, PTP_MMD(clock), reg,
return phy_set_bits_mmd(phydev, PTP_MMD(clock), addr, val);
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_CFG_REG0,
return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_SGMII_PCS_CFG,
return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_REG_REG26,
return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, LAN887X_DSP_PMA_CONTROL,
rc = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_FUNC_ENABLES,
return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONTROL,
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, regmap->cable_test,
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_LINK_DROP_COUNTER,
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONFIG,
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RX_PREAMBLE_COUNT,
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TX_PREAMBLE_COUNT,
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RX_IPG_LENGTH,
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TX_IPG_LENGTH,
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_FUNC_ENABLES,
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_SYMBOL_ERROR_CNT_XTD,
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_MONITOR_STATUS,
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_MONITOR_CONFIG,
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONFIG,
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_CTRL2,
return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR,
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_HDD,
return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_HDD,
return phy_set_bits_mmd(phydev, MDIO_MMD_AN, reg,
return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
ret = phy_set_bits_mmd(phydev,
ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN,
return phy_set_bits_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_CNT_CTRL,