Symbol: phy_set_bits_mmd
drivers/net/phy/adin.c
459
return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/adin.c
800
rc = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/adin.c
919
return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_CDIAG_RUN,
drivers/net/phy/adin1100.c
108
ret = phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_B10L_PMA_CTRL,
drivers/net/phy/adin1100.c
117
return phy_set_bits_mmd(phydev, MDIO_MMD_AN, ADIN_FORCED_MODE, ADIN_FORCED_MODE_EN);
drivers/net/phy/adin1100.c
126
ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H,
drivers/net/phy/adin1100.c
223
return phy_set_bits_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_10T1L_CTRL,
drivers/net/phy/adin1100.c
235
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ADIN_CRSM_SFT_RST, ADIN_CRSM_SFT_RST_EN);
drivers/net/phy/aquantia/aquantia_main.c
1052
err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
drivers/net/phy/aquantia/aquantia_main.c
413
ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1,
drivers/net/phy/as21xxx.c
628
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PTP_CLK,
drivers/net/phy/dp83822.c
569
err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
drivers/net/phy/dp83822.c
630
err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
drivers/net/phy/dp83822.c
651
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR,
drivers/net/phy/dp83822.c
673
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR,
drivers/net/phy/dp83867.c
495
phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
drivers/net/phy/dp83867.c
842
phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
drivers/net/phy/dp83869.c
513
return phy_set_bits_mmd(phydev, DP83869_DEVADDR,
drivers/net/phy/dp83tc811.c
381
phy_set_bits_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,
drivers/net/phy/dp83td510.c
541
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
drivers/net/phy/dp83td510.c
703
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_CTRL,
drivers/net/phy/dp83td510.c
713
ret = phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL,
drivers/net/phy/dp83td510.c
768
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_CTRL,
drivers/net/phy/dp83td510.c
773
return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_CFG,
drivers/net/phy/dp83tg720.c
336
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
drivers/net/phy/dp83tg720.c
367
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_TDR_CFG,
drivers/net/phy/marvell-88q2xxx.c
605
return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
drivers/net/phy/marvell-88q2xxx.c
830
ret = phy_set_bits_mmd(phydev, MDIO_MMD_PCS,
drivers/net/phy/marvell-88x2222.c
100
int ret = phy_set_bits_mmd(phydev, MDIO_MMD_PCS, MV_1GBX_CTRL,
drivers/net/phy/marvell-88x2222.c
70
return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_TXDIS,
drivers/net/phy/marvell10g.c
1337
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
drivers/net/phy/marvell10g.c
1366
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
drivers/net/phy/marvell10g.c
306
return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
drivers/net/phy/marvell10g.c
329
return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
drivers/net/phy/marvell10g.c
612
err = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2,
drivers/net/phy/marvell10g.c
665
return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
drivers/net/phy/mediatek/mtk-2p5ge.c
351
phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
drivers/net/phy/mediatek/mtk-2p5ge.c
359
phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_BLINK_CTRL,
drivers/net/phy/mediatek/mtk-ge-soc.c
1012
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323,
drivers/net/phy/mediatek/mtk-ge-soc.c
1021
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326,
drivers/net/phy/mediatek/mtk-ge-soc.c
394
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
drivers/net/phy/mediatek/mtk-ge-soc.c
650
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
drivers/net/phy/mediatek/mtk-ge-soc.c
654
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
drivers/net/phy/mediatek/mtk-ge-soc.c
665
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/mediatek/mtk-ge-soc.c
676
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/mediatek/mtk-ge-soc.c
687
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/mediatek/mtk-ge-soc.c
698
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/mediatek/mtk-ge-soc.c
984
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/micrel.c
5548
ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
drivers/net/phy/micrel.c
5552
ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DIR, BIT(pin));
drivers/net/phy/micrel.c
5556
return phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));
drivers/net/phy/micrel.c
5636
ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL1,
drivers/net/phy/micrel.c
5639
ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL2,
drivers/net/phy/micrel.c
5791
ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
drivers/net/phy/microchip_rds_ptp.c
1098
return phy_set_bits_mmd(clock->phydev, PTP_MMD(clock), reg,
drivers/net/phy/microchip_rds_ptp.c
54
return phy_set_bits_mmd(phydev, PTP_MMD(clock), addr, val);
drivers/net/phy/microchip_t1.c
1128
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/microchip_t1.c
1144
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_CFG_REG0,
drivers/net/phy/microchip_t1.c
1150
return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_SGMII_PCS_CFG,
drivers/net/phy/microchip_t1.c
1400
return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_REG_REG26,
drivers/net/phy/microchip_t1.c
1417
return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, LAN887X_DSP_PMA_CONTROL,
drivers/net/phy/microchip_t1.c
2086
rc = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/mxl-gpy.c
753
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
drivers/net/phy/mxl-gpy.c
760
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
drivers/net/phy/mxl-gpy.c
767
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
drivers/net/phy/mxl-gpy.c
780
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
drivers/net/phy/nxp-c45-tja11xx-macsec.c
1608
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_FUNC_ENABLES,
drivers/net/phy/nxp-c45-tja11xx.c
1214
return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONTROL,
drivers/net/phy/nxp-c45-tja11xx.c
1223
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
1228
return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
1259
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
1330
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
1332
return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, regmap->cable_test,
drivers/net/phy/nxp-c45-tja11xx.c
1398
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
1429
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_LINK_DROP_COUNTER,
drivers/net/phy/nxp-c45-tja11xx.c
1661
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
1690
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONFIG,
drivers/net/phy/nxp-c45-tja11xx.c
1810
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RX_PREAMBLE_COUNT,
drivers/net/phy/nxp-c45-tja11xx.c
1812
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TX_PREAMBLE_COUNT,
drivers/net/phy/nxp-c45-tja11xx.c
1814
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RX_IPG_LENGTH,
drivers/net/phy/nxp-c45-tja11xx.c
1816
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TX_IPG_LENGTH,
drivers/net/phy/nxp-c45-tja11xx.c
1824
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_FUNC_ENABLES,
drivers/net/phy/nxp-c45-tja11xx.c
1835
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
1925
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_SYMBOL_ERROR_CNT_XTD,
drivers/net/phy/nxp-c45-tja11xx.c
1927
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_MONITOR_STATUS,
drivers/net/phy/nxp-c45-tja11xx.c
1929
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_MONITOR_CONFIG,
drivers/net/phy/nxp-c45-tja11xx.c
1939
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONFIG,
drivers/net/phy/nxp-c45-tja11xx.c
1946
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
824
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
836
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
845
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/phy-c45.c
1262
ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
drivers/net/phy/phy-c45.c
1267
ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_CTRL2,
drivers/net/phy/phy-c45.c
1273
return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR,
drivers/net/phy/phy-c45.c
1434
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
drivers/net/phy/phy-c45.c
1685
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_HDD,
drivers/net/phy/phy-c45.c
1694
return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_HDD,
drivers/net/phy/phy-c45.c
348
return phy_set_bits_mmd(phydev, MDIO_MMD_AN, reg,
drivers/net/phy/phy-c45.c
72
return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
drivers/net/phy/qcom/qca807x.c
664
ret = phy_set_bits_mmd(phydev,
drivers/net/phy/qcom/qca808x.c
205
ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN,
drivers/net/phy/qcom/qcom-phy-lib.c
710
return phy_set_bits_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_CNT_CTRL,