drivers/net/ethernet/realtek/r8169_phy_config.c

304

phy_set_bits(phydev, 0x14, BIT(5));

drivers/net/ethernet/realtek/r8169_phy_config.c

305

phy_set_bits(phydev, 0x0d, BIT(5));

drivers/net/ethernet/realtek/r8169_phy_config.c

334

phy_set_bits(phydev, 0x14, BIT(5));

drivers/net/ethernet/realtek/r8169_phy_config.c

335

phy_set_bits(phydev, 0x0d, BIT(5));

drivers/net/ethernet/realtek/r8169_phy_config.c

361

phy_set_bits(phydev, 0x16, BIT(0));

drivers/net/ethernet/realtek/r8169_phy_config.c

362

phy_set_bits(phydev, 0x14, BIT(5));

drivers/net/ethernet/realtek/r8169_phy_config.c

363

phy_set_bits(phydev, 0x0d, BIT(5));

drivers/net/ethernet/realtek/r8169_phy_config.c

383

phy_set_bits(phydev, 0x16, BIT(0));

drivers/net/ethernet/realtek/r8169_phy_config.c

384

phy_set_bits(phydev, 0x14, BIT(5));

drivers/net/ethernet/realtek/r8169_phy_config.c

385

phy_set_bits(phydev, 0x0d, BIT(5));

drivers/net/ethernet/realtek/r8169_phy_config.c

491

phy_set_bits(phydev, 0x0d, 0x0300);

drivers/net/ethernet/realtek/r8169_phy_config.c

492

phy_set_bits(phydev, 0x0f, 0x0010);

drivers/net/ethernet/realtek/r8169_phy_config.c

532

phy_set_bits(phydev, 0x0d, BIT(5));

drivers/net/ethernet/realtek/r8169_phy_config.c

569

phy_set_bits(phydev, 0x14, BIT(15));

drivers/net/ethernet/realtek/r8169_phy_config.c

599

phy_set_bits(phydev, 0x17, 0x0006);

drivers/net/ethernet/realtek/r8169_phy_config.c

604

phy_set_bits(phydev, 0x14, BIT(15));

drivers/net/ethernet/realtek/r8169_phy_config.c

616

phy_set_bits(phydev, 0x19, BIT(0));

drivers/net/ethernet/realtek/r8169_phy_config.c

617

phy_set_bits(phydev, 0x10, BIT(10));

drivers/net/ethernet/realtek/r8169_phy_config.c

630

phy_set_bits(phydev, 0x14, BIT(15));

drivers/net/ethernet/realtek/r8169_phy_config.c

930

phy_set_bits(phydev, 0x11, BIT(12));

drivers/net/ethernet/realtek/r8169_phy_config.c

931

phy_set_bits(phydev, 0x19, BIT(13));

drivers/net/ethernet/realtek/r8169_phy_config.c

932

phy_set_bits(phydev, 0x10, BIT(15));

drivers/net/ethernet/realtek/r8169_phy_config.c

940

phy_set_bits(phydev, 0x11, BIT(12));

drivers/net/phy/adin.c

388

return phy_set_bits(phydev, ADIN1300_PHY_CTRL2,

drivers/net/phy/adin.c

594

err = phy_set_bits(phydev, ADIN1300_INT_MASK_REG,

drivers/net/phy/adin.c

732

ret = phy_set_bits(phydev, ADIN1300_PHY_CTRL3, ADIN1300_LINKING_EN);

drivers/net/phy/bcm-phy-lib.c

636

return phy_set_bits(phydev, MII_BCM54XX_ECR, MII_BCM54XX_ECR_FIFOE);

drivers/net/phy/broadcom.c

177

rc = phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN);

drivers/net/phy/dp83867.c

930

phy_set_bits(phydev, DP83867_CFG2,

drivers/net/phy/icplus.c

281

ret = phy_set_bits(phydev, IP10XX_SPEC_CTRL_STATUS, IP101A_G_APS_ON);

drivers/net/phy/intel-xway.c

501

return phy_set_bits(phydev, XWAY_MDIO_LED, XWAY_GPHY_LED_EN(index));

drivers/net/phy/intel-xway.c

527

return phy_set_bits(phydev, XWAY_MDIO_LED, XWAY_GPHY_LED_INV(index));

drivers/net/phy/marvell.c

1341

err = phy_set_bits(phydev, MII_88E1510_GEN_CTRL_REG_1,

drivers/net/phy/marvell.c

1583

return phy_set_bits(phydev, MII_88E1540_COPPER_CTRL3,

drivers/net/phy/mediatek/mtk-2p5ge.c

82

phy_set_bits(phydev, MII_BMCR, BMCR_RESET);

drivers/net/phy/mediatek/mtk-2p5ge.c

85

phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN);

drivers/net/phy/mediatek/mtk-2p5ge.c

96

phy_set_bits(phydev, MII_BMCR, BMCR_RESET);

drivers/net/phy/mediatek/mtk-ge.c

81

phy_set_bits(phydev, 0x17, BIT(4));

drivers/net/phy/micrel.c

1447

return phy_set_bits(phydev, 0x1e, BIT(9));

drivers/net/phy/micrel.c

1946

ret = phy_set_bits(phydev, MII_KSZPHY_CTRL,

drivers/net/phy/mxl-gpy.c

1015

return phy_set_bits(phydev, PHY_LED, PHY_LED_HWCONTROL(index));

drivers/net/phy/mxl-gpy.c

1041

return phy_set_bits(phydev, PHY_LED, PHY_LED_POLARITY(index));

drivers/net/phy/mxl-gpy.c

812

ret = phy_set_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC);

drivers/net/phy/nxp-cbtx.c

105

return phy_set_bits(phydev, CBTX_MODE_CTRL_STAT,

drivers/net/phy/nxp-cbtx.c

89

return phy_set_bits(phydev, CBTX_MODE_CTRL_STAT,

drivers/net/phy/nxp-tja11xx.c

133

return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_CONFIG_EN);

drivers/net/phy/nxp-tja11xx.c

138

return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_LINK_CONTROL);

drivers/net/phy/nxp-tja11xx.c

158

ret = phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST);

drivers/net/phy/nxp-tja11xx.c

189

return phy_set_bits(phydev, MII_CFG3, MII_CFG3_PHY_EN);

drivers/net/phy/nxp-tja11xx.c

343

ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP);

drivers/net/phy/nxp-tja11xx.c

739

return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_CABLE_TEST);

drivers/net/phy/nxp-tja11xx.c

800

ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP);

drivers/net/phy/phy_device.c

2816

return phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN);

drivers/net/phy/qcom/at803x.c

916

err = phy_set_bits(phydev, AT803X_INTR_ENABLE, value);

drivers/net/phy/qcom/qca83xx.c

121

phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER);

drivers/net/phy/qcom/qca83xx.c

165

phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);

drivers/net/phy/realtek/realtek_main.c

1086

ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE,

drivers/net/phy/realtek/realtek_main.c

586

return phy_set_bits(phydev, MII_CTRL1000,

drivers/net/phy/smsc.c

214

int rc = phy_set_bits(phydev, PHY_EDPD_CONFIG,

drivers/net/phy/smsc.c

94

return phy_set_bits(phydev, MII_LAN83C185_CTRL_STATUS,