phy_modify_mmd
return phy_modify_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_CLK_CFG_REG,
return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index),
err = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index),
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR,
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR,
return phy_modify_mmd(phydev, MDIO_MMD_VEND1, AQR_LED_PROV(index),
return phy_modify_mmd(phydev, MDIO_MMD_VEND1, AQR_LED_DRIVE(index),
return phy_modify_mmd(phydev, MDIO_MMD_VEND1, AQR_LED_PROV(index),
return phy_modify_mmd(phydev, MDIO_MMD_PHYXS,
err = phy_modify_mmd(phydev, MDIO_MMD_VEND1,
return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
return phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, PMAPMD_RSVD_VEND_PROV,
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLB_REG_CPU_CTRL,
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1,
return phy_modify_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLB_REG_CPU_CTRL,
return phy_modify_mmd(phydev, MDIO_MMD_VEND1,
return phy_modify_mmd(phydev, MDIO_MMD_VEND1,
return phy_modify_mmd(phydev, MDIO_MMD_VEND1,
return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_MLEDCR,
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_IOCTRL2,
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_IOCTRL1,
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_IOCTRL1,
phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_IOCTRL2,
phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_LDCTRL,
phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_IOCTRL,
err = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR,
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83826_VOD_CFG1, mask, val);
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83826_VOD_CFG2, mask, val);
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83826_VOD_CFG2, mask, val);
ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
ret = phy_modify_mmd(phydev, DP83869_DEVADDR,
ret = phy_modify_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE,
ret = phy_modify_mmd(phydev,
return phy_modify_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_LEDS_CFG_2,
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_LEDS_CFG_1,
return phy_modify_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_LEDS_CFG_2,
return phy_modify_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_LEDS_CFG_2,
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_CFG1,
return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
return phy_modify_mmd(phydev, MDIO_MMD_PCS,
return phy_modify_mmd(phydev, MDIO_MMD_PCS,
ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, 0xfc5d, 0xff, 0xac);
return phy_modify_mmd(phydev, MDIO_MMD_PCS, MDIO_MMD_PCS_MV_TEMP_SENSOR2,
return phy_modify_mmd(phydev, MDIO_MMD_PCS,
return phy_modify_mmd(phydev, MDIO_MMD_PCS,
return phy_modify_mmd(phydev, MDIO_MMD_PCS,
return phy_modify_mmd(phydev, MDIO_MMD_PCS,
ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, MV_1GBX_ADVERTISE,
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2,
return phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL,
err = phy_modify_mmd(phydev, MDIO_MMD_PCS, unit + MDIO_CTRL1,
err = phy_modify_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC2,
return phy_modify_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1,
err = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_21X0_PORT_CTRL,
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LPI_PCS_DSP_CTRL,
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7,
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1,
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324,
phy_modify_mmd(phydev, MDIO_MMD_VEND1,
phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
phy_modify_mmd(phydev, devad, regnum,
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5,
phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL,
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C,
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D,
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
phy_modify_mmd(phydev, MDIO_MMD_VEND1,
phy_modify_mmd(phydev, MDIO_MMD_VEND1,
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238,
phy_modify_mmd(phydev, MDIO_MMD_VEND1,
phy_modify_mmd(phydev, MDIO_MMD_VEND1,
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_GBE_MODE_TX_DELAY_SEL,
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TEST_MODE_TX_DELAY_SEL,
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,
phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,
phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
phy_modify_mmd(phydev, 2, LAN8841_PTP_TX_MOD,
ret = phy_modify_mmd(phydev, 2, LAN8841_PTP_GENERAL_CONFIG,
ret = phy_modify_mmd(phydev, 2, LAN8841_PTP_GENERAL_CONFIG,
return phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,
ret = phy_modify_mmd(phydev, 2, LAN8841_PTP_GPIO_CAP_EN,
return phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,
return phy_modify_mmd(phydev, PTP_MMD(clock), addr, mask, val);
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_CFG_REG0,
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_CFG_REG0,
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG1,
return phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG0,
phy_modify_mmd(phydev, MDIO_MMD_VEND1,
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1,
rc = phy_modify_mmd(phydev, MDIO_MMD_VEND1,
rc = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD,
rc = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_REG_REG26,
rc = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_POKE_PEEK_100,
err = phy_modify_mmd(phydev, MDIO_MMD_VEND2,
return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
return phy_modify_mmd(phydev, MDIO_MMD_VEND2, LAN86XX_REG_COL_DET_CTRL0,
return phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
return phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
return phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL,
return phy_modify_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1,
ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL,
EXPORT_SYMBOL_GPL(phy_modify_mmd);
return phy_modify_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1,
phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, IPQ5018_PHY_MMD1_MDAC,
return phy_modify_mmd(phydev, MDIO_MMD_PCS,
ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1,
return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3,
return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M,
return phy_modify_mmd(phydev, MDIO_MMD_PCS,
return phy_modify_mmd(phydev, MDIO_MMD_AN, reg, mask,
ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7,
return phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
return phy_modify_mmd(phydev, MDIO_MMD_AN,
ret = phy_modify_mmd(phydev, MDIO_MMD_PCS,
ret = phy_modify_mmd(phydev, MDIO_MMD_PCS,
return phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
ret = phy_modify_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_LED_GLOBAL,
ret = phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2,
return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
int phy_modify_mmd(struct phy_device *phydev, int devad, u32 regnum,
return phy_modify_mmd(phydev, devad, regnum, 0, val);
return phy_modify_mmd(phydev, devad, regnum, val, 0);