phy_config
struct inno_hdmi_phy_config *phy_config;
phy_config = hdmi->plat_data->default_phy_config;
phy_config = &hdmi->plat_data->phy_configs[ret];
hdmi_writeb(hdmi, HDMI_PHY_PRE_EMPHASIS, phy_config->pre_emphasis);
hdmi_writeb(hdmi, HDMI_PHY_DRIVER, phy_config->voltage_level_control);
const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
for (; phy_config->mpixelclock != ~0UL; phy_config++)
if (mpixelclock <= phy_config->mpixelclock)
phy_config->mpixelclock == ~0UL)
dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM);
dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr,
dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr,
.phy_config = imx_phy_config,
.phy_config = imx_phy_config,
.phy_config = ingenic_phy_config,
.phy_config = rockchip_phy_config,
.phy_config = rockchip_phy_config,
.phy_config = rockchip_phy_config,
.phy_config = rockchip_phy_config,
plat_data->phy_config = variant->phy_cfg;
ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >>
u8 phy_config;
struct phylink_config phy_config;
port->phy_config.dev = &port->dev->dev;
port->phy_config.type = PHYLINK_NETDEV;
port->phy_config.supported_interfaces);
port->phy_config.supported_interfaces);
port->phy_config.supported_interfaces);
port->phy_config.supported_interfaces);
port->phy_config.mac_capabilities =
phy_link = phylink_create(&port->phy_config, fwnode,
u32 phy_config;
drv->fw.phy_config = le32_to_cpup((const __le32 *)tlv_data);
drv->fw.valid_tx_ant = (drv->fw.phy_config &
drv->fw.valid_rx_ant = (drv->fw.phy_config &
u32 phy_config = ~(FW_PHY_CFG_TX_CHAIN |
phy_config |= valid_tx_ant << FW_PHY_CFG_TX_CHAIN_POS |
return mld->fw->phy_config & phy_config;
u32 phy_config = ~(FW_PHY_CFG_TX_CHAIN |
phy_config |= valid_tx_ant << FW_PHY_CFG_TX_CHAIN_POS |
return mvm->fw->phy_config & phy_config;
u32 phy_config = iwl_mvm_get_phy_config(mvm);
radio_cfg_type = (phy_config & FW_PHY_CFG_RADIO_TYPE) >>
radio_cfg_step = (phy_config & FW_PHY_CFG_RADIO_STEP) >>
radio_cfg_dash = (phy_config & FW_PHY_CFG_RADIO_DASH) >>
u32 phy_config;
phy_config = grf5101_encode[(data >> 8) & 0xF];
phy_config |= grf5101_encode[(data >> 4) & 0xF] << 4;
phy_config |= grf5101_encode[data & 0xF] << 8;
phy_config |= grf5101_encode[(addr >> 1) & 0xF] << 12;
phy_config |= (addr & 1) << 16;
phy_config |= grf5101_encode[(data & 0xf000) >> 12] << 24;
phy_config |= 0x90000000;
(__le32 __iomem *) &priv->map->RFPinsOutput, phy_config);
u32 phy_config;
phy_config = 0x90 + (data & 0xf);
phy_config <<= 16;
phy_config += addr;
phy_config <<= 8;
phy_config += (data >> 4) & 0xff;
(__le32 __iomem *) &priv->map->RFPinsOutput, phy_config);
u32 phy_config;
phy_config = 0xb0000000;
phy_config |= ((u32)(addr & 0xf)) << 24;
phy_config |= data & 0xffffff;
(__le32 __iomem *) &priv->map->RFPinsOutput, phy_config);
const struct phy_config *cur_cfg;
const struct phy_config *cfg)
const struct phy_config *cfg)
static const struct phy_config *fsl_samsung_hdmi_phy_lookup_rate(unsigned long rate)
static void fsl_samsung_hdmi_calculate_phy(struct phy_config *cal_phy, unsigned long rate,
const struct phy_config *fsl_samsung_hdmi_phy_find_settings(struct fsl_samsung_hdmi_phy *phy,
const struct phy_config *fract_div_phy;
const struct phy_config *target_settings = fsl_samsung_hdmi_phy_find_settings(phy,
static struct phy_config calculated_phy_pll_cfg = {
const struct phy_config *target_settings = fsl_samsung_hdmi_phy_find_settings(phy, rate);
static const struct phy_config phy_pll_cfg[] = {
const struct phy_config *phy_cfg)
const struct phy_config *phy_cfg)
const struct phy_config *phy_cfg);
const struct phy_config *phy_cfg_table;
static const struct phy_config rk3228_phy_cfg[] = {
static const struct phy_config rk3328_phy_cfg[] = {
const struct phy_config *phy_cfg = inno->plat_data->phy_cfg_table;
const struct dw_hdmi_phy_config *phy_config;
if (!pp->phy_config.set_root && !pp->phy_config.set_gap_count) {
printf("ext phy config: phy_id=%02x", pp->phy_config.root_id);
if (pp->phy_config.set_root)
printf(" set_root_id=%02x", pp->phy_config.root_id);
if (pp->phy_config.set_gap_count)
printf(" set_gap_count=%u", pp->phy_config.gap_count);
} phy_config;