phy_clear_bits
phy_clear_bits(phydev, 0x03, 0xe000);
phy_clear_bits(phydev, 0x03, 0xe000);
phy_clear_bits(phydev, 0x19, BIT(0));
phy_clear_bits(phydev, 0x10, BIT(10));
return phy_clear_bits(phydev, ADIN1300_PHY_CTRL2,
return phy_clear_bits(phydev, ADIN1300_PHY_CTRL_STATUS2,
err = phy_clear_bits(phydev, ADIN1300_INT_MASK_REG,
ret = phy_clear_bits(phydev, ADIN1300_PHY_CTRL1, ADIN1300_DIAG_CLK_EN);
ret = phy_clear_bits(phydev, ADIN1300_PHY_CTRL3, ADIN1300_LINKING_EN);
ret = phy_clear_bits(phydev, ADIN1300_PHY_CTRL1, ADIN1300_DIAG_CLK_EN);
rc = phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN);
return phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN);
return phy_clear_bits(phydev, DP83867_CFG2,
return phy_clear_bits(phydev, DP83869_CFG2,
return phy_clear_bits(phydev, XWAY_MDIO_LED, XWAY_GPHY_LED_INV(index));
err = phy_clear_bits(phydev, MII_M1111_PHY_EXT_CR,
err = phy_clear_bits(phydev, MII_M1011_PHY_SCR,
return phy_clear_bits(phydev, MII_88E1540_COPPER_CTRL3,
ret = phy_clear_bits(phydev, MII_BMCR, BMCR_ANENABLE);
return phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN);
ret = phy_clear_bits(phydev, MII_KSZPHY_CTRL,
return phy_clear_bits(phydev, MII_BMCR, BMCR_ANENABLE | BMCR_SPEED100);
phy_clear_bits(phydev, MII_KSZPHY_OMSO, KSZPHY_OMSO_FACTORY_TEST);
return phy_clear_bits(phydev, PHY_LED, PHY_LED_POLARITY(index));
ret = phy_clear_bits(phydev, PHY_IMASK, PHY_IMASK_WOL);
return phy_clear_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC);
ret = phy_clear_bits(phydev, CBTX_MODE_CTRL_STAT,
ret = phy_clear_bits(phydev, CBTX_PDOWN_CTRL,
ret = phy_clear_bits(phydev, CBTX_MODE_CTRL_STAT,
return phy_clear_bits(phydev, CBTX_MODE_CTRL_STAT,
return phy_clear_bits(phydev, MII_ECTRL, MII_ECTRL_LINK_CONTROL);
ret = phy_clear_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST);
ret = phy_clear_bits(phydev, MII_CFG1, MII_CFG1_SLEEP_CONFIRM);
ret = phy_clear_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP);
return phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN);
return phy_clear_bits(phydev, MII_LAN83C185_CTRL_STATUS,