phy_base_write
int phy_base_write(struct phy_device *phydev, u32 regnum, u16 val);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, RUN_FROM_INT_ROM |
phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM | INT_MEM_WRITE_EN |
phy_base_write(phydev, MSCC_INT_MEM_ADDR, 0x0000);
phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM |
phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0);
phy_base_write(phydev, MSCC_PHY_EXT_PHY_CNTL_2, 0x0040);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
phy_base_write(phydev, MSCC_PHY_TEST_PAGE_20, 0x4320);
phy_base_write(phydev, MSCC_PHY_TEST_PAGE_24, 0x0c00);
phy_base_write(phydev, MSCC_PHY_TEST_PAGE_9, 0x18ca);
phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1b20);
phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2);
phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), 0x3eb7);
phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), 0x4012);
phy_base_write(phydev, MSCC_INT_MEM_CNTL,
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0);
phy_base_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_3);
phy_base_write(phydev, MSCC_PHY_SERDES_TX_CRC_ERR_CNT, 0x2000);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1f20);
phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x2fa4));
phy_base_write(phydev, MSCC_PHY_TR_MSB, reg);
phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x0fa4));
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2);
phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_GPIO);
ret = phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), reg);
ret = phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), reg);
ret = phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val);
ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val);
ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val);
ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
ret = phy_base_write(phydev, MSCC_INT_MEM_CNTL, val);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
ret = phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), reg);
ret = phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), reg);
ret = phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL);
phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20,
phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19,
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL);
phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20,
phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_17, (u16)val);
phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_18, (u16)(val >> 16));
phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19,
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
phy_base_write(phydev, MSCC_PHY_TR_MSB, val >> 16);
phy_base_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0));
phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr));
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NCOMPLETED | val);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM);
phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, enable);
phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, release);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(4), 0x005b);
phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(4), 0x005b);
phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NOP);
phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, reg);
phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_MCB_ACCESS_MAC_CONF |
phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_2, start);
phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_3, size);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_GPIO);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);