phy_base_read
int phy_base_read(struct phy_device *phydev, u32 regnum);
reg = phy_base_read(phydev, MSCC_TRAP_ROM_ADDR(1));
reg = phy_base_read(phydev, MSCC_PATCH_RAM_ADDR(1));
reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS);
reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
reg = phy_base_read(phydev, MSCC_PHY_BYPASS_CONTROL);
reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
reg = phy_base_read(phydev, MSCC_PHY_TR_MSB);
reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);
val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);
val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);
val = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19);
val_l = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_17);
val_h = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_18);
val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19);
reg_val = phy_base_read(phydev, MSCC_PHY_PROC_CMD);
reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS);
reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
*crc = phy_base_read(phydev, MSCC_PHY_VERIPHY_CNTL_2);
ret = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);