drivers/gpu/drm/amd/pm/powerplay/hwmgr/hwmgr_ppt.h

47

typedef struct phm_ppt_v1_clock_voltage_dependency_record phm_ppt_v1_clock_voltage_dependency_record;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/hwmgr_ppt.h

51

phm_ppt_v1_clock_voltage_dependency_record entries[]; /* Dynamically allocate count entries. */

drivers/gpu/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

319

phm_ppt_v1_clock_voltage_dependency_record *dep_record;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

332

phm_ppt_v1_clock_voltage_dependency_record,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

367

phm_ppt_v1_clock_voltage_dependency_record *mclk_table_record;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

382

phm_ppt_v1_clock_voltage_dependency_record,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

407

phm_ppt_v1_clock_voltage_dependency_record *sclk_table_record;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

429

phm_ppt_v1_clock_voltage_dependency_record,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

458

phm_ppt_v1_clock_voltage_dependency_record,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

179

phm_ppt_v1_clock_voltage_dependency_record entries[MAX_REGULAR_DPM_NUMBER];

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

286

struct phm_ppt_v1_clock_voltage_dependency_record entries[MAX_REGULAR_DPM_NUMBER];

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

283

struct phm_ppt_v1_clock_voltage_dependency_record

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

346

struct phm_ppt_v1_clock_voltage_dependency_record