arch/alpha/include/asm/core_marvel.h

249

#define IO7_IPE(pe) (EV7_IPE(pe))

arch/alpha/include/asm/core_marvel.h

252

#define IO7_HOSE(pe, port) (IO7_IPE(pe) | IO7_IPORT(port))

arch/alpha/include/asm/core_marvel.h

254

#define IO7_MEM_PHYS(pe, port) (IO7_HOSE(pe, port) | 0x00000000UL)

arch/alpha/include/asm/core_marvel.h

255

#define IO7_CONF_PHYS(pe, port) (IO7_HOSE(pe, port) | 0xFE000000UL)

arch/alpha/include/asm/core_marvel.h

256

#define IO7_IO_PHYS(pe, port) (IO7_HOSE(pe, port) | 0xFF000000UL)

arch/alpha/include/asm/core_marvel.h

257

#define IO7_CSR_PHYS(pe, port, off) \

arch/alpha/include/asm/core_marvel.h

258

(IO7_HOSE(pe, port) | 0xFF800000UL | (off))

arch/alpha/include/asm/core_marvel.h

259

#define IO7_CSRS_PHYS(pe, port) (IO7_CSR_PHYS(pe, port, 0UL))

arch/alpha/include/asm/core_marvel.h

260

#define IO7_PORT7_CSRS_PHYS(pe) (IO7_CSR_PHYS(pe, 7, 0x300000UL))

arch/alpha/include/asm/core_marvel.h

262

#define IO7_MEM_KERN(pe, port) (IO7_KERN_ADDR(IO7_MEM_PHYS(pe, port)))

arch/alpha/include/asm/core_marvel.h

263

#define IO7_CONF_KERN(pe, port) (IO7_KERN_ADDR(IO7_CONF_PHYS(pe, port)))

arch/alpha/include/asm/core_marvel.h

264

#define IO7_IO_KERN(pe, port) (IO7_KERN_ADDR(IO7_IO_PHYS(pe, port)))

arch/alpha/include/asm/core_marvel.h

265

#define IO7_CSR_KERN(pe, port, off) (IO7_KERN_ADDR(IO7_CSR_PHYS(pe,port,off)))

arch/alpha/include/asm/core_marvel.h

266

#define IO7_CSRS_KERN(pe, port) (IO7_KERN_ADDR(IO7_CSRS_PHYS(pe, port)))

arch/alpha/include/asm/core_marvel.h

267

#define IO7_PORT7_CSRS_KERN(pe) (IO7_KERN_ADDR(IO7_PORT7_CSRS_PHYS(pe)))

arch/alpha/include/asm/core_marvel.h

312

unsigned int pe;

arch/alpha/include/asm/core_marvel.h

57

#define EV7_IPE(pe) ((~((long)(pe)) & EV7_PE_MASK) << 35)

arch/alpha/include/asm/core_marvel.h

59

#define EV7_CSR_PHYS(pe, off) (EV7_IPE(pe) | (0x7FFCUL << 20) | (off))

arch/alpha/include/asm/core_marvel.h

60

#define EV7_CSRS_PHYS(pe) (EV7_CSR_PHYS(pe, 0UL))

arch/alpha/include/asm/core_marvel.h

62

#define EV7_CSR_KERN(pe, off) (EV7_KERN_ADDR(EV7_CSR_PHYS(pe, off)))

arch/alpha/include/asm/core_marvel.h

63

#define EV7_CSRS_KERN(pe) (EV7_KERN_ADDR(EV7_CSRS_PHYS(pe)))

arch/alpha/kernel/core_marvel.c

100

marvel_find_io7(int pe)

arch/alpha/kernel/core_marvel.c

104

for (io7 = io7_head; io7 && io7->pe != pe; io7 = io7->next)

arch/alpha/kernel/core_marvel.c

111

alloc_io7(unsigned int pe)

arch/alpha/kernel/core_marvel.c

117

if (marvel_find_io7(pe)) {

arch/alpha/kernel/core_marvel.c

118

printk(KERN_WARNING "IO7 at PE %d already allocated!\n", pe);

arch/alpha/kernel/core_marvel.c

123

io7->pe = pe;

arch/alpha/kernel/core_marvel.c

137

else if (io7_head->pe > io7->pe) { /* insert at head */

arch/alpha/kernel/core_marvel.c

142

if (insp->pe == io7->pe) {

arch/alpha/kernel/core_marvel.c

144

io7->pe);

arch/alpha/kernel/core_marvel.c

149

insp->next->pe > io7->pe) { /* insert here */

arch/alpha/kernel/core_marvel.c

158

" - adding at head of list\n", io7->pe);

arch/alpha/kernel/core_marvel.c

179

csrs = IO7_CSRS_KERN(io7->pe, port);

arch/alpha/kernel/core_marvel.c

190

p7csrs = IO7_PORT7_CSRS_KERN(io7->pe);

arch/alpha/kernel/core_marvel.c

208

io7_ioport_csrs *csrs = IO7_CSRS_KERN(io7->pe, port);

arch/alpha/kernel/core_marvel.c

236

hose->dense_mem_base = IO7_MEM_PHYS(io7->pe, port);

arch/alpha/kernel/core_marvel.c

237

hose->dense_io_base = IO7_IO_PHYS(io7->pe, port);

arch/alpha/kernel/core_marvel.c

242

hose->config_space_base = (unsigned long)IO7_CONF_KERN(io7->pe, port);

arch/alpha/kernel/core_marvel.c

244

hose->io_space->start = (unsigned long)IO7_IO_KERN(io7->pe, port);

arch/alpha/kernel/core_marvel.c

246

hose->io_space->name = mk_resource_name(io7->pe, port, "IO");

arch/alpha/kernel/core_marvel.c

249

hose->mem_space->start = (unsigned long)IO7_MEM_KERN(io7->pe, port);

arch/alpha/kernel/core_marvel.c

251

hose->mem_space->name = mk_resource_name(io7->pe, port, "MEM");

arch/alpha/kernel/core_marvel.c

336

printk("Initializing IO7 at PID %d\n", io7->pe);

arch/alpha/kernel/core_marvel.c

341

io7->csrs = IO7_PORT7_CSRS_KERN(io7->pe);

arch/alpha/kernel/core_marvel.c

347

io7_ioport_csrs *csrs = IO7_CSRS_KERN(io7->pe, i);

arch/alpha/kernel/core_marvel.c

358

int pe;

arch/alpha/kernel/core_marvel.c

364

pe = (node->id >> 8) & 0xff;

arch/alpha/kernel/core_marvel.c

365

printk("Found an IO7 at PID %d\n", pe);

arch/alpha/kernel/core_marvel.c

367

alloc_io7(pe);

arch/alpha/kernel/core_marvel.c

56

read_ev7_csr(int pe, unsigned long offset)

arch/alpha/kernel/core_marvel.c

58

ev7_csr *ev7csr = EV7_CSR_KERN(pe, offset);

arch/alpha/kernel/core_marvel.c

69

write_ev7_csr(int pe, unsigned long offset, unsigned long q)

arch/alpha/kernel/core_marvel.c

71

ev7_csr *ev7csr = EV7_CSR_KERN(pe, offset);

arch/alpha/kernel/core_marvel.c

79

mk_resource_name(int pe, int port, char *str)

arch/alpha/kernel/core_marvel.c

85

sz = scnprintf(tmp, sizeof(tmp), "PCI %s PE %d PORT %d", str, pe, port);

arch/alpha/kernel/err_marvel.c

897

lf_subpackets->io_pid = io7->pe;

arch/alpha/kernel/perf_event.c

344

struct perf_event *pe;

arch/alpha/kernel/perf_event.c

354

for_each_sibling_event(pe, group) {

arch/alpha/kernel/perf_event.c

355

if (!is_software_event(pe) && pe->state != PERF_EVENT_STATE_OFF) {

arch/alpha/kernel/perf_event.c

358

event[n] = pe;

arch/alpha/kernel/perf_event.c

359

evtype[n] = pe->hw.event_base;

arch/alpha/kernel/perf_event.c

400

struct perf_event *pe = cpuc->event[j];

arch/alpha/kernel/perf_event.c

403

cpuc->current_idx[j] != pe->hw.idx) {

arch/alpha/kernel/perf_event.c

404

alpha_perf_event_update(pe, &pe->hw, cpuc->current_idx[j], 0);

arch/alpha/kernel/perf_event.c

412

struct perf_event *pe = cpuc->event[j];

arch/alpha/kernel/perf_event.c

413

struct hw_perf_event *hwc = &pe->hw;

arch/alpha/kernel/perf_event.c

417

alpha_perf_event_set_period(pe, hwc, idx);

arch/alpha/kernel/proto.h

42

struct io7 *marvel_find_io7(int pe);

arch/alpha/kernel/sys_marvel.c

249

long base = (io7->pe << MARVEL_IRQ_VEC_PE_SHIFT) + 16;

arch/alpha/kernel/sys_marvel.c

253

io7->pe, base);

arch/alpha/kernel/sys_marvel.c

359

(irq + 16) | (io7->pe << MARVEL_IRQ_VEC_PE_SHIFT),

arch/alpha/kernel/sys_marvel.c

360

(irq + 16) | (io7->pe << MARVEL_IRQ_VEC_PE_SHIFT));

arch/alpha/kernel/sys_marvel.c

374

irq |= io7->pe << MARVEL_IRQ_VEC_PE_SHIFT; /* merge the pid */

arch/mips/include/asm/octeon/cvmx-mio-defs.h

3716

uint64_t pe:1;

arch/mips/include/asm/octeon/cvmx-mio-defs.h

3722

uint64_t pe:1;

arch/mips/include/asm/octeon/cvmx-mio-defs.h

4131

uint64_t pe:1;

arch/mips/include/asm/octeon/cvmx-mio-defs.h

4137

uint64_t pe:1;

arch/powerpc/include/asm/eeh.h

104

#define eeh_pe_for_each_dev(pe, edev, tmp) \

arch/powerpc/include/asm/eeh.h

105

list_for_each_entry_safe(edev, tmp, &pe->edevs, entry)

arch/powerpc/include/asm/eeh.h

107

#define eeh_for_each_pe(root, pe) \

arch/powerpc/include/asm/eeh.h

108

for (pe = root; pe; pe = eeh_pe_next(pe, root))

arch/powerpc/include/asm/eeh.h

110

static inline bool eeh_pe_passed(struct eeh_pe *pe)

arch/powerpc/include/asm/eeh.h

112

return pe ? !!atomic_read(&pe->pass_dev_cnt) : false;

arch/powerpc/include/asm/eeh.h

142

struct eeh_pe *pe; /* Associated PE */

arch/powerpc/include/asm/eeh.h

159

((edev)->pe ? (edev)->pe_config_addr : 0xffff), ##__VA_ARGS__)

arch/powerpc/include/asm/eeh.h

177

return edev ? edev->pe : NULL;

arch/powerpc/include/asm/eeh.h

218

int (*set_option)(struct eeh_pe *pe, int option);

arch/powerpc/include/asm/eeh.h

219

int (*get_state)(struct eeh_pe *pe, int *delay);

arch/powerpc/include/asm/eeh.h

220

int (*reset)(struct eeh_pe *pe, int option);

arch/powerpc/include/asm/eeh.h

221

int (*get_log)(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len);

arch/powerpc/include/asm/eeh.h

222

int (*configure_bridge)(struct eeh_pe *pe);

arch/powerpc/include/asm/eeh.h

223

int (*err_inject)(struct eeh_pe *pe, int type, int func,

arch/powerpc/include/asm/eeh.h

227

int (*next_error)(struct eeh_pe **pe);

arch/powerpc/include/asm/eeh.h

275

typedef void *(*eeh_pe_traverse_func)(struct eeh_pe *pe, void *flag);

arch/powerpc/include/asm/eeh.h

278

int eeh_wait_state(struct eeh_pe *pe, int max_wait);

arch/powerpc/include/asm/eeh.h

280

struct eeh_pe *eeh_pe_next(struct eeh_pe *pe, struct eeh_pe *root);

arch/powerpc/include/asm/eeh.h

284

void eeh_pe_update_time_stamp(struct eeh_pe *pe);

arch/powerpc/include/asm/eeh.h

289

void eeh_pe_restore_bars(struct eeh_pe *pe);

arch/powerpc/include/asm/eeh.h

290

const char *eeh_pe_loc_get(struct eeh_pe *pe);

arch/powerpc/include/asm/eeh.h

291

struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe);

arch/powerpc/include/asm/eeh.h

293

struct pci_bus *eeh_pe_bus_get_nolock(struct eeh_pe *pe);

arch/powerpc/include/asm/eeh.h

302

int eeh_unfreeze_pe(struct eeh_pe *pe);

arch/powerpc/include/asm/eeh.h

303

int eeh_pe_reset_and_recover(struct eeh_pe *pe);

arch/powerpc/include/asm/eeh.h

307

int eeh_pe_set_option(struct eeh_pe *pe, int option);

arch/powerpc/include/asm/eeh.h

308

int eeh_pe_get_state(struct eeh_pe *pe);

arch/powerpc/include/asm/eeh.h

309

int eeh_pe_reset(struct eeh_pe *pe, int option, bool include_passed);

arch/powerpc/include/asm/eeh.h

310

int eeh_pe_configure(struct eeh_pe *pe);

arch/powerpc/include/asm/eeh.h

311

int eeh_pe_inject_err(struct eeh_pe *pe, int type, int func,

arch/powerpc/include/asm/eeh_event.h

19

struct eeh_pe *pe; /* EEH PE */

arch/powerpc/include/asm/eeh_event.h

23

int eeh_send_failure_event(struct eeh_pe *pe);

arch/powerpc/include/asm/eeh_event.h

24

int __eeh_send_failure_event(struct eeh_pe *pe);

arch/powerpc/include/asm/eeh_event.h

25

void eeh_remove_event(struct eeh_pe *pe, bool force);

arch/powerpc/include/asm/eeh_event.h

26

void eeh_handle_normal_event(struct eeh_pe *pe);

arch/powerpc/include/asm/ppc-pci.h

56

void eeh_slot_error_detail(struct eeh_pe *pe, int severity);

arch/powerpc/include/asm/ppc-pci.h

57

int eeh_pci_enable(struct eeh_pe *pe, int function);

arch/powerpc/include/asm/ppc-pci.h

58

int eeh_pe_reset_full(struct eeh_pe *pe, bool include_passed);

arch/powerpc/include/asm/ppc-pci.h

60

void eeh_pe_state_mark(struct eeh_pe *pe, int state);

arch/powerpc/include/asm/ppc-pci.h

61

void eeh_pe_mark_isolated(struct eeh_pe *pe);

arch/powerpc/include/asm/ppc-pci.h

62

void eeh_pe_state_clear(struct eeh_pe *pe, int state, bool include_passed);

arch/powerpc/include/asm/ppc-pci.h

63

void eeh_pe_state_mark_with_cfg(struct eeh_pe *pe, int state);

arch/powerpc/include/asm/ppc-pci.h

64

void eeh_pe_dev_mode_mark(struct eeh_pe *pe, int mode);

arch/powerpc/kernel/eeh.c

1078

if (!edev || !edev->pdev || !edev->pe) {

arch/powerpc/kernel/eeh.c

1116

if (!(edev->pe->state & EEH_PE_KEEP))

arch/powerpc/kernel/eeh.c

1122

int eeh_unfreeze_pe(struct eeh_pe *pe)

arch/powerpc/kernel/eeh.c

1126

ret = eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);

arch/powerpc/kernel/eeh.c

1129

__func__, ret, pe->phb->global_number, pe->addr);

arch/powerpc/kernel/eeh.c

1133

ret = eeh_pci_enable(pe, EEH_OPT_THAW_DMA);

arch/powerpc/kernel/eeh.c

1136

__func__, ret, pe->phb->global_number, pe->addr);

arch/powerpc/kernel/eeh.c

1152

static int eeh_pe_change_owner(struct eeh_pe *pe)

arch/powerpc/kernel/eeh.c

1160

ret = eeh_ops->get_state(pe, NULL);

arch/powerpc/kernel/eeh.c

1169

eeh_pe_for_each_dev(pe, edev, tmp) {

arch/powerpc/kernel/eeh.c

1188

return eeh_pe_reset_and_recover(pe);

arch/powerpc/kernel/eeh.c

1192

ret = eeh_unfreeze_pe(pe);

arch/powerpc/kernel/eeh.c

1194

eeh_pe_state_clear(pe, EEH_PE_ISOLATED, true);

arch/powerpc/kernel/eeh.c

1220

if (!edev || !edev->pe)

arch/powerpc/kernel/eeh.c

1229

ret = eeh_pe_change_owner(edev->pe);

arch/powerpc/kernel/eeh.c

1234

atomic_inc(&edev->pe->pass_dev_cnt);

arch/powerpc/kernel/eeh.c

1260

if (!edev || !edev->pe || !eeh_pe_passed(edev->pe))

arch/powerpc/kernel/eeh.c

1264

WARN_ON(atomic_dec_if_positive(&edev->pe->pass_dev_cnt) < 0);

arch/powerpc/kernel/eeh.c

1265

eeh_pe_change_owner(edev->pe);

arch/powerpc/kernel/eeh.c

1293

if (!edev || !edev->pe)

arch/powerpc/kernel/eeh.c

1296

return edev->pe;

arch/powerpc/kernel/eeh.c

1310

int eeh_pe_set_option(struct eeh_pe *pe, int option)

arch/powerpc/kernel/eeh.c

1315

if (!pe)

arch/powerpc/kernel/eeh.c

1326

ret = eeh_pe_change_owner(pe);

arch/powerpc/kernel/eeh.c

1341

ret = eeh_pci_enable(pe, option);

arch/powerpc/kernel/eeh.c

1360

int eeh_pe_get_state(struct eeh_pe *pe)

arch/powerpc/kernel/eeh.c

1366

if (!pe)

arch/powerpc/kernel/eeh.c

1378

if (pe->parent &&

arch/powerpc/kernel/eeh.c

1379

!(pe->state & EEH_PE_REMOVED) &&

arch/powerpc/kernel/eeh.c

1380

(pe->parent->state & (EEH_PE_ISOLATED | EEH_PE_RECOVERING)))

arch/powerpc/kernel/eeh.c

1383

result = eeh_ops->get_state(pe, NULL);

arch/powerpc/kernel/eeh.c

1403

static int eeh_pe_reenable_devices(struct eeh_pe *pe, bool include_passed)

arch/powerpc/kernel/eeh.c

1409

eeh_pe_restore_bars(pe);

arch/powerpc/kernel/eeh.c

1415

eeh_pe_for_each_dev(pe, edev, tmp) {

arch/powerpc/kernel/eeh.c

1429

if (include_passed || !eeh_pe_passed(pe)) {

arch/powerpc/kernel/eeh.c

1430

ret = eeh_unfreeze_pe(pe);

arch/powerpc/kernel/eeh.c

1433

pe->phb->global_number, pe->addr);

arch/powerpc/kernel/eeh.c

1435

eeh_pe_state_clear(pe, EEH_PE_ISOLATED, include_passed);

arch/powerpc/kernel/eeh.c

1450

int eeh_pe_reset(struct eeh_pe *pe, int option, bool include_passed)

arch/powerpc/kernel/eeh.c

1455

if (!pe)

arch/powerpc/kernel/eeh.c

1463

ret = eeh_ops->reset(pe, option);

arch/powerpc/kernel/eeh.c

1464

eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, include_passed);

arch/powerpc/kernel/eeh.c

1468

ret = eeh_pe_reenable_devices(pe, include_passed);

arch/powerpc/kernel/eeh.c

1477

eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);

arch/powerpc/kernel/eeh.c

1479

eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);

arch/powerpc/kernel/eeh.c

1480

ret = eeh_ops->reset(pe, option);

arch/powerpc/kernel/eeh.c

1500

int eeh_pe_configure(struct eeh_pe *pe)

arch/powerpc/kernel/eeh.c

1505

if (!pe)

arch/powerpc/kernel/eeh.c

1508

ret = eeh_ops->configure_bridge(pe);

arch/powerpc/kernel/eeh.c

1526

int eeh_pe_inject_err(struct eeh_pe *pe, int type, int func,

arch/powerpc/kernel/eeh.c

1530

if (!pe)

arch/powerpc/kernel/eeh.c

1541

return eeh_ops->err_inject(pe, type, func, addr, mask);

arch/powerpc/kernel/eeh.c

1730

struct eeh_pe *pe;

arch/powerpc/kernel/eeh.c

1758

pe = eeh_pe_get(hose, pe_no);

arch/powerpc/kernel/eeh.c

1759

if (!pe)

arch/powerpc/kernel/eeh.c

176

edev->pe->phb->global_number, edev->bdfn >> 8,

arch/powerpc/kernel/eeh.c

1769

__eeh_send_failure_event(pe);

arch/powerpc/kernel/eeh.c

179

edev->pe->phb->global_number, edev->bdfn >> 8,

arch/powerpc/kernel/eeh.c

269

static void *eeh_dump_pe_log(struct eeh_pe *pe, void *flag)

arch/powerpc/kernel/eeh.c

274

eeh_pe_for_each_dev(pe, edev, tmp)

arch/powerpc/kernel/eeh.c

291

void eeh_slot_error_detail(struct eeh_pe *pe, int severity)

arch/powerpc/kernel/eeh.c

311

if (!(pe->type & EEH_PE_PHB)) {

arch/powerpc/kernel/eeh.c

314

eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);

arch/powerpc/kernel/eeh.c

328

eeh_ops->configure_bridge(pe);

arch/powerpc/kernel/eeh.c

329

if (!(pe->state & EEH_PE_CFG_BLOCKED)) {

arch/powerpc/kernel/eeh.c

330

eeh_pe_restore_bars(pe);

arch/powerpc/kernel/eeh.c

333

eeh_pe_traverse(pe, eeh_dump_pe_log, &loglen);

arch/powerpc/kernel/eeh.c

337

eeh_ops->get_log(pe, severity, pci_regs_buf, loglen);

arch/powerpc/kernel/eeh.c

357

static int eeh_phb_check_failure(struct eeh_pe *pe)

arch/powerpc/kernel/eeh.c

367

phb_pe = eeh_phb_pe_get(pe->phb);

arch/powerpc/kernel/eeh.c

370

__func__, pe->phb->global_number);

arch/powerpc/kernel/eeh.c

430

struct eeh_pe *pe, *parent_pe;

arch/powerpc/kernel/eeh.c

444

pe = eeh_dev_to_pe(edev);

arch/powerpc/kernel/eeh.c

447

if (!pe) {

arch/powerpc/kernel/eeh.c

457

ret = eeh_phb_check_failure(pe);

arch/powerpc/kernel/eeh.c

466

if (eeh_pe_passed(pe))

arch/powerpc/kernel/eeh.c

477

if (pe->state & EEH_PE_ISOLATED) {

arch/powerpc/kernel/eeh.c

478

pe->check_count++;

arch/powerpc/kernel/eeh.c

479

if (pe->check_count == EEH_MAX_FAILS) {

arch/powerpc/kernel/eeh.c

485

pe->check_count,

arch/powerpc/kernel/eeh.c

502

ret = eeh_ops->get_state(pe, NULL);

arch/powerpc/kernel/eeh.c

522

pe->false_positives++;

arch/powerpc/kernel/eeh.c

532

parent_pe = pe->parent;

arch/powerpc/kernel/eeh.c

541

pe = parent_pe;

arch/powerpc/kernel/eeh.c

543

pe->phb->global_number, pe->addr,

arch/powerpc/kernel/eeh.c

544

pe->phb->global_number, parent_pe->addr);

arch/powerpc/kernel/eeh.c

557

eeh_pe_mark_isolated(pe);

arch/powerpc/kernel/eeh.c

565

__func__, pe->phb->global_number, pe->addr);

arch/powerpc/kernel/eeh.c

566

eeh_send_failure_event(pe);

arch/powerpc/kernel/eeh.c

615

int eeh_pci_enable(struct eeh_pe *pe, int function)

arch/powerpc/kernel/eeh.c

647

rc = eeh_ops->get_state(pe, NULL);

arch/powerpc/kernel/eeh.c

662

rc = eeh_ops->set_option(pe, function);

arch/powerpc/kernel/eeh.c

666

__func__, function, pe->phb->global_number,

arch/powerpc/kernel/eeh.c

667

pe->addr, rc);

arch/powerpc/kernel/eeh.c

671

rc = eeh_wait_state(pe, PCI_BUS_RESET_WAIT_MSEC);

arch/powerpc/kernel/eeh.c

738

struct eeh_pe *pe = eeh_dev_to_pe(edev);

arch/powerpc/kernel/eeh.c

740

if (!pe) {

arch/powerpc/kernel/eeh.c

748

eeh_ops->reset(pe, EEH_RESET_DEACTIVATE);

arch/powerpc/kernel/eeh.c

749

eeh_unfreeze_pe(pe);

arch/powerpc/kernel/eeh.c

750

if (!(pe->type & EEH_PE_VF))

arch/powerpc/kernel/eeh.c

751

eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, true);

arch/powerpc/kernel/eeh.c

752

eeh_pe_dev_traverse(pe, eeh_restore_dev_state, dev);

arch/powerpc/kernel/eeh.c

753

eeh_pe_state_clear(pe, EEH_PE_ISOLATED, true);

arch/powerpc/kernel/eeh.c

756

eeh_pe_mark_isolated(pe);

arch/powerpc/kernel/eeh.c

757

eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, true);

arch/powerpc/kernel/eeh.c

758

eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);

arch/powerpc/kernel/eeh.c

759

eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev);

arch/powerpc/kernel/eeh.c

760

if (!(pe->type & EEH_PE_VF))

arch/powerpc/kernel/eeh.c

761

eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);

arch/powerpc/kernel/eeh.c

762

eeh_ops->reset(pe, EEH_RESET_HOT);

arch/powerpc/kernel/eeh.c

765

eeh_pe_mark_isolated(pe);

arch/powerpc/kernel/eeh.c

766

eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, true);

arch/powerpc/kernel/eeh.c

767

eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);

arch/powerpc/kernel/eeh.c

768

eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev);

arch/powerpc/kernel/eeh.c

769

if (!(pe->type & EEH_PE_VF))

arch/powerpc/kernel/eeh.c

770

eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);

arch/powerpc/kernel/eeh.c

771

eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL);

arch/powerpc/kernel/eeh.c

774

eeh_pe_state_clear(pe, EEH_PE_ISOLATED | EEH_PE_CFG_BLOCKED, true);

arch/powerpc/kernel/eeh.c

803

struct eeh_pe *pe;

arch/powerpc/kernel/eeh.c

806

eeh_for_each_pe(root, pe) {

arch/powerpc/kernel/eeh.c

807

if (eeh_pe_passed(pe)) {

arch/powerpc/kernel/eeh.c

808

state = eeh_ops->get_state(pe, NULL);

arch/powerpc/kernel/eeh.c

812

pe->phb->global_number, pe->addr);

arch/powerpc/kernel/eeh.c

813

eeh_pe_set_option(pe, EEH_OPT_FREEZE_PE);

arch/powerpc/kernel/eeh.c

832

int eeh_pe_reset_full(struct eeh_pe *pe, bool include_passed)

arch/powerpc/kernel/eeh.c

844

eeh_pe_dev_traverse(pe, eeh_set_dev_freset, &freset);

arch/powerpc/kernel/eeh.c

850

eeh_pe_state_mark(pe, reset_state);

arch/powerpc/kernel/eeh.c

854

ret = eeh_pe_reset(pe, type, include_passed);

arch/powerpc/kernel/eeh.c

856

ret = eeh_pe_reset(pe, EEH_RESET_DEACTIVATE,

arch/powerpc/kernel/eeh.c

861

state, pe->phb->global_number, pe->addr, i + 1);

arch/powerpc/kernel/eeh.c

866

pe->phb->global_number, pe->addr, i + 1);

arch/powerpc/kernel/eeh.c

869

state = eeh_wait_state(pe, PCI_BUS_RESET_WAIT_MSEC);

arch/powerpc/kernel/eeh.c

872

pe->phb->global_number, pe->addr);

arch/powerpc/kernel/eeh.c

880

pe->phb->global_number, pe->addr, state, i + 1);

arch/powerpc/kernel/eeh.c

887

eeh_pe_refreeze_passed(pe);

arch/powerpc/kernel/eeh.c

889

eeh_pe_state_clear(pe, reset_state, true);

arch/powerpc/kernel/eeh_cache.c

173

if (!edev->pe) {

arch/powerpc/kernel/eeh_driver.c

1002

eeh_pe_report("mmio_enabled", pe,

arch/powerpc/kernel/eeh_driver.c

1008

rc = eeh_pci_enable(pe, EEH_OPT_THAW_DMA);

arch/powerpc/kernel/eeh_driver.c

1020

eeh_pe_state_clear(pe, EEH_PE_ISOLATED, true);

arch/powerpc/kernel/eeh_driver.c

1028

rc = eeh_reset_device(pe, bus, &rmv_data, true);

arch/powerpc/kernel/eeh_driver.c

1035

eeh_set_channel_state(pe, pci_channel_io_normal);

arch/powerpc/kernel/eeh_driver.c

1036

eeh_set_irq_state(pe, true);

arch/powerpc/kernel/eeh_driver.c

1037

eeh_pe_report("slot_reset", pe, eeh_report_reset,

arch/powerpc/kernel/eeh_driver.c

1055

eeh_set_channel_state(pe, pci_channel_io_normal);

arch/powerpc/kernel/eeh_driver.c

1056

eeh_set_irq_state(pe, true);

arch/powerpc/kernel/eeh_driver.c

1057

eeh_pe_report("resume", pe, eeh_report_resume, NULL);

arch/powerpc/kernel/eeh_driver.c

1058

eeh_for_each_pe(pe, tmp_pe) {

arch/powerpc/kernel/eeh_driver.c

1077

pe->phb->global_number, pe->addr);

arch/powerpc/kernel/eeh_driver.c

1079

eeh_slot_error_detail(pe, EEH_LOG_PERM);

arch/powerpc/kernel/eeh_driver.c

1082

eeh_set_irq_state(pe, false);

arch/powerpc/kernel/eeh_driver.c

1083

eeh_pe_report("error_detected(permanent failure)", pe,

arch/powerpc/kernel/eeh_driver.c

1085

eeh_set_channel_state(pe, pci_channel_io_perm_failure);

arch/powerpc/kernel/eeh_driver.c

1088

eeh_pe_state_mark(pe, EEH_PE_REMOVED);

arch/powerpc/kernel/eeh_driver.c

1095

if (pe->type & EEH_PE_VF) {

arch/powerpc/kernel/eeh_driver.c

1096

eeh_pe_dev_traverse(pe, eeh_rmv_device, NULL);

arch/powerpc/kernel/eeh_driver.c

1097

eeh_pe_dev_mode_mark(pe, EEH_DEV_REMOVED);

arch/powerpc/kernel/eeh_driver.c

1099

eeh_pe_state_clear(pe, EEH_PE_PRI_BUS, true);

arch/powerpc/kernel/eeh_driver.c

1100

eeh_pe_dev_mode_mark(pe, EEH_DEV_REMOVED);

arch/powerpc/kernel/eeh_driver.c

1102

bus = eeh_pe_bus_get_nolock(pe);

arch/powerpc/kernel/eeh_driver.c

1107

__func__, pe->phb->global_number, pe->addr);

arch/powerpc/kernel/eeh_driver.c

1119

eeh_pe_cleanup(pe);

arch/powerpc/kernel/eeh_driver.c

1122

eeh_for_each_pe(pe, tmp_pe)

arch/powerpc/kernel/eeh_driver.c

1126

eeh_pe_state_clear(pe, EEH_PE_RECOVERING, true);

arch/powerpc/kernel/eeh_driver.c

1140

struct eeh_pe *pe, *phb_pe, *tmp_pe;

arch/powerpc/kernel/eeh_driver.c

1150

rc = eeh_ops->next_error(&pe);

arch/powerpc/kernel/eeh_driver.c

1177

eeh_remove_event(pe, true);

arch/powerpc/kernel/eeh_driver.c

1180

eeh_pe_state_mark(pe, EEH_PE_RECOVERING);

arch/powerpc/kernel/eeh_driver.c

1181

eeh_pe_mark_isolated(pe);

arch/powerpc/kernel/eeh_driver.c

1203

eeh_pe_state_mark(pe, EEH_PE_RECOVERING);

arch/powerpc/kernel/eeh_driver.c

1205

eeh_handle_normal_event(pe);

arch/powerpc/kernel/eeh_driver.c

1208

eeh_for_each_pe(pe, tmp_pe)

arch/powerpc/kernel/eeh_driver.c

1213

eeh_pe_state_clear(pe, EEH_PE_PRI_BUS, true);

arch/powerpc/kernel/eeh_driver.c

1215

"error_detected(permanent failure)", pe,

arch/powerpc/kernel/eeh_driver.c

1217

eeh_set_channel_state(pe, pci_channel_io_perm_failure);

arch/powerpc/kernel/eeh_driver.c

1231

pe->phb->global_number,

arch/powerpc/kernel/eeh_driver.c

1232

pe->addr);

arch/powerpc/kernel/eeh_driver.c

206

if (edev->pe && (edev->pe->state & EEH_PE_CFG_RESTRICTED))

arch/powerpc/kernel/eeh_driver.c

218

struct eeh_pe *pe;

arch/powerpc/kernel/eeh_driver.c

221

eeh_for_each_pe(root, pe)

arch/powerpc/kernel/eeh_driver.c

222

eeh_pe_for_each_dev(pe, edev, tmp)

arch/powerpc/kernel/eeh_driver.c

229

struct eeh_pe *pe;

arch/powerpc/kernel/eeh_driver.c

232

eeh_for_each_pe(root, pe) {

arch/powerpc/kernel/eeh_driver.c

233

eeh_pe_for_each_dev(pe, edev, tmp) {

arch/powerpc/kernel/eeh_driver.c

291

!eeh_dev_removed(edev), !eeh_pe_passed(edev->pe));

arch/powerpc/kernel/eeh_driver.c

306

eeh_for_each_pe(root, pe)

arch/powerpc/kernel/eeh_driver.c

394

if (edev->pe && (edev->pe->state & EEH_PE_CFG_RESTRICTED)) {

arch/powerpc/kernel/eeh_driver.c

395

if (list_is_last(&edev->entry, &edev->pe->edevs))

arch/powerpc/kernel/eeh_driver.c

569

eeh_for_each_pe(root, pe) {

arch/powerpc/kernel/eeh_driver.c

570

if (include_passed || !eeh_pe_passed(pe)) {

arch/powerpc/kernel/eeh_driver.c

572

if (!eeh_unfreeze_pe(pe))

arch/powerpc/kernel/eeh_driver.c

582

int eeh_pe_reset_and_recover(struct eeh_pe *pe)

arch/powerpc/kernel/eeh_driver.c

587

if (pe->state & EEH_PE_RECOVERING)

arch/powerpc/kernel/eeh_driver.c

591

eeh_pe_state_mark(pe, EEH_PE_RECOVERING);

arch/powerpc/kernel/eeh_driver.c

594

eeh_pe_dev_traverse(pe, eeh_dev_save_state, NULL);

arch/powerpc/kernel/eeh_driver.c

597

ret = eeh_pe_reset_full(pe, true);

arch/powerpc/kernel/eeh_driver.c

599

eeh_pe_state_clear(pe, EEH_PE_RECOVERING, true);

arch/powerpc/kernel/eeh_driver.c

604

ret = eeh_clear_pe_frozen_state(pe, true);

arch/powerpc/kernel/eeh_driver.c

606

eeh_pe_state_clear(pe, EEH_PE_RECOVERING, true);

arch/powerpc/kernel/eeh_driver.c

611

eeh_pe_dev_traverse(pe, eeh_dev_restore_state, NULL);

arch/powerpc/kernel/eeh_driver.c

614

eeh_pe_state_clear(pe, EEH_PE_RECOVERING, true);

arch/powerpc/kernel/eeh_driver.c

630

static int eeh_reset_device(struct eeh_pe *pe, struct pci_bus *bus,

arch/powerpc/kernel/eeh_driver.c

640

eeh_for_each_pe(pe, tmp_pe)

arch/powerpc/kernel/eeh_driver.c

644

cnt = pe->freeze_count;

arch/powerpc/kernel/eeh_driver.c

645

tstamp = pe->tstamp;

arch/powerpc/kernel/eeh_driver.c

653

eeh_pe_state_mark(pe, EEH_PE_KEEP);

arch/powerpc/kernel/eeh_driver.c

654

if (any_passed || driver_eeh_aware || (pe->type & EEH_PE_VF)) {

arch/powerpc/kernel/eeh_driver.c

655

eeh_pe_dev_traverse(pe, eeh_rmv_device, rmv_data);

arch/powerpc/kernel/eeh_driver.c

669

rc = eeh_pe_reset_full(pe, false);

arch/powerpc/kernel/eeh_driver.c

674

eeh_ops->configure_bridge(pe);

arch/powerpc/kernel/eeh_driver.c

675

eeh_pe_restore_bars(pe);

arch/powerpc/kernel/eeh_driver.c

678

rc = eeh_clear_pe_frozen_state(pe, false);

arch/powerpc/kernel/eeh_driver.c

699

edev = list_first_entry(&pe->edevs, struct eeh_dev, entry);

arch/powerpc/kernel/eeh_driver.c

700

eeh_pe_traverse(pe, eeh_pe_detach_dev, NULL);

arch/powerpc/kernel/eeh_driver.c

701

if (pe->type & EEH_PE_VF) {

arch/powerpc/kernel/eeh_driver.c

705

eeh_pe_state_clear(pe, EEH_PE_PRI_BUS, true);

arch/powerpc/kernel/eeh_driver.c

709

eeh_pe_state_clear(pe, EEH_PE_KEEP, true);

arch/powerpc/kernel/eeh_driver.c

711

pe->tstamp = tstamp;

arch/powerpc/kernel/eeh_driver.c

712

pe->freeze_count = cnt;

arch/powerpc/kernel/eeh_driver.c

730

static void eeh_pe_cleanup(struct eeh_pe *pe)

arch/powerpc/kernel/eeh_driver.c

734

list_for_each_entry_safe(child_pe, tmp, &pe->child_list, child)

arch/powerpc/kernel/eeh_driver.c

737

if (pe->state & EEH_PE_KEEP)

arch/powerpc/kernel/eeh_driver.c

740

if (!(pe->state & EEH_PE_INVALID))

arch/powerpc/kernel/eeh_driver.c

743

if (list_empty(&pe->edevs) && list_empty(&pe->child_list)) {

arch/powerpc/kernel/eeh_driver.c

744

list_del(&pe->child);

arch/powerpc/kernel/eeh_driver.c

745

kfree(pe);

arch/powerpc/kernel/eeh_driver.c

836

void eeh_handle_normal_event(struct eeh_pe *pe)

arch/powerpc/kernel/eeh_driver.c

849

bus = eeh_pe_bus_get_nolock(pe);

arch/powerpc/kernel/eeh_driver.c

852

__func__, pe->phb->global_number, pe->addr);

arch/powerpc/kernel/eeh_driver.c

866

eeh_for_each_pe(pe, tmp_pe)

arch/powerpc/kernel/eeh_driver.c

873

pe->phb->global_number, pe->addr);

arch/powerpc/kernel/eeh_driver.c

887

if (pe->type & EEH_PE_PHB) {

arch/powerpc/kernel/eeh_driver.c

889

pe->phb->global_number, eeh_pe_loc_get_bus(bus));

arch/powerpc/kernel/eeh_driver.c

89

if (eeh_pe_passed(edev->pe))

arch/powerpc/kernel/eeh_driver.c

891

struct eeh_pe *phb_pe = eeh_phb_pe_get(pe->phb);

arch/powerpc/kernel/eeh_driver.c

894

pe->phb->global_number, pe->addr);

arch/powerpc/kernel/eeh_driver.c

905

if (pe->trace_entries) {

arch/powerpc/kernel/eeh_driver.c

906

void **ptrs = (void **) pe->stack_trace;

arch/powerpc/kernel/eeh_driver.c

910

pe->phb->global_number, pe->addr);

arch/powerpc/kernel/eeh_driver.c

914

for (i = 0; i < pe->trace_entries; i++)

arch/powerpc/kernel/eeh_driver.c

917

pe->trace_entries = 0;

arch/powerpc/kernel/eeh_driver.c

921

eeh_for_each_pe(pe, tmp_pe)

arch/powerpc/kernel/eeh_driver.c

925

eeh_pe_update_time_stamp(pe);

arch/powerpc/kernel/eeh_driver.c

926

pe->freeze_count++;

arch/powerpc/kernel/eeh_driver.c

927

if (pe->freeze_count > eeh_max_freezes) {

arch/powerpc/kernel/eeh_driver.c

929

pe->phb->global_number, pe->addr,

arch/powerpc/kernel/eeh_driver.c

930

pe->freeze_count);

arch/powerpc/kernel/eeh_driver.c

946

pe->freeze_count, eeh_max_freezes);

arch/powerpc/kernel/eeh_driver.c

948

eeh_set_channel_state(pe, pci_channel_io_frozen);

arch/powerpc/kernel/eeh_driver.c

949

eeh_set_irq_state(pe, false);

arch/powerpc/kernel/eeh_driver.c

950

eeh_pe_report("error_detected(IO frozen)", pe,

arch/powerpc/kernel/eeh_driver.c

959

if ((pe->type & EEH_PE_PHB) && result != PCI_ERS_RESULT_NONE)

arch/powerpc/kernel/eeh_driver.c

965

rc = eeh_wait_state(pe, MAX_WAIT_FOR_RECOVERY * 1000);

arch/powerpc/kernel/eeh_driver.c

976

eeh_slot_error_detail(pe, EEH_LOG_TEMP);

arch/powerpc/kernel/eeh_driver.c

984

rc = eeh_reset_device(pe, bus, NULL, false);

arch/powerpc/kernel/eeh_driver.c

994

rc = eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);

arch/powerpc/kernel/eeh_event.c

102

int __eeh_send_failure_event(struct eeh_pe *pe)

arch/powerpc/kernel/eeh_event.c

112

event->pe = pe;

arch/powerpc/kernel/eeh_event.c

119

if (pe) {

arch/powerpc/kernel/eeh_event.c

125

pe->trace_entries = stack_trace_save(pe->stack_trace,

arch/powerpc/kernel/eeh_event.c

126

ARRAY_SIZE(pe->stack_trace), 0);

arch/powerpc/kernel/eeh_event.c

129

eeh_pe_state_mark(pe, EEH_PE_RECOVERING);

arch/powerpc/kernel/eeh_event.c

143

int eeh_send_failure_event(struct eeh_pe *pe)

arch/powerpc/kernel/eeh_event.c

154

return __eeh_send_failure_event(pe);

arch/powerpc/kernel/eeh_event.c

167

void eeh_remove_event(struct eeh_pe *pe, bool force)

arch/powerpc/kernel/eeh_event.c

183

if (!force && event->pe &&

arch/powerpc/kernel/eeh_event.c

184

(event->pe->state & EEH_PE_ISOLATED))

arch/powerpc/kernel/eeh_event.c

187

if (!pe) {

arch/powerpc/kernel/eeh_event.c

190

} else if (pe->type & EEH_PE_PHB) {

arch/powerpc/kernel/eeh_event.c

191

if (event->pe && event->pe->phb == pe->phb) {

arch/powerpc/kernel/eeh_event.c

195

} else if (event->pe == pe) {

arch/powerpc/kernel/eeh_event.c

61

if (event->pe)

arch/powerpc/kernel/eeh_event.c

62

eeh_handle_normal_event(event->pe);

arch/powerpc/kernel/eeh_pe.c

107

int eeh_wait_state(struct eeh_pe *pe, int max_wait)

arch/powerpc/kernel/eeh_pe.c

124

ret = eeh_ops->get_state(pe, &mwait);

arch/powerpc/kernel/eeh_pe.c

160

struct eeh_pe *pe;

arch/powerpc/kernel/eeh_pe.c

162

list_for_each_entry(pe, &eeh_phb_pe, child) {

arch/powerpc/kernel/eeh_pe.c

168

if ((pe->type & EEH_PE_PHB) && pe->phb == phb)

arch/powerpc/kernel/eeh_pe.c

169

return pe;

arch/powerpc/kernel/eeh_pe.c

183

struct eeh_pe *eeh_pe_next(struct eeh_pe *pe, struct eeh_pe *root)

arch/powerpc/kernel/eeh_pe.c

185

struct list_head *next = pe->child_list.next;

arch/powerpc/kernel/eeh_pe.c

187

if (next == &pe->child_list) {

arch/powerpc/kernel/eeh_pe.c

189

if (pe == root)

arch/powerpc/kernel/eeh_pe.c

191

next = pe->child.next;

arch/powerpc/kernel/eeh_pe.c

192

if (next != &pe->parent->child_list)

arch/powerpc/kernel/eeh_pe.c

194

pe = pe->parent;

arch/powerpc/kernel/eeh_pe.c

215

struct eeh_pe *pe;

arch/powerpc/kernel/eeh_pe.c

218

eeh_for_each_pe(root, pe) {

arch/powerpc/kernel/eeh_pe.c

219

ret = fn(pe, flag);

arch/powerpc/kernel/eeh_pe.c

238

struct eeh_pe *pe;

arch/powerpc/kernel/eeh_pe.c

248

eeh_for_each_pe(root, pe)

arch/powerpc/kernel/eeh_pe.c

249

eeh_pe_for_each_dev(pe, edev, tmp)

arch/powerpc/kernel/eeh_pe.c

261

static void *__eeh_pe_get(struct eeh_pe *pe, void *flag)

arch/powerpc/kernel/eeh_pe.c

266

if (pe->type & EEH_PE_PHB)

arch/powerpc/kernel/eeh_pe.c

269

if (*target_pe == pe->addr)

arch/powerpc/kernel/eeh_pe.c

270

return pe;

arch/powerpc/kernel/eeh_pe.c

310

struct eeh_pe *pe, *parent;

arch/powerpc/kernel/eeh_pe.c

318

pe = eeh_pe_get(hose, edev->pe_config_addr);

arch/powerpc/kernel/eeh_pe.c

319

if (pe) {

arch/powerpc/kernel/eeh_pe.c

320

if (pe->type & EEH_PE_INVALID) {

arch/powerpc/kernel/eeh_pe.c

321

list_add_tail(&edev->entry, &pe->edevs);

arch/powerpc/kernel/eeh_pe.c

322

edev->pe = pe;

arch/powerpc/kernel/eeh_pe.c

327

parent = pe;

arch/powerpc/kernel/eeh_pe.c

336

pe->parent->addr);

arch/powerpc/kernel/eeh_pe.c

339

pe->type = EEH_PE_BUS;

arch/powerpc/kernel/eeh_pe.c

340

edev->pe = pe;

arch/powerpc/kernel/eeh_pe.c

343

list_add_tail(&edev->entry, &pe->edevs);

arch/powerpc/kernel/eeh_pe.c

351

pe = eeh_pe_alloc(hose, EEH_PE_VF);

arch/powerpc/kernel/eeh_pe.c

353

pe = eeh_pe_alloc(hose, EEH_PE_DEVICE);

arch/powerpc/kernel/eeh_pe.c

354

if (!pe) {

arch/powerpc/kernel/eeh_pe.c

359

pe->addr = edev->pe_config_addr;

arch/powerpc/kernel/eeh_pe.c

372

edev->pe = NULL;

arch/powerpc/kernel/eeh_pe.c

373

kfree(pe);

arch/powerpc/kernel/eeh_pe.c

379

pe->parent = new_pe_parent;

arch/powerpc/kernel/eeh_pe.c

380

list_add_tail(&pe->child, &new_pe_parent->child_list);

arch/powerpc/kernel/eeh_pe.c

386

list_add_tail(&edev->entry, &pe->edevs);

arch/powerpc/kernel/eeh_pe.c

387

edev->pe = pe;

arch/powerpc/kernel/eeh_pe.c

405

struct eeh_pe *pe, *parent, *child;

arch/powerpc/kernel/eeh_pe.c

409

pe = eeh_dev_to_pe(edev);

arch/powerpc/kernel/eeh_pe.c

410

if (!pe) {

arch/powerpc/kernel/eeh_pe.c

416

edev->pe = NULL;

arch/powerpc/kernel/eeh_pe.c

426

parent = pe->parent;

arch/powerpc/kernel/eeh_pe.c

429

if (pe->type & EEH_PE_PHB)

arch/powerpc/kernel/eeh_pe.c

437

keep = !!(pe->state & EEH_PE_KEEP);

arch/powerpc/kernel/eeh_pe.c

438

recover = !!(pe->state & EEH_PE_RECOVERING);

arch/powerpc/kernel/eeh_pe.c

442

if (list_empty(&pe->edevs) &&

arch/powerpc/kernel/eeh_pe.c

443

list_empty(&pe->child_list)) {

arch/powerpc/kernel/eeh_pe.c

444

list_del(&pe->child);

arch/powerpc/kernel/eeh_pe.c

445

kfree(pe);

arch/powerpc/kernel/eeh_pe.c

459

if (list_empty(&pe->edevs)) {

arch/powerpc/kernel/eeh_pe.c

461

list_for_each_entry(child, &pe->child_list, child) {

arch/powerpc/kernel/eeh_pe.c

469

pe->type |= EEH_PE_INVALID;

arch/powerpc/kernel/eeh_pe.c

475

pe = parent;

arch/powerpc/kernel/eeh_pe.c

49

struct eeh_pe *pe;

arch/powerpc/kernel/eeh_pe.c

490

void eeh_pe_update_time_stamp(struct eeh_pe *pe)

arch/powerpc/kernel/eeh_pe.c

494

if (!pe) return;

arch/powerpc/kernel/eeh_pe.c

496

if (pe->freeze_count <= 0) {

arch/powerpc/kernel/eeh_pe.c

497

pe->freeze_count = 0;

arch/powerpc/kernel/eeh_pe.c

498

pe->tstamp = ktime_get_seconds();

arch/powerpc/kernel/eeh_pe.c

501

if (tstamp - pe->tstamp > 3600) {

arch/powerpc/kernel/eeh_pe.c

502

pe->tstamp = tstamp;

arch/powerpc/kernel/eeh_pe.c

503

pe->freeze_count = 0;

arch/powerpc/kernel/eeh_pe.c

518

struct eeh_pe *pe;

arch/powerpc/kernel/eeh_pe.c

520

eeh_for_each_pe(root, pe)

arch/powerpc/kernel/eeh_pe.c

521

if (!(pe->state & EEH_PE_REMOVED))

arch/powerpc/kernel/eeh_pe.c

522

pe->state |= state;

arch/powerpc/kernel/eeh_pe.c

536

struct eeh_pe *pe;

arch/powerpc/kernel/eeh_pe.c

541

eeh_for_each_pe(root, pe) {

arch/powerpc/kernel/eeh_pe.c

542

list_for_each_entry(edev, &pe->edevs, entry) {

arch/powerpc/kernel/eeh_pe.c

548

if (pe->state & EEH_PE_CFG_RESTRICTED)

arch/powerpc/kernel/eeh_pe.c

549

pe->state |= EEH_PE_CFG_BLOCKED;

arch/powerpc/kernel/eeh_pe.c

567

void eeh_pe_dev_mode_mark(struct eeh_pe *pe, int mode)

arch/powerpc/kernel/eeh_pe.c

569

eeh_pe_dev_traverse(pe, __eeh_pe_dev_mode_mark, &mode);

arch/powerpc/kernel/eeh_pe.c

584

struct eeh_pe *pe;

arch/powerpc/kernel/eeh_pe.c

588

eeh_for_each_pe(root, pe) {

arch/powerpc/kernel/eeh_pe.c

59

pe = kzalloc(alloc_size, GFP_KERNEL);

arch/powerpc/kernel/eeh_pe.c

590

if (pe->state & EEH_PE_REMOVED)

arch/powerpc/kernel/eeh_pe.c

593

if (!include_passed && eeh_pe_passed(pe))

arch/powerpc/kernel/eeh_pe.c

596

pe->state &= ~state;

arch/powerpc/kernel/eeh_pe.c

60

if (!pe) return NULL;

arch/powerpc/kernel/eeh_pe.c

606

pe->check_count = 0;

arch/powerpc/kernel/eeh_pe.c

607

eeh_pe_for_each_dev(pe, edev, tmp) {

arch/powerpc/kernel/eeh_pe.c

616

if (pe->state & EEH_PE_CFG_RESTRICTED)

arch/powerpc/kernel/eeh_pe.c

617

pe->state &= ~EEH_PE_CFG_BLOCKED;

arch/powerpc/kernel/eeh_pe.c

63

pe->type = type;

arch/powerpc/kernel/eeh_pe.c

64

pe->phb = phb;

arch/powerpc/kernel/eeh_pe.c

65

INIT_LIST_HEAD(&pe->child_list);

arch/powerpc/kernel/eeh_pe.c

66

INIT_LIST_HEAD(&pe->edevs);

arch/powerpc/kernel/eeh_pe.c

68

pe->data = (void *)pe + ALIGN(sizeof(struct eeh_pe),

arch/powerpc/kernel/eeh_pe.c

70

return pe;

arch/powerpc/kernel/eeh_pe.c

794

void eeh_pe_restore_bars(struct eeh_pe *pe)

arch/powerpc/kernel/eeh_pe.c

800

eeh_pe_dev_traverse(pe, eeh_restore_one_device_bars, NULL);

arch/powerpc/kernel/eeh_pe.c

812

const char *eeh_pe_loc_get(struct eeh_pe *pe)

arch/powerpc/kernel/eeh_pe.c

814

struct pci_bus *bus = eeh_pe_bus_get(pe);

arch/powerpc/kernel/eeh_pe.c

82

struct eeh_pe *pe;

arch/powerpc/kernel/eeh_pe.c

85

pe = eeh_pe_alloc(phb, EEH_PE_PHB);

arch/powerpc/kernel/eeh_pe.c

86

if (!pe) {

arch/powerpc/kernel/eeh_pe.c

869

static struct pci_bus *_eeh_pe_bus_get(struct eeh_pe *pe, bool do_lock)

arch/powerpc/kernel/eeh_pe.c

875

if (pe->type & EEH_PE_PHB)

arch/powerpc/kernel/eeh_pe.c

876

return pe->phb->bus;

arch/powerpc/kernel/eeh_pe.c

879

if (pe->state & EEH_PE_PRI_BUS)

arch/powerpc/kernel/eeh_pe.c

880

return pe->bus;

arch/powerpc/kernel/eeh_pe.c

883

edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, entry);

arch/powerpc/kernel/eeh_pe.c

911

struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe)

arch/powerpc/kernel/eeh_pe.c

913

return _eeh_pe_bus_get(pe, true);

arch/powerpc/kernel/eeh_pe.c

92

list_add_tail(&pe->child, &eeh_phb_pe);

arch/powerpc/kernel/eeh_pe.c

935

struct pci_bus *eeh_pe_bus_get_nolock(struct eeh_pe *pe)

arch/powerpc/kernel/eeh_pe.c

937

return _eeh_pe_bus_get(pe, false);

arch/powerpc/kernel/eeh_sysfs.c

100

if (!edev || !edev->pe || !eeh_ops->notify_resume)

arch/powerpc/kernel/eeh_sysfs.c

48

if (!edev || !edev->pe)

arch/powerpc/kernel/eeh_sysfs.c

51

state = eeh_ops->get_state(edev->pe, NULL);

arch/powerpc/kernel/eeh_sysfs.c

53

state, edev->pe->state);

arch/powerpc/kernel/eeh_sysfs.c

63

if (!edev || !edev->pe)

arch/powerpc/kernel/eeh_sysfs.c

67

if (!(edev->pe->state & EEH_PE_ISOLATED))

arch/powerpc/kernel/eeh_sysfs.c

70

if (eeh_unfreeze_pe(edev->pe))

arch/powerpc/kernel/eeh_sysfs.c

72

eeh_pe_state_clear(edev->pe, EEH_PE_ISOLATED, true);

arch/powerpc/kernel/eeh_sysfs.c

87

if (!edev || !edev->pe)

arch/powerpc/kernel/pci_dn.c

265

if (edev->pe)

arch/powerpc/kernel/rtas_pci.c

108

if (pdn->edev && pdn->edev->pe &&

arch/powerpc/kernel/rtas_pci.c

109

(pdn->edev->pe->state & EEH_PE_CFG_BLOCKED))

arch/powerpc/kernel/rtas_pci.c

57

if (pdn->edev && pdn->edev->pe &&

arch/powerpc/kernel/rtas_pci.c

58

(pdn->edev->pe->state & EEH_PE_CFG_BLOCKED))

arch/powerpc/platforms/powernv/eeh-powernv.c

1002

static int pnv_eeh_reset_vf_pe(struct eeh_pe *pe, int option)

arch/powerpc/platforms/powernv/eeh-powernv.c

1009

edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, entry);

arch/powerpc/platforms/powernv/eeh-powernv.c

1033

static int pnv_eeh_reset(struct eeh_pe *pe, int option)

arch/powerpc/platforms/powernv/eeh-powernv.c

1035

struct pci_controller *hose = pe->phb;

arch/powerpc/platforms/powernv/eeh-powernv.c

1054

if (pe->type & EEH_PE_PHB)

arch/powerpc/platforms/powernv/eeh-powernv.c

1078

if (pe->type & EEH_PE_VF)

arch/powerpc/platforms/powernv/eeh-powernv.c

1079

return pnv_eeh_reset_vf_pe(pe, option);

arch/powerpc/platforms/powernv/eeh-powernv.c

1081

bus = eeh_pe_bus_get(pe);

arch/powerpc/platforms/powernv/eeh-powernv.c

1084

__func__, pe->phb->global_number, pe->addr);

arch/powerpc/platforms/powernv/eeh-powernv.c

1131

static int pnv_eeh_get_log(struct eeh_pe *pe, int severity,

arch/powerpc/platforms/powernv/eeh-powernv.c

1135

pnv_pci_dump_phb_diag_data(pe->phb, pe->data);

arch/powerpc/platforms/powernv/eeh-powernv.c

1148

static int pnv_eeh_configure_bridge(struct eeh_pe *pe)

arch/powerpc/platforms/powernv/eeh-powernv.c

1165

static int pnv_eeh_err_inject(struct eeh_pe *pe, int type, int func,

arch/powerpc/platforms/powernv/eeh-powernv.c

1168

struct pci_controller *hose = pe->phb;

arch/powerpc/platforms/powernv/eeh-powernv.c

1194

rc = opal_pci_err_inject(phb->opal_id, pe->addr,

arch/powerpc/platforms/powernv/eeh-powernv.c

1200

hose->global_number, pe->addr);

arch/powerpc/platforms/powernv/eeh-powernv.c

1211

if (!edev || !edev->pe)

arch/powerpc/platforms/powernv/eeh-powernv.c

1219

if (edev->physfn && (edev->pe->state & EEH_PE_RESET))

arch/powerpc/platforms/powernv/eeh-powernv.c

1222

if (edev->pe->state & EEH_PE_CFG_BLOCKED)

arch/powerpc/platforms/powernv/eeh-powernv.c

1340

u16 pe_no, struct eeh_pe **pe)

arch/powerpc/platforms/powernv/eeh-powernv.c

1365

*pe = dev_pe;

arch/powerpc/platforms/powernv/eeh-powernv.c

1384

*pe = dev_pe;

arch/powerpc/platforms/powernv/eeh-powernv.c

1405

static int pnv_eeh_next_error(struct eeh_pe **pe)

arch/powerpc/platforms/powernv/eeh-powernv.c

1473

*pe = phb_pe;

arch/powerpc/platforms/powernv/eeh-powernv.c

1481

*pe = phb_pe;

arch/powerpc/platforms/powernv/eeh-powernv.c

1504

be64_to_cpu(frozen_pe_no), pe)) {

arch/powerpc/platforms/powernv/eeh-powernv.c

1522

} else if ((*pe)->state & EEH_PE_ISOLATED ||

arch/powerpc/platforms/powernv/eeh-powernv.c

1523

eeh_pe_passed(*pe)) {

arch/powerpc/platforms/powernv/eeh-powernv.c

1528

(*pe)->addr,

arch/powerpc/platforms/powernv/eeh-powernv.c

1529

(*pe)->phb->global_number);

arch/powerpc/platforms/powernv/eeh-powernv.c

1532

eeh_pe_loc_get(*pe),

arch/powerpc/platforms/powernv/eeh-powernv.c

1552

!((*pe)->state & EEH_PE_ISOLATED)) {

arch/powerpc/platforms/powernv/eeh-powernv.c

1553

eeh_pe_mark_isolated(*pe);

arch/powerpc/platforms/powernv/eeh-powernv.c

1554

pnv_eeh_get_phb_diag(*pe);

arch/powerpc/platforms/powernv/eeh-powernv.c

1557

pnv_pci_dump_phb_diag_data((*pe)->phb,

arch/powerpc/platforms/powernv/eeh-powernv.c

1558

(*pe)->data);

arch/powerpc/platforms/powernv/eeh-powernv.c

1566

parent_pe = (*pe)->parent;

arch/powerpc/platforms/powernv/eeh-powernv.c

1575

*pe = parent_pe;

arch/powerpc/platforms/powernv/eeh-powernv.c

1582

eeh_pe_mark_isolated(*pe);

arch/powerpc/platforms/powernv/eeh-powernv.c

338

if (!edev || edev->pe)

arch/powerpc/platforms/powernv/eeh-powernv.c

411

edev->pe->state |= EEH_PE_CFG_RESTRICTED;

arch/powerpc/platforms/powernv/eeh-powernv.c

419

if (!(edev->pe->state & EEH_PE_PRI_BUS)) {

arch/powerpc/platforms/powernv/eeh-powernv.c

420

edev->pe->bus = pci_find_bus(hose->global_number,

arch/powerpc/platforms/powernv/eeh-powernv.c

422

if (edev->pe->bus)

arch/powerpc/platforms/powernv/eeh-powernv.c

423

edev->pe->state |= EEH_PE_PRI_BUS;

arch/powerpc/platforms/powernv/eeh-powernv.c

453

static int pnv_eeh_set_option(struct eeh_pe *pe, int option)

arch/powerpc/platforms/powernv/eeh-powernv.c

455

struct pci_controller *hose = pe->phb;

arch/powerpc/platforms/powernv/eeh-powernv.c

484

phb->freeze_pe(phb, pe->addr);

arch/powerpc/platforms/powernv/eeh-powernv.c

488

rc = opal_pci_eeh_freeze_set(phb->opal_id, pe->addr, opt);

arch/powerpc/platforms/powernv/eeh-powernv.c

492

pe->addr);

arch/powerpc/platforms/powernv/eeh-powernv.c

501

return phb->unfreeze_pe(phb, pe->addr, opt);

arch/powerpc/platforms/powernv/eeh-powernv.c

503

rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe->addr, opt);

arch/powerpc/platforms/powernv/eeh-powernv.c

507

pe->addr);

arch/powerpc/platforms/powernv/eeh-powernv.c

514

static void pnv_eeh_get_phb_diag(struct eeh_pe *pe)

arch/powerpc/platforms/powernv/eeh-powernv.c

516

struct pnv_phb *phb = pe->phb->private_data;

arch/powerpc/platforms/powernv/eeh-powernv.c

519

rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data,

arch/powerpc/platforms/powernv/eeh-powernv.c

523

__func__, rc, pe->phb->global_number);

arch/powerpc/platforms/powernv/eeh-powernv.c

526

static int pnv_eeh_get_phb_state(struct eeh_pe *pe)

arch/powerpc/platforms/powernv/eeh-powernv.c

528

struct pnv_phb *phb = pe->phb->private_data;

arch/powerpc/platforms/powernv/eeh-powernv.c

535

pe->addr,

arch/powerpc/platforms/powernv/eeh-powernv.c

554

} else if (!(pe->state & EEH_PE_ISOLATED)) {

arch/powerpc/platforms/powernv/eeh-powernv.c

555

eeh_pe_mark_isolated(pe);

arch/powerpc/platforms/powernv/eeh-powernv.c

556

pnv_eeh_get_phb_diag(pe);

arch/powerpc/platforms/powernv/eeh-powernv.c

559

pnv_pci_dump_phb_diag_data(pe->phb, pe->data);

arch/powerpc/platforms/powernv/eeh-powernv.c

565

static int pnv_eeh_get_pe_state(struct eeh_pe *pe)

arch/powerpc/platforms/powernv/eeh-powernv.c

567

struct pnv_phb *phb = pe->phb->private_data;

arch/powerpc/platforms/powernv/eeh-powernv.c

579

if (pe->state & EEH_PE_RESET) {

arch/powerpc/platforms/powernv/eeh-powernv.c

592

fstate = phb->get_pe_state(phb, pe->addr);

arch/powerpc/platforms/powernv/eeh-powernv.c

595

pe->addr,

arch/powerpc/platforms/powernv/eeh-powernv.c

602

pe->addr);

arch/powerpc/platforms/powernv/eeh-powernv.c

639

pe->addr, fstate);

arch/powerpc/platforms/powernv/eeh-powernv.c

653

!(pe->state & EEH_PE_ISOLATED)) {

arch/powerpc/platforms/powernv/eeh-powernv.c

655

phb->freeze_pe(phb, pe->addr);

arch/powerpc/platforms/powernv/eeh-powernv.c

657

eeh_pe_mark_isolated(pe);

arch/powerpc/platforms/powernv/eeh-powernv.c

658

pnv_eeh_get_phb_diag(pe);

arch/powerpc/platforms/powernv/eeh-powernv.c

661

pnv_pci_dump_phb_diag_data(pe->phb, pe->data);

arch/powerpc/platforms/powernv/eeh-powernv.c

677

static int pnv_eeh_get_state(struct eeh_pe *pe, int *delay)

arch/powerpc/platforms/powernv/eeh-powernv.c

681

if (pe->type & EEH_PE_PHB)

arch/powerpc/platforms/powernv/eeh-powernv.c

682

ret = pnv_eeh_get_phb_state(pe);

arch/powerpc/platforms/powernv/eeh-powernv.c

684

ret = pnv_eeh_get_pe_state(pe);

arch/powerpc/platforms/powernv/eeh-powernv.c

70

struct eeh_pe *pe;

arch/powerpc/platforms/powernv/eeh-powernv.c

91

pe = eeh_pe_get(hose, pe_no);

arch/powerpc/platforms/powernv/eeh-powernv.c

92

if (!pe)

arch/powerpc/platforms/powernv/eeh-powernv.c

96

ret = eeh_ops->err_inject(pe, type, func, addr, mask);

arch/powerpc/platforms/powernv/pci-ioda.c

1005

pe = pnv_pci_bdfn_to_pe(phb, pci_dev_id(pdev));

arch/powerpc/platforms/powernv/pci-ioda.c

1006

pci_info(pdev, "Configured PE#%x\n", pe ? pe->pe_number : 0xfffff);

arch/powerpc/platforms/powernv/pci-ioda.c

1013

if (WARN_ON(!pe))

arch/powerpc/platforms/powernv/pci-ioda.c

1016

pci_info(pdev, "Added to existing PE#%x\n", pe->pe_number);

arch/powerpc/platforms/powernv/pci-ioda.c

1023

if (!pe->dma_setup_done && !pci_is_bridge(pdev)) {

arch/powerpc/platforms/powernv/pci-ioda.c

1026

pnv_pci_ioda2_setup_dma_pe(phb, pe);

arch/powerpc/platforms/powernv/pci-ioda.c

1035

pdn->pe_number = pe->pe_number;

arch/powerpc/platforms/powernv/pci-ioda.c

1036

pe->device_count++;

arch/powerpc/platforms/powernv/pci-ioda.c

1039

pdev->dev.archdata.dma_offset = pe->tce_bypass_base;

arch/powerpc/platforms/powernv/pci-ioda.c

1040

set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);

arch/powerpc/platforms/powernv/pci-ioda.c

1043

if (pe->table_group.group)

arch/powerpc/platforms/powernv/pci-ioda.c

1044

iommu_add_device(&pe->table_group, &pdev->dev);

arch/powerpc/platforms/powernv/pci-ioda.c

1064

static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe)

arch/powerpc/platforms/powernv/pci-ioda.c

1083

table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL,

arch/powerpc/platforms/powernv/pci-ioda.c

1099

rc = opal_pci_map_pe_dma_window(pe->phb->opal_id,

arch/powerpc/platforms/powernv/pci-ioda.c

1100

pe->pe_number,

arch/powerpc/platforms/powernv/pci-ioda.c

1102

(pe->pe_number << 1) + 0,

arch/powerpc/platforms/powernv/pci-ioda.c

1108

pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n");

arch/powerpc/platforms/powernv/pci-ioda.c

1112

pe_err(pe, "Error configuring 64-bit DMA bypass\n");

arch/powerpc/platforms/powernv/pci-ioda.c

1121

struct pnv_ioda_pe *pe;

arch/powerpc/platforms/powernv/pci-ioda.c

1126

pe = &phb->ioda.pe_array[pdn->pe_number];

arch/powerpc/platforms/powernv/pci-ioda.c

1127

if (pe->tce_bypass_enabled) {

arch/powerpc/platforms/powernv/pci-ioda.c

1128

u64 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;

arch/powerpc/platforms/powernv/pci-ioda.c

1142

(pe->device_count == 1 || !pe->pbus) &&

arch/powerpc/platforms/powernv/pci-ioda.c

1145

s64 rc = pnv_pci_ioda_dma_64bit_bypass(pe);

arch/powerpc/platforms/powernv/pci-ioda.c

1174

static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe)

arch/powerpc/platforms/powernv/pci-ioda.c

1177

__be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb);

arch/powerpc/platforms/powernv/pci-ioda.c

1178

unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF);

arch/powerpc/platforms/powernv/pci-ioda.c

1184

static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe,

arch/powerpc/platforms/powernv/pci-ioda.c

1188

__be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb);

arch/powerpc/platforms/powernv/pci-ioda.c

1193

start |= (pe->pe_number & 0xFF);

arch/powerpc/platforms/powernv/pci-ioda.c

1208

static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe)

arch/powerpc/platforms/powernv/pci-ioda.c

1210

struct pnv_phb *phb = pe->phb;

arch/powerpc/platforms/powernv/pci-ioda.c

1213

pnv_pci_phb3_tce_invalidate_pe(pe);

arch/powerpc/platforms/powernv/pci-ioda.c

1216

pe->pe_number, 0, 0, 0);

arch/powerpc/platforms/powernv/pci-ioda.c

1225

struct pnv_ioda_pe *pe = container_of(tgl->table_group,

arch/powerpc/platforms/powernv/pci-ioda.c

1227

struct pnv_phb *phb = pe->phb;

arch/powerpc/platforms/powernv/pci-ioda.c

1231

pnv_pci_phb3_tce_invalidate(pe, shift,

arch/powerpc/platforms/powernv/pci-ioda.c

1236

pe->pe_number, 1u << shift,

arch/powerpc/platforms/powernv/pci-ioda.c

1278

struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,

arch/powerpc/platforms/powernv/pci-ioda.c

1280

struct pnv_phb *phb = pe->phb;

arch/powerpc/platforms/powernv/pci-ioda.c

1287

pe_info(pe, "Setting up window#%d %llx..%llx pg=%lx\n",

arch/powerpc/platforms/powernv/pci-ioda.c

1296

pe->pe_number,

arch/powerpc/platforms/powernv/pci-ioda.c

1297

(pe->pe_number << 1) + num,

arch/powerpc/platforms/powernv/pci-ioda.c

1303

pe_err(pe, "Failed to configure TCE table, err %lld\n", rc);

arch/powerpc/platforms/powernv/pci-ioda.c

1308

tbl, &pe->table_group);

arch/powerpc/platforms/powernv/pci-ioda.c

1309

pnv_pci_ioda2_tce_invalidate_pe(pe);

arch/powerpc/platforms/powernv/pci-ioda.c

1314

static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)

arch/powerpc/platforms/powernv/pci-ioda.c

1316

uint16_t window_id = (pe->pe_number << 1 ) + 1;

arch/powerpc/platforms/powernv/pci-ioda.c

1319

pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");

arch/powerpc/platforms/powernv/pci-ioda.c

1324

rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,

arch/powerpc/platforms/powernv/pci-ioda.c

1325

pe->pe_number,

arch/powerpc/platforms/powernv/pci-ioda.c

1327

pe->tce_bypass_base,

arch/powerpc/platforms/powernv/pci-ioda.c

1330

rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,

arch/powerpc/platforms/powernv/pci-ioda.c

1331

pe->pe_number,

arch/powerpc/platforms/powernv/pci-ioda.c

1333

pe->tce_bypass_base,

arch/powerpc/platforms/powernv/pci-ioda.c

1337

pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);

arch/powerpc/platforms/powernv/pci-ioda.c

1339

pe->tce_bypass_enabled = enable;

arch/powerpc/platforms/powernv/pci-ioda.c

1346

struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,

arch/powerpc/platforms/powernv/pci-ioda.c

1348

int nid = pe->phb->hose->node;

arch/powerpc/platforms/powernv/pci-ioda.c

1349

__u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;

arch/powerpc/platforms/powernv/pci-ioda.c

1372

static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)

arch/powerpc/platforms/powernv/pci-ioda.c

1414

rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, PAGE_SHIFT,

arch/powerpc/platforms/powernv/pci-ioda.c

1417

pe_err(pe, "Failed to create 32-bit TCE table, err %ld",

arch/powerpc/platforms/powernv/pci-ioda.c

1425

if (window_size > pe->phb->ioda.m32_pci_base) {

arch/powerpc/platforms/powernv/pci-ioda.c

1426

res_start = pe->phb->ioda.m32_pci_base >> tbl->it_page_shift;

arch/powerpc/platforms/powernv/pci-ioda.c

1430

tbl->it_index = (pe->phb->hose->global_number << 16) | pe->pe_number;

arch/powerpc/platforms/powernv/pci-ioda.c

1431

if (iommu_init_table(tbl, pe->phb->hose->node, res_start, res_end))

arch/powerpc/platforms/powernv/pci-ioda.c

1432

rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);

arch/powerpc/platforms/powernv/pci-ioda.c

1436

pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", rc);

arch/powerpc/platforms/powernv/pci-ioda.c

1441

pnv_pci_ioda2_set_bypass(pe, true);

arch/powerpc/platforms/powernv/pci-ioda.c

1448

if (pe->pdev)

arch/powerpc/platforms/powernv/pci-ioda.c

1449

set_iommu_table_base(&pe->pdev->dev, tbl);

arch/powerpc/platforms/powernv/pci-ioda.c

1457

struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,

arch/powerpc/platforms/powernv/pci-ioda.c

1459

struct pnv_phb *phb = pe->phb;

arch/powerpc/platforms/powernv/pci-ioda.c

1462

pe_info(pe, "Removing DMA window #%d\n", num);

arch/powerpc/platforms/powernv/pci-ioda.c

1464

ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,

arch/powerpc/platforms/powernv/pci-ioda.c

1465

(pe->pe_number << 1) + num,

arch/powerpc/platforms/powernv/pci-ioda.c

1469

pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);

arch/powerpc/platforms/powernv/pci-ioda.c

1471

pnv_pci_ioda2_tce_invalidate_pe(pe);

arch/powerpc/platforms/powernv/pci-ioda.c

1525

static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus)

arch/powerpc/platforms/powernv/pci-ioda.c

1530

set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);

arch/powerpc/platforms/powernv/pci-ioda.c

1531

dev->dev.archdata.dma_offset = pe->tce_bypass_base;

arch/powerpc/platforms/powernv/pci-ioda.c

1533

if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)

arch/powerpc/platforms/powernv/pci-ioda.c

1534

pnv_ioda_setup_bus_dma(pe, dev->subordinate);

arch/powerpc/platforms/powernv/pci-ioda.c

1541

struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,

arch/powerpc/platforms/powernv/pci-ioda.c

1544

struct iommu_table *tbl = pe->table_group.tables[0];

arch/powerpc/platforms/powernv/pci-ioda.c

1553

pnv_pci_ioda2_set_bypass(pe, false);

arch/powerpc/platforms/powernv/pci-ioda.c

1554

pnv_pci_ioda2_unset_window(&pe->table_group, 0);

arch/powerpc/platforms/powernv/pci-ioda.c

1555

if (pe->pbus)

arch/powerpc/platforms/powernv/pci-ioda.c

1556

pnv_ioda_setup_bus_dma(pe, pe->pbus);

arch/powerpc/platforms/powernv/pci-ioda.c

1557

else if (pe->pdev)

arch/powerpc/platforms/powernv/pci-ioda.c

1558

set_iommu_table_base(&pe->pdev->dev, NULL);

arch/powerpc/platforms/powernv/pci-ioda.c

156

int run = 0, pe, i;

arch/powerpc/platforms/powernv/pci-ioda.c

1567

struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,

arch/powerpc/platforms/powernv/pci-ioda.c

1571

if (pe->table_group.tables[0])

arch/powerpc/platforms/powernv/pci-ioda.c

1573

pnv_pci_ioda2_setup_default_config(pe);

arch/powerpc/platforms/powernv/pci-ioda.c

1574

if (pe->pbus)

arch/powerpc/platforms/powernv/pci-ioda.c

1575

pnv_ioda_setup_bus_dma(pe, pe->pbus);

arch/powerpc/platforms/powernv/pci-ioda.c

1589

struct pnv_ioda_pe *pe)

arch/powerpc/platforms/powernv/pci-ioda.c

1594

pe->tce_bypass_base = 1ull << 59;

arch/powerpc/platforms/powernv/pci-ioda.c

1597

pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",

arch/powerpc/platforms/powernv/pci-ioda.c

1601

pe->table_group.tce32_start = 0;

arch/powerpc/platforms/powernv/pci-ioda.c

1602

pe->table_group.tce32_size = phb->ioda.m32_pci_base;

arch/powerpc/platforms/powernv/pci-ioda.c

1603

pe->table_group.max_dynamic_windows_supported =

arch/powerpc/platforms/powernv/pci-ioda.c

1605

pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;

arch/powerpc/platforms/powernv/pci-ioda.c

1606

pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb);

arch/powerpc/platforms/powernv/pci-ioda.c

1608

rc = pnv_pci_ioda2_setup_default_config(pe);

arch/powerpc/platforms/powernv/pci-ioda.c

161

for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) {

arch/powerpc/platforms/powernv/pci-ioda.c

1613

pe->table_group.ops = &pnv_pci_ioda2_ops;

arch/powerpc/platforms/powernv/pci-ioda.c

1614

iommu_register_group(&pe->table_group, phb->hose->global_number,

arch/powerpc/platforms/powernv/pci-ioda.c

1615

pe->pe_number);

arch/powerpc/platforms/powernv/pci-ioda.c

1617

pe->dma_setup_done = true;

arch/powerpc/platforms/powernv/pci-ioda.c

162

if (test_bit(pe, phb->ioda.pe_alloc)) {

arch/powerpc/platforms/powernv/pci-ioda.c

1653

struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);

arch/powerpc/platforms/powernv/pci-ioda.c

1661

if (pe == NULL)

arch/powerpc/platforms/powernv/pci-ioda.c

1665

if (pe->mve_number < 0)

arch/powerpc/platforms/powernv/pci-ioda.c

1673

rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);

arch/powerpc/platforms/powernv/pci-ioda.c

1683

rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,

arch/powerpc/platforms/powernv/pci-ioda.c

1695

rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,

arch/powerpc/platforms/powernv/pci-ioda.c

174

for (i = pe; i < pe + count; i++) {

arch/powerpc/platforms/powernv/pci-ioda.c

178

ret = &phb->ioda.pe_array[pe];

arch/powerpc/platforms/powernv/pci-ioda.c

185

void pnv_ioda_free_pe(struct pnv_ioda_pe *pe)

arch/powerpc/platforms/powernv/pci-ioda.c

187

struct pnv_phb *phb = pe->phb;

arch/powerpc/platforms/powernv/pci-ioda.c

188

unsigned int pe_num = pe->pe_number;

arch/powerpc/platforms/powernv/pci-ioda.c

190

WARN_ON(pe->pdev);

arch/powerpc/platforms/powernv/pci-ioda.c

191

memset(pe, 0, sizeof(struct pnv_ioda_pe));

arch/powerpc/platforms/powernv/pci-ioda.c

1914

static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe,

arch/powerpc/platforms/powernv/pci-ioda.c

1917

struct pnv_phb *phb = pe->phb;

arch/powerpc/platforms/powernv/pci-ioda.c

1933

phb->ioda.io_segmap[index] = pe->pe_number;

arch/powerpc/platforms/powernv/pci-ioda.c

1935

pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);

arch/powerpc/platforms/powernv/pci-ioda.c

1938

__func__, rc, index, pe->pe_number);

arch/powerpc/platforms/powernv/pci-ioda.c

1957

phb->ioda.m32_segmap[index] = pe->pe_number;

arch/powerpc/platforms/powernv/pci-ioda.c

1959

pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);

arch/powerpc/platforms/powernv/pci-ioda.c

1962

__func__, rc, index, pe->pe_number);

arch/powerpc/platforms/powernv/pci-ioda.c

1977

static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe)

arch/powerpc/platforms/powernv/pci-ioda.c

1987

BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));

arch/powerpc/platforms/powernv/pci-ioda.c

1989

list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {

arch/powerpc/platforms/powernv/pci-ioda.c

1991

pnv_ioda_setup_pe_res(pe, &pdev->resource[i]);

arch/powerpc/platforms/powernv/pci-ioda.c

1998

if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev))

arch/powerpc/platforms/powernv/pci-ioda.c

2001

pnv_ioda_setup_pe_res(pe,

arch/powerpc/platforms/powernv/pci-ioda.c

2032

struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_num];

arch/powerpc/platforms/powernv/pci-ioda.c

2037

pe_warn(pe, "rid: %04x dev count: %2d flags: %s%s%s%s%s%s\n",

arch/powerpc/platforms/powernv/pci-ioda.c

2038

pe->rid, pe->device_count,

arch/powerpc/platforms/powernv/pci-ioda.c

2039

(pe->flags & PNV_IODA_PE_DEV) ? "dev " : "",

arch/powerpc/platforms/powernv/pci-ioda.c

2040

(pe->flags & PNV_IODA_PE_BUS) ? "bus " : "",

arch/powerpc/platforms/powernv/pci-ioda.c

2041

(pe->flags & PNV_IODA_PE_BUS_ALL) ? "all " : "",

arch/powerpc/platforms/powernv/pci-ioda.c

2042

(pe->flags & PNV_IODA_PE_MASTER) ? "master " : "",

arch/powerpc/platforms/powernv/pci-ioda.c

2043

(pe->flags & PNV_IODA_PE_SLAVE) ? "slave " : "",

arch/powerpc/platforms/powernv/pci-ioda.c

2044

(pe->flags & PNV_IODA_PE_VF) ? "vf " : "");

arch/powerpc/platforms/powernv/pci-ioda.c

2226

struct pnv_ioda_pe *pe;

arch/powerpc/platforms/powernv/pci-ioda.c

2243

pe = pnv_ioda_setup_bus_PE(bus, all);

arch/powerpc/platforms/powernv/pci-ioda.c

2244

if (!pe)

arch/powerpc/platforms/powernv/pci-ioda.c

2247

pnv_ioda_setup_pe_seg(pe);

arch/powerpc/platforms/powernv/pci-ioda.c

2274

struct pnv_ioda_pe *pe;

arch/powerpc/platforms/powernv/pci-ioda.c

2281

pe = pnv_ioda_setup_dev_PE(dev);

arch/powerpc/platforms/powernv/pci-ioda.c

2282

if (!pe)

arch/powerpc/platforms/powernv/pci-ioda.c

2288

void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe)

arch/powerpc/platforms/powernv/pci-ioda.c

2290

struct iommu_table *tbl = pe->table_group.tables[0];

arch/powerpc/platforms/powernv/pci-ioda.c

2293

if (!pe->dma_setup_done)

arch/powerpc/platforms/powernv/pci-ioda.c

2296

rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);

arch/powerpc/platforms/powernv/pci-ioda.c

2298

pe_warn(pe, "OPAL error %lld release DMA window\n", rc);

arch/powerpc/platforms/powernv/pci-ioda.c

2300

pnv_pci_ioda2_set_bypass(pe, false);

arch/powerpc/platforms/powernv/pci-ioda.c

2301

if (pe->table_group.group) {

arch/powerpc/platforms/powernv/pci-ioda.c

2302

iommu_group_put(pe->table_group.group);

arch/powerpc/platforms/powernv/pci-ioda.c

2303

WARN_ON(pe->table_group.group);

arch/powerpc/platforms/powernv/pci-ioda.c

2309

static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe,

arch/powerpc/platforms/powernv/pci-ioda.c

2313

struct pnv_phb *phb = pe->phb;

arch/powerpc/platforms/powernv/pci-ioda.c

2318

if (map[idx] != pe->pe_number)

arch/powerpc/platforms/powernv/pci-ioda.c

2325

pe_warn(pe, "Error %lld unmapping (%d) segment#%d\n",

arch/powerpc/platforms/powernv/pci-ioda.c

2332

static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe)

arch/powerpc/platforms/powernv/pci-ioda.c

2334

struct pnv_phb *phb = pe->phb;

arch/powerpc/platforms/powernv/pci-ioda.c

2337

pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,

arch/powerpc/platforms/powernv/pci-ioda.c

2342

static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe)

arch/powerpc/platforms/powernv/pci-ioda.c

2344

struct pnv_phb *phb = pe->phb;

arch/powerpc/platforms/powernv/pci-ioda.c

2347

pe_info(pe, "Releasing PE\n");

arch/powerpc/platforms/powernv/pci-ioda.c

2350

list_del(&pe->list);

arch/powerpc/platforms/powernv/pci-ioda.c

2355

pnv_pci_ioda2_release_pe_dma(pe);

arch/powerpc/platforms/powernv/pci-ioda.c

2363

pnv_ioda_release_pe_seg(pe);

arch/powerpc/platforms/powernv/pci-ioda.c

2364

pnv_ioda_deconfigure_pe(pe->phb, pe);

arch/powerpc/platforms/powernv/pci-ioda.c

2367

if (pe->flags & PNV_IODA_PE_MASTER) {

arch/powerpc/platforms/powernv/pci-ioda.c

2368

list_for_each_entry_safe(slave, tmp, &pe->slaves, list) {

arch/powerpc/platforms/powernv/pci-ioda.c

2380

if (phb->ioda.root_pe_idx == pe->pe_number)

arch/powerpc/platforms/powernv/pci-ioda.c

2383

pnv_ioda_free_pe(pe);

arch/powerpc/platforms/powernv/pci-ioda.c

2390

struct pnv_ioda_pe *pe;

arch/powerpc/platforms/powernv/pci-ioda.c

2417

pe = &phb->ioda.pe_array[pdn->pe_number];

arch/powerpc/platforms/powernv/pci-ioda.c

2420

WARN_ON(--pe->device_count < 0);

arch/powerpc/platforms/powernv/pci-ioda.c

2421

if (pe->device_count == 0)

arch/powerpc/platforms/powernv/pci-ioda.c

2422

pnv_ioda_release_pe(pe);

arch/powerpc/platforms/powernv/pci-ioda.c

2436

struct pnv_ioda_pe *pe;

arch/powerpc/platforms/powernv/pci-ioda.c

2438

list_for_each_entry(pe, &phb->ioda.pe_list, list) {

arch/powerpc/platforms/powernv/pci-ioda.c

2439

if (!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)))

arch/powerpc/platforms/powernv/pci-ioda.c

2442

if (!pe->pbus)

arch/powerpc/platforms/powernv/pci-ioda.c

2445

if (bus->number == ((pe->rid >> 8) & 0xFF)) {

arch/powerpc/platforms/powernv/pci-ioda.c

2446

pe->pbus = bus;

arch/powerpc/platforms/powernv/pci-ioda.c

2457

struct pnv_ioda_pe *pe;

arch/powerpc/platforms/powernv/pci-ioda.c

2462

pe = pnv_pci_bdfn_to_pe(phb, pci_dev_id(pdev));

arch/powerpc/platforms/powernv/pci-ioda.c

2463

if (!pe)

arch/powerpc/platforms/powernv/pci-ioda.c

2466

if (!pe->table_group.group)

arch/powerpc/platforms/powernv/pci-ioda.c

2469

return iommu_group_ref_get(pe->table_group.group);

arch/powerpc/platforms/powernv/pci-ioda.c

296

struct pnv_ioda_pe *master_pe, *pe;

arch/powerpc/platforms/powernv/pci-ioda.c

334

pe = &phb->ioda.pe_array[i];

arch/powerpc/platforms/powernv/pci-ioda.c

336

phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number;

arch/powerpc/platforms/powernv/pci-ioda.c

338

pe->flags |= PNV_IODA_PE_MASTER;

arch/powerpc/platforms/powernv/pci-ioda.c

339

INIT_LIST_HEAD(&pe->slaves);

arch/powerpc/platforms/powernv/pci-ioda.c

340

master_pe = pe;

arch/powerpc/platforms/powernv/pci-ioda.c

342

pe->flags |= PNV_IODA_PE_SLAVE;

arch/powerpc/platforms/powernv/pci-ioda.c

343

pe->master = master_pe;

arch/powerpc/platforms/powernv/pci-ioda.c

344

list_add_tail(&pe->list, &master_pe->slaves);

arch/powerpc/platforms/powernv/pci-ioda.c

441

struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];

arch/powerpc/platforms/powernv/pci-ioda.c

446

if (pe->flags & PNV_IODA_PE_SLAVE) {

arch/powerpc/platforms/powernv/pci-ioda.c

447

pe = pe->master;

arch/powerpc/platforms/powernv/pci-ioda.c

448

if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))

arch/powerpc/platforms/powernv/pci-ioda.c

451

pe_no = pe->pe_number;

arch/powerpc/platforms/powernv/pci-ioda.c

465

if (!(pe->flags & PNV_IODA_PE_MASTER))

arch/powerpc/platforms/powernv/pci-ioda.c

468

list_for_each_entry(slave, &pe->slaves, list) {

arch/powerpc/platforms/powernv/pci-ioda.c

481

struct pnv_ioda_pe *pe, *slave;

arch/powerpc/platforms/powernv/pci-ioda.c

485

pe = &phb->ioda.pe_array[pe_no];

arch/powerpc/platforms/powernv/pci-ioda.c

486

if (pe->flags & PNV_IODA_PE_SLAVE) {

arch/powerpc/platforms/powernv/pci-ioda.c

487

pe = pe->master;

arch/powerpc/platforms/powernv/pci-ioda.c

488

WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));

arch/powerpc/platforms/powernv/pci-ioda.c

489

pe_no = pe->pe_number;

arch/powerpc/platforms/powernv/pci-ioda.c

49

static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);

arch/powerpc/platforms/powernv/pci-ioda.c

500

if (!(pe->flags & PNV_IODA_PE_MASTER))

arch/powerpc/platforms/powernv/pci-ioda.c

504

list_for_each_entry(slave, &pe->slaves, list) {

arch/powerpc/platforms/powernv/pci-ioda.c

52

void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,

arch/powerpc/platforms/powernv/pci-ioda.c

521

struct pnv_ioda_pe *slave, *pe;

arch/powerpc/platforms/powernv/pci-ioda.c

534

pe = &phb->ioda.pe_array[pe_no];

arch/powerpc/platforms/powernv/pci-ioda.c

535

if (pe->flags & PNV_IODA_PE_SLAVE) {

arch/powerpc/platforms/powernv/pci-ioda.c

536

pe = pe->master;

arch/powerpc/platforms/powernv/pci-ioda.c

537

WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));

arch/powerpc/platforms/powernv/pci-ioda.c

538

pe_no = pe->pe_number;

arch/powerpc/platforms/powernv/pci-ioda.c

553

if (!(pe->flags & PNV_IODA_PE_MASTER))

arch/powerpc/platforms/powernv/pci-ioda.c

556

list_for_each_entry(slave, &pe->slaves, list) {

arch/powerpc/platforms/powernv/pci-ioda.c

64

if (pe->flags & PNV_IODA_PE_DEV)

arch/powerpc/platforms/powernv/pci-ioda.c

641

struct pnv_ioda_pe *pe,

arch/powerpc/platforms/powernv/pci-ioda.c

65

strscpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));

arch/powerpc/platforms/powernv/pci-ioda.c

653

opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,

arch/powerpc/platforms/powernv/pci-ioda.c

655

if (pe->flags & PNV_IODA_PE_MASTER) {

arch/powerpc/platforms/powernv/pci-ioda.c

656

list_for_each_entry(slave, &pe->slaves, list)

arch/powerpc/platforms/powernv/pci-ioda.c

66

else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))

arch/powerpc/platforms/powernv/pci-ioda.c

669

ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);

arch/powerpc/platforms/powernv/pci-ioda.c

674

if (pe->flags & PNV_IODA_PE_MASTER) {

arch/powerpc/platforms/powernv/pci-ioda.c

675

list_for_each_entry(slave, &pe->slaves, list) {

arch/powerpc/platforms/powernv/pci-ioda.c

676

ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);

arch/powerpc/platforms/powernv/pci-ioda.c

68

pci_domain_nr(pe->pbus), pe->pbus->number);

arch/powerpc/platforms/powernv/pci-ioda.c

682

if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))

arch/powerpc/platforms/powernv/pci-ioda.c

683

pdev = pe->pbus->self;

arch/powerpc/platforms/powernv/pci-ioda.c

684

else if (pe->flags & PNV_IODA_PE_DEV)

arch/powerpc/platforms/powernv/pci-ioda.c

685

pdev = pe->pdev->bus->self;

arch/powerpc/platforms/powernv/pci-ioda.c

687

else if (pe->flags & PNV_IODA_PE_VF)

arch/powerpc/platforms/powernv/pci-ioda.c

688

pdev = pe->parent_dev;

arch/powerpc/platforms/powernv/pci-ioda.c

696

ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);

arch/powerpc/platforms/powernv/pci-ioda.c

70

else if (pe->flags & PNV_IODA_PE_VF)

arch/powerpc/platforms/powernv/pci-ioda.c

708

struct pnv_ioda_pe *pe,

arch/powerpc/platforms/powernv/pci-ioda.c

718

pe->pe_number,

arch/powerpc/platforms/powernv/pci-ioda.c

72

pci_domain_nr(pe->parent_dev->bus),

arch/powerpc/platforms/powernv/pci-ioda.c

725

opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,

arch/powerpc/platforms/powernv/pci-ioda.c

729

rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,

arch/powerpc/platforms/powernv/pci-ioda.c

73

(pe->rid & 0xff00) >> 8,

arch/powerpc/platforms/powernv/pci-ioda.c

730

pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);

arch/powerpc/platforms/powernv/pci-ioda.c

732

pe_warn(pe, "OPAL error %lld remove self from PELTV\n", rc);

arch/powerpc/platforms/powernv/pci-ioda.c

735

int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)

arch/powerpc/platforms/powernv/pci-ioda.c

74

PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));

arch/powerpc/platforms/powernv/pci-ioda.c

743

if (pe->pbus) {

arch/powerpc/platforms/powernv/pci-ioda.c

748

parent = pe->pbus->self;

arch/powerpc/platforms/powernv/pci-ioda.c

749

if (pe->flags & PNV_IODA_PE_BUS_ALL)

arch/powerpc/platforms/powernv/pci-ioda.c

750

count = resource_size(&pe->pbus->busn_res);

arch/powerpc/platforms/powernv/pci-ioda.c

762

dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",

arch/powerpc/platforms/powernv/pci-ioda.c

767

rid_end = pe->rid + (count << 8);

arch/powerpc/platforms/powernv/pci-ioda.c

770

if (pe->flags & PNV_IODA_PE_VF)

arch/powerpc/platforms/powernv/pci-ioda.c

771

parent = pe->parent_dev;

arch/powerpc/platforms/powernv/pci-ioda.c

774

parent = pe->pdev->bus->self;

arch/powerpc/platforms/powernv/pci-ioda.c

778

rid_end = pe->rid + 1;

arch/powerpc/platforms/powernv/pci-ioda.c

78

level, pfix, pe->pe_number, &vaf);

arch/powerpc/platforms/powernv/pci-ioda.c

782

for (rid = pe->rid; rid < rid_end; rid++)

arch/powerpc/platforms/powernv/pci-ioda.c

790

pnv_ioda_unset_peltv(phb, pe, parent);

arch/powerpc/platforms/powernv/pci-ioda.c

792

rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,

arch/powerpc/platforms/powernv/pci-ioda.c

795

pe_err(pe, "OPAL error %lld trying to setup PELT table\n", rc);

arch/powerpc/platforms/powernv/pci-ioda.c

797

pe->pbus = NULL;

arch/powerpc/platforms/powernv/pci-ioda.c

798

pe->pdev = NULL;

arch/powerpc/platforms/powernv/pci-ioda.c

800

pe->parent_dev = NULL;

arch/powerpc/platforms/powernv/pci-ioda.c

806

int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)

arch/powerpc/platforms/powernv/pci-ioda.c

812

if (pe->pbus) {

arch/powerpc/platforms/powernv/pci-ioda.c

817

if (pe->flags & PNV_IODA_PE_BUS_ALL)

arch/powerpc/platforms/powernv/pci-ioda.c

818

count = resource_size(&pe->pbus->busn_res);

arch/powerpc/platforms/powernv/pci-ioda.c

830

dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",

arch/powerpc/platforms/powernv/pci-ioda.c

835

rid_end = pe->rid + (count << 8);

arch/powerpc/platforms/powernv/pci-ioda.c

840

rid_end = pe->rid + 1;

arch/powerpc/platforms/powernv/pci-ioda.c

849

rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,

arch/powerpc/platforms/powernv/pci-ioda.c

852

pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);

arch/powerpc/platforms/powernv/pci-ioda.c

861

pnv_ioda_set_peltv(phb, pe, true);

arch/powerpc/platforms/powernv/pci-ioda.c

864

for (rid = pe->rid; rid < rid_end; rid++)

arch/powerpc/platforms/powernv/pci-ioda.c

865

phb->ioda.pe_rmap[rid] = pe->pe_number;

arch/powerpc/platforms/powernv/pci-ioda.c

867

pe->mve_number = 0;

arch/powerpc/platforms/powernv/pci-ioda.c

876

struct pnv_ioda_pe *pe;

arch/powerpc/platforms/powernv/pci-ioda.c

886

pe = pnv_ioda_alloc_pe(phb, 1);

arch/powerpc/platforms/powernv/pci-ioda.c

887

if (!pe) {

arch/powerpc/platforms/powernv/pci-ioda.c

899

pdn->pe_number = pe->pe_number;

arch/powerpc/platforms/powernv/pci-ioda.c

900

pe->flags = PNV_IODA_PE_DEV;

arch/powerpc/platforms/powernv/pci-ioda.c

901

pe->pdev = dev;

arch/powerpc/platforms/powernv/pci-ioda.c

902

pe->pbus = NULL;

arch/powerpc/platforms/powernv/pci-ioda.c

903

pe->mve_number = -1;

arch/powerpc/platforms/powernv/pci-ioda.c

904

pe->rid = dev->bus->number << 8 | pdn->devfn;

arch/powerpc/platforms/powernv/pci-ioda.c

905

pe->device_count++;

arch/powerpc/platforms/powernv/pci-ioda.c

907

pe_info(pe, "Associated device to PE\n");

arch/powerpc/platforms/powernv/pci-ioda.c

909

if (pnv_ioda_configure_pe(phb, pe)) {

arch/powerpc/platforms/powernv/pci-ioda.c

911

pnv_ioda_free_pe(pe);

arch/powerpc/platforms/powernv/pci-ioda.c

913

pe->pdev = NULL;

arch/powerpc/platforms/powernv/pci-ioda.c

919

list_add_tail(&pe->list, &phb->ioda.pe_list);

arch/powerpc/platforms/powernv/pci-ioda.c

921

return pe;

arch/powerpc/platforms/powernv/pci-ioda.c

933

struct pnv_ioda_pe *pe = NULL;

arch/powerpc/platforms/powernv/pci-ioda.c

942

pe = &phb->ioda.pe_array[pe_num];

arch/powerpc/platforms/powernv/pci-ioda.c

948

pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx];

arch/powerpc/platforms/powernv/pci-ioda.c

951

if (!pe)

arch/powerpc/platforms/powernv/pci-ioda.c

952

pe = pnv_ioda_pick_m64_pe(bus, all);

arch/powerpc/platforms/powernv/pci-ioda.c

955

if (!pe)

arch/powerpc/platforms/powernv/pci-ioda.c

956

pe = pnv_ioda_alloc_pe(phb, 1);

arch/powerpc/platforms/powernv/pci-ioda.c

958

if (!pe) {

arch/powerpc/platforms/powernv/pci-ioda.c

964

pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);

arch/powerpc/platforms/powernv/pci-ioda.c

965

pe->pbus = bus;

arch/powerpc/platforms/powernv/pci-ioda.c

966

pe->pdev = NULL;

arch/powerpc/platforms/powernv/pci-ioda.c

967

pe->mve_number = -1;

arch/powerpc/platforms/powernv/pci-ioda.c

968

pe->rid = bus->busn_res.start << 8;

arch/powerpc/platforms/powernv/pci-ioda.c

971

pe_info(pe, "Secondary bus %pad..%pad associated with PE#%x\n",

arch/powerpc/platforms/powernv/pci-ioda.c

973

pe->pe_number);

arch/powerpc/platforms/powernv/pci-ioda.c

975

pe_info(pe, "Secondary bus %pad associated with PE#%x\n",

arch/powerpc/platforms/powernv/pci-ioda.c

976

&bus->busn_res.start, pe->pe_number);

arch/powerpc/platforms/powernv/pci-ioda.c

978

if (pnv_ioda_configure_pe(phb, pe)) {

arch/powerpc/platforms/powernv/pci-ioda.c

980

pnv_ioda_free_pe(pe);

arch/powerpc/platforms/powernv/pci-ioda.c

981

pe->pbus = NULL;

arch/powerpc/platforms/powernv/pci-ioda.c

986

list_add_tail(&pe->list, &phb->ioda.pe_list);

arch/powerpc/platforms/powernv/pci-ioda.c

988

return pe;

arch/powerpc/platforms/powernv/pci-ioda.c

995

struct pnv_ioda_pe *pe;

arch/powerpc/platforms/powernv/pci-ioda.c

998

pe = pnv_pci_bdfn_to_pe(phb, pci_dev_id(pdev));

arch/powerpc/platforms/powernv/pci-ioda.c

999

if (!pe) {

arch/powerpc/platforms/powernv/pci-sriov.c

229

struct pnv_ioda_pe *pe = pnv_ioda_get_pe(pdev);

arch/powerpc/platforms/powernv/pci-sriov.c

236

pe->pdev = pdev;

arch/powerpc/platforms/powernv/pci-sriov.c

237

WARN_ON(!(pe->flags & PNV_IODA_PE_VF));

arch/powerpc/platforms/powernv/pci-sriov.c

478

struct pnv_ioda_pe *pe, *pe_n;

arch/powerpc/platforms/powernv/pci-sriov.c

486

list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {

arch/powerpc/platforms/powernv/pci-sriov.c

487

if (pe->parent_dev != pdev)

arch/powerpc/platforms/powernv/pci-sriov.c

490

pnv_pci_ioda2_release_pe_dma(pe);

arch/powerpc/platforms/powernv/pci-sriov.c

494

list_del(&pe->list);

arch/powerpc/platforms/powernv/pci-sriov.c

497

pnv_ioda_deconfigure_pe(phb, pe);

arch/powerpc/platforms/powernv/pci-sriov.c

499

pnv_ioda_free_pe(pe);

arch/powerpc/platforms/powernv/pci-sriov.c

617

struct pnv_ioda_pe *pe;

arch/powerpc/platforms/powernv/pci-sriov.c

636

pe = &iov->vf_pe_arr[vf_index];

arch/powerpc/platforms/powernv/pci-sriov.c

637

pe->phb = phb;

arch/powerpc/platforms/powernv/pci-sriov.c

638

pe->flags = PNV_IODA_PE_VF;

arch/powerpc/platforms/powernv/pci-sriov.c

639

pe->pbus = NULL;

arch/powerpc/platforms/powernv/pci-sriov.c

640

pe->parent_dev = pdev;

arch/powerpc/platforms/powernv/pci-sriov.c

641

pe->mve_number = -1;

arch/powerpc/platforms/powernv/pci-sriov.c

642

pe->rid = (vf_bus << 8) | vf_devfn;

arch/powerpc/platforms/powernv/pci-sriov.c

644

pe_num = pe->pe_number;

arch/powerpc/platforms/powernv/pci-sriov.c

645

pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n",

arch/powerpc/platforms/powernv/pci-sriov.c

649

if (pnv_ioda_configure_pe(phb, pe)) {

arch/powerpc/platforms/powernv/pci-sriov.c

651

pnv_ioda_free_pe(pe);

arch/powerpc/platforms/powernv/pci-sriov.c

652

pe->pdev = NULL;

arch/powerpc/platforms/powernv/pci-sriov.c

658

list_add_tail(&pe->list, &phb->ioda.pe_list);

arch/powerpc/platforms/powernv/pci-sriov.c

670

pnv_pci_ioda2_setup_dma_pe(phb, pe);

arch/powerpc/platforms/powernv/pci.c

656

if (edev->pe &&

arch/powerpc/platforms/powernv/pci.c

657

(edev->pe->state & EEH_PE_CFG_BLOCKED))

arch/powerpc/platforms/powernv/pci.h

206

int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe);

arch/powerpc/platforms/powernv/pci.h

207

int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe);

arch/powerpc/platforms/powernv/pci.h

209

void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe);

arch/powerpc/platforms/powernv/pci.h

210

void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe);

arch/powerpc/platforms/powernv/pci.h

213

void pnv_ioda_free_pe(struct pnv_ioda_pe *pe);

arch/powerpc/platforms/powernv/pci.h

288

extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,

arch/powerpc/platforms/powernv/pci.h

290

#define pe_err(pe, fmt, ...) \

arch/powerpc/platforms/powernv/pci.h

291

pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__)

arch/powerpc/platforms/powernv/pci.h

292

#define pe_warn(pe, fmt, ...) \

arch/powerpc/platforms/powernv/pci.h

293

pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__)

arch/powerpc/platforms/powernv/pci.h

294

#define pe_info(pe, fmt, ...) \

arch/powerpc/platforms/powernv/pci.h

295

pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__)

arch/powerpc/platforms/pseries/eeh_pseries.c

345

if (parent->pe)

arch/powerpc/platforms/pseries/eeh_pseries.c

346

return parent->pe;

arch/powerpc/platforms/pseries/eeh_pseries.c

366

struct eeh_pe pe, *parent;

arch/powerpc/platforms/pseries/eeh_pseries.c

390

if (edev->pe)

arch/powerpc/platforms/pseries/eeh_pseries.c

433

memset(&pe, 0, sizeof(struct eeh_pe));

arch/powerpc/platforms/pseries/eeh_pseries.c

434

pe.phb = pdn->phb;

arch/powerpc/platforms/pseries/eeh_pseries.c

435

pe.addr = ret;

arch/powerpc/platforms/pseries/eeh_pseries.c

438

ret = eeh_ops->set_option(&pe, EEH_OPT_ENABLE);

arch/powerpc/platforms/pseries/eeh_pseries.c

444

edev->pe_config_addr = pe.addr;

arch/powerpc/platforms/pseries/eeh_pseries.c

473

if (!edev || !edev->pe)

arch/powerpc/platforms/pseries/eeh_pseries.c

510

static int pseries_eeh_set_option(struct eeh_pe *pe, int option)

arch/powerpc/platforms/pseries/eeh_pseries.c

535

pe->addr, BUID_HI(pe->phb->buid),

arch/powerpc/platforms/pseries/eeh_pseries.c

536

BUID_LO(pe->phb->buid), option);

arch/powerpc/platforms/pseries/eeh_pseries.c

554

static int pseries_eeh_get_state(struct eeh_pe *pe, int *delay)

arch/powerpc/platforms/pseries/eeh_pseries.c

562

pe->addr, BUID_HI(pe->phb->buid),

arch/powerpc/platforms/pseries/eeh_pseries.c

563

BUID_LO(pe->phb->buid));

arch/powerpc/platforms/pseries/eeh_pseries.c

568

pe->addr, BUID_HI(pe->phb->buid),

arch/powerpc/platforms/pseries/eeh_pseries.c

569

BUID_LO(pe->phb->buid));

arch/powerpc/platforms/pseries/eeh_pseries.c

622

static int pseries_eeh_reset(struct eeh_pe *pe, int option)

arch/powerpc/platforms/pseries/eeh_pseries.c

624

return pseries_eeh_phb_reset(pe->phb, pe->addr, option);

arch/powerpc/platforms/pseries/eeh_pseries.c

638

static int pseries_eeh_get_log(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len)

arch/powerpc/platforms/pseries/eeh_pseries.c

646

ret = rtas_call(ibm_slot_error_detail, 8, 1, NULL, pe->addr,

arch/powerpc/platforms/pseries/eeh_pseries.c

647

BUID_HI(pe->phb->buid), BUID_LO(pe->phb->buid),

arch/powerpc/platforms/pseries/eeh_pseries.c

663

static int pseries_eeh_configure_bridge(struct eeh_pe *pe)

arch/powerpc/platforms/pseries/eeh_pseries.c

665

return pseries_eeh_phb_configure_bridge(pe->phb, pe->addr);

arch/powerpc/platforms/pseries/eeh_pseries.c

76

struct eeh_pe *physfn_pe = pci_dev_to_eeh_dev(pdev->physfn)->pe;

arch/powerpc/platforms/pseries/eeh_pseries.c

799

static int pseries_eeh_err_inject(struct eeh_pe *pe, int type, int func,

arch/powerpc/platforms/pseries/eeh_pseries.c

815

list_for_each_entry(pdev, &pe->edevs, entry)

arch/powerpc/platforms/pseries/msi.c

200

if (edev->pe)

arch/powerpc/platforms/pseries/msi.c

201

edev = list_first_entry(&edev->pe->edevs, struct eeh_dev,

arch/x86/coco/sev/svsm.c

100

struct svsm_pvalidate_entry *pe;

arch/x86/coco/sev/svsm.c

106

pe = &pc->entry[0];

arch/x86/coco/sev/svsm.c

109

pe->page_size = RMP_PG_SIZE_4K;

arch/x86/coco/sev/svsm.c

110

pe->action = action;

arch/x86/coco/sev/svsm.c

111

pe->ignore_cf = 0;

arch/x86/coco/sev/svsm.c

112

pe->rsvd = 0;

arch/x86/coco/sev/svsm.c

113

pe->pfn = pfn;

arch/x86/coco/sev/svsm.c

115

pe++;

arch/x86/coco/sev/svsm.c

129

struct svsm_pvalidate_entry *pe;

arch/x86/coco/sev/svsm.c

136

pe = &pc->entry[0];

arch/x86/coco/sev/svsm.c

140

pe->page_size = e->pagesize ? RMP_PG_SIZE_2M : RMP_PG_SIZE_4K;

arch/x86/coco/sev/svsm.c

141

pe->action = e->operation == SNP_PAGE_STATE_PRIVATE;

arch/x86/coco/sev/svsm.c

142

pe->ignore_cf = 0;

arch/x86/coco/sev/svsm.c

143

pe->rsvd = 0;

arch/x86/coco/sev/svsm.c

144

pe->pfn = e->gfn;

arch/x86/coco/sev/svsm.c

146

pe++;

crypto/asymmetric_keys/verify_pefile.c

110

ctx->n_sections = pe->sections;

crypto/asymmetric_keys/verify_pefile.c

26

const struct pe_hdr *pe;

crypto/asymmetric_keys/verify_pefile.c

47

chkaddr(cursor, mz->peaddr, sizeof(*pe));

crypto/asymmetric_keys/verify_pefile.c

48

pe = pebuf + mz->peaddr;

crypto/asymmetric_keys/verify_pefile.c

49

if (pe->magic != IMAGE_NT_SIGNATURE)

crypto/asymmetric_keys/verify_pefile.c

51

cursor = mz->peaddr + sizeof(*pe);

drivers/ata/sata_dwc_460ex.c

123

struct ata_probe_ent *pe; /* ptr to probe-ent */

drivers/clk/st/clkgen-fsyn.c

111

.pe = { CLKGEN_FIELD(0x304, 0x7fff, 0),

drivers/clk/st/clkgen-fsyn.c

147

.pe = { CLKGEN_FIELD(0x2b4, 0x7fff, 0),

drivers/clk/st/clkgen-fsyn.c

36

unsigned long pe;

drivers/clk/st/clkgen-fsyn.c

524

u32 pe;

drivers/clk/st/clkgen-fsyn.c

554

CLKGEN_WRITE(fs, pe[fs->chan], fs->pe);

drivers/clk/st/clkgen-fsyn.c

59

struct clkgen_field pe[QUADFS_MAX_CHAN];

drivers/clk/st/clkgen-fsyn.c

638

res = (P20 * (32 + fs->mdiv) + 32 * fs->pe) * s * ns;

drivers/clk/st/clkgen-fsyn.c

663

fs_tmp.pe = (unsigned long)*p;

drivers/clk/st/clkgen-fsyn.c

673

fs->pe = (unsigned long)*p;

drivers/clk/st/clkgen-fsyn.c

722

if (fs->pe > 2)

drivers/clk/st/clkgen-fsyn.c

723

p2 = fs->pe - 2;

drivers/clk/st/clkgen-fsyn.c

727

for (; p2 < 32768ll && (p2 <= (fs->pe + 2)); p2++) {

drivers/clk/st/clkgen-fsyn.c

728

fs_tmp.pe = (unsigned long)p2;

drivers/clk/st/clkgen-fsyn.c

736

fs->pe = (unsigned long)p2;

drivers/clk/st/clkgen-fsyn.c

752

params->pe = CLKGEN_READ(fs, pe[fs->chan]);

drivers/clk/st/clkgen-fsyn.c

763

if (!params->mdiv && !params->pe && !params->sdiv)

drivers/clk/st/clkgen-fsyn.c

767

fs->pe = params->pe;

drivers/clk/st/clkgen-fsyn.c

828

(unsigned int)params.pe, (unsigned int)params.nsdiv);

drivers/clk/st/clkgen-fsyn.c

838

fs->pe = params->pe;

drivers/crypto/inside-secure/safexcel.c

1365

offsets->pe = EIP197_PE_BASE;

drivers/crypto/inside-secure/safexcel.c

1377

offsets->pe = EIP97_PE_BASE;

drivers/crypto/inside-secure/safexcel.c

271

int pe, i;

drivers/crypto/inside-secure/safexcel.c

274

for (pe = 0; pe < priv->config.pes; pe++) {

drivers/crypto/inside-secure/safexcel.c

276

writel(3, EIP197_PE(priv) + EIP197_PE_ICE_PUTF_CTRL(pe));

drivers/crypto/inside-secure/safexcel.c

277

writel(0, EIP197_PE(priv) + EIP197_PE_ICE_PPTF_CTRL(pe));

drivers/crypto/inside-secure/safexcel.c

280

val = readl(EIP197_PE(priv) + EIP197_PE_ICE_SCRATCH_CTRL(pe));

drivers/crypto/inside-secure/safexcel.c

285

writel(val, EIP197_PE(priv) + EIP197_PE_ICE_SCRATCH_CTRL(pe));

drivers/crypto/inside-secure/safexcel.c

290

EIP197_PE_ICE_SCRATCH_RAM(pe) + (i << 2));

drivers/crypto/inside-secure/safexcel.c

296

EIP197_PE(priv) + EIP197_PE_ICE_FPP_CTRL(pe));

drivers/crypto/inside-secure/safexcel.c

302

EIP197_PE(priv) + EIP197_PE_ICE_PUE_CTRL(pe));

drivers/crypto/inside-secure/safexcel.c

306

EIP197_PE(priv) + EIP197_PE_ICE_RAM_CTRL(pe));

drivers/crypto/inside-secure/safexcel.c

311

EIP197_PE_DEBUG(pe));

drivers/crypto/inside-secure/safexcel.c

344

int pe, pollcnt;

drivers/crypto/inside-secure/safexcel.c

352

for (pe = 0; pe < priv->config.pes; pe++) {

drivers/crypto/inside-secure/safexcel.c

353

base = EIP197_PE_ICE_SCRATCH_RAM(pe);

drivers/crypto/inside-secure/safexcel.c

362

fpp, pe);

drivers/crypto/inside-secure/safexcel.c

372

int pe;

drivers/crypto/inside-secure/safexcel.c

375

for (pe = 0; pe < priv->config.pes; pe++) {

drivers/crypto/inside-secure/safexcel.c

377

writel(0, EIP197_PE(priv) + EIP197_PE_ICE_RAM_CTRL(pe));

drivers/crypto/inside-secure/safexcel.c

386

writel(val, EIP197_PE(priv) + EIP197_PE_ICE_FPP_CTRL(pe));

drivers/crypto/inside-secure/safexcel.c

395

writel(val, EIP197_PE(priv) + EIP197_PE_ICE_PUE_CTRL(pe));

drivers/crypto/inside-secure/safexcel.c

416

int i, j, ret = 0, pe;

drivers/crypto/inside-secure/safexcel.c

452

for (pe = 0; pe < priv->config.pes; pe++)

drivers/crypto/inside-secure/safexcel.c

454

EIP197_PE(priv) + EIP197_PE_ICE_RAM_CTRL(pe));

drivers/crypto/inside-secure/safexcel.c

597

int i, ret, pe, opbuflo, opbufhi;

drivers/crypto/inside-secure/safexcel.c

626

for (pe = 0; pe < priv->config.pes; pe++) {

drivers/crypto/inside-secure/safexcel.c

631

EIP197_HIA_DFE_THR(priv) + EIP197_HIA_DFE_THR_CTRL(pe));

drivers/crypto/inside-secure/safexcel.c

636

EIP197_HIA_AIC(priv) + EIP197_HIA_RA_PE_CTRL(pe));

drivers/crypto/inside-secure/safexcel.c

646

writel(val, EIP197_HIA_DFE(priv) + EIP197_HIA_DFE_CFG(pe));

drivers/crypto/inside-secure/safexcel.c

649

writel(0, EIP197_HIA_DFE_THR(priv) + EIP197_HIA_DFE_THR_CTRL(pe));

drivers/crypto/inside-secure/safexcel.c

654

EIP197_PE(priv) + EIP197_PE_IN_DBUF_THRES(pe));

drivers/crypto/inside-secure/safexcel.c

657

EIP197_PE(priv) + EIP197_PE_IN_TBUF_THRES(pe));

drivers/crypto/inside-secure/safexcel.c

663

EIP197_HIA_AIC(priv) + EIP197_HIA_RA_PE_CTRL(pe));

drivers/crypto/inside-secure/safexcel.c

669

EIP197_HIA_DSE_THR(priv) + EIP197_HIA_DSE_THR_CTRL(pe));

drivers/crypto/inside-secure/safexcel.c

672

while ((readl(EIP197_HIA_DSE_THR(priv) + EIP197_HIA_DSE_THR_STAT(pe)) &

drivers/crypto/inside-secure/safexcel.c

694

writel(val, EIP197_HIA_DSE(priv) + EIP197_HIA_DSE_CFG(pe));

drivers/crypto/inside-secure/safexcel.c

697

writel(0, EIP197_HIA_DSE_THR(priv) + EIP197_HIA_DSE_THR_CTRL(pe));

drivers/crypto/inside-secure/safexcel.c

702

EIP197_PE(priv) + EIP197_PE_OUT_DBUF_THRES(pe));

drivers/crypto/inside-secure/safexcel.c

710

writel(val, EIP197_PE(priv) + EIP197_PE_EIP96_TOKEN_CTRL(pe));

drivers/crypto/inside-secure/safexcel.c

714

EIP197_PE(priv) + EIP197_PE_EIP96_FUNCTION_EN(pe));

drivers/crypto/inside-secure/safexcel.c

716

EIP197_PE(priv) + EIP197_PE_EIP96_FUNCTION2_EN(pe));

drivers/crypto/inside-secure/safexcel.c

768

for (pe = 0; pe < priv->config.pes; pe++) {

drivers/crypto/inside-secure/safexcel.c

771

EIP197_HIA_DFE_THR(priv) + EIP197_HIA_DFE_THR_CTRL(pe));

drivers/crypto/inside-secure/safexcel.c

775

EIP197_HIA_DSE_THR(priv) + EIP197_HIA_DSE_THR_CTRL(pe));

drivers/crypto/inside-secure/safexcel.h

100

#define EIP197_PE(priv) ((priv)->base + (priv)->offsets.pe)

drivers/crypto/inside-secure/safexcel.h

787

u32 pe;

drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c

228

struct amdgpu_pmu_entry *pe = container_of(event->pmu,

drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c

236

if ((!pe->adev->df.funcs) ||

drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c

237

(!pe->adev->df.funcs->pmc_start))

drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c

247

target_cntr = pe->adev->df.funcs->pmc_start(pe->adev,

drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c

256

pe->adev->df.funcs->pmc_start(pe->adev, hwc->config,

drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c

270

struct amdgpu_pmu_entry *pe = container_of(event->pmu,

drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c

275

if ((!pe->adev->df.funcs) ||

drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c

276

(!pe->adev->df.funcs->pmc_get_count))

drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c

284

pe->adev->df.funcs->pmc_get_count(pe->adev,

drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c

300

struct amdgpu_pmu_entry *pe = container_of(event->pmu,

drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c

307

if ((!pe->adev->df.funcs) ||

drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c

308

(!pe->adev->df.funcs->pmc_stop))

drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c

314

pe->adev->df.funcs->pmc_stop(pe->adev, hwc->config, hwc->idx,

drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c

336

struct amdgpu_pmu_entry *pe = container_of(event->pmu,

drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c

340

if ((!pe->adev->df.funcs) ||

drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c

341

(!pe->adev->df.funcs->pmc_start))

drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c

344

switch (pe->pmu_perf_type) {

drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c

360

target_cntr = pe->adev->df.funcs->pmc_start(pe->adev,

drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c

386

struct amdgpu_pmu_entry *pe = container_of(event->pmu,

drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c

389

if ((!pe->adev->df.funcs) ||

drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c

390

(!pe->adev->df.funcs->pmc_stop))

drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c

398

pe->adev->df.funcs->pmc_stop(pe->adev, hwc->config, hwc->idx,

drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c

578

struct amdgpu_pmu_entry *pe, *temp;

drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c

580

list_for_each_entry_safe(pe, temp, &amdgpu_pmu_list, entry) {

drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c

581

if (pe->adev != adev)

drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c

583

list_del(&pe->entry);

drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c

584

perf_pmu_unregister(&pe->pmu);

drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c

585

kfree(pe->pmu.attr_groups);

drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c

586

kfree(pe->fmt_attr_group.attrs);

drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c

587

kfree(pe->fmt_attr);

drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c

588

kfree(pe->evt_attr_group.attrs);

drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c

589

kfree(pe->evt_attr);

drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c

590

kfree(pe);

drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h

366

TP_PROTO(uint64_t pe, uint64_t addr, unsigned count,

drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h

368

TP_ARGS(pe, addr, count, incr, flags, immediate),

drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h

370

__field(u64, pe)

drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h

379

__entry->pe = pe;

drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h

387

"immediate=%d", __entry->pe, __entry->addr, __entry->incr,

drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h

392

TP_PROTO(uint64_t pe, uint64_t src, unsigned count, bool immediate),

drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h

393

TP_ARGS(pe, src, count, immediate),

drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h

395

__field(u64, pe)

drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h

402

__entry->pe = pe;

drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h

408

__entry->pe, __entry->src, __entry->count,

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h

226

uint64_t pe, uint64_t src,

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h

230

void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h

235

uint64_t pe,

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h

315

struct amdgpu_bo_vm *bo, uint64_t pe, uint64_t addr,

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h

494

#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h

495

#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h

496

#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))

drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c

72

struct amdgpu_bo_vm *vmbo, uint64_t pe,

drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c

85

pe += (unsigned long)amdgpu_bo_kptr(&vmbo->bo);

drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c

87

trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags, p->immediate);

drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c

93

amdgpu_gmc_set_pte_pde(p->adev, (void *)(uintptr_t)pe,

drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c

682

uint64_t pe, uint64_t addr,

drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c

719

params->vm->update_funcs->update(params, pt, pe, addr, count, incr,

drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c

159

struct amdgpu_bo *bo, uint64_t pe,

drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c

167

pe += amdgpu_bo_gpu_offset_no_check(bo);

drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c

168

trace_amdgpu_vm_copy_ptes(pe, src, count, p->immediate);

drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c

170

amdgpu_vm_copy_pte(p->adev, ib, pe, src, count);

drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c

188

struct amdgpu_bo *bo, uint64_t pe,

drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c

194

pe += amdgpu_bo_gpu_offset_no_check(bo);

drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c

195

trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags, p->immediate);

drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c

197

amdgpu_vm_write_pte(p->adev, ib, pe, addr | flags,

drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c

200

amdgpu_vm_set_pte_pde(p->adev, ib, pe, addr,

drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c

220

struct amdgpu_bo_vm *vmbo, uint64_t pe,

drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c

261

amdgpu_vm_sdma_set_ptes(p, bo, pe, addr, count,

drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c

282

amdgpu_vm_sdma_copy_ptes(p, bo, pe, nptes);

drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c

284

pe += nptes * 8;

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

718

uint64_t pe, uint64_t src,

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

729

ib->ptr[ib->length_dw++] = lower_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

730

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

744

static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

752

ib->ptr[ib->length_dw++] = lower_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

753

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

774

static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

780

ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

781

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

654

uint64_t pe, uint64_t src,

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

665

ib->ptr[ib->length_dw++] = lower_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

666

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

680

static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

688

ib->ptr[ib->length_dw++] = pe;

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

689

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

710

static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

716

ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

717

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

927

uint64_t pe, uint64_t src,

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

938

ib->ptr[ib->length_dw++] = lower_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

939

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

953

static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

961

ib->ptr[ib->length_dw++] = lower_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

962

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

983

static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

989

ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

990

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1587

uint64_t pe, uint64_t src,

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1598

ib->ptr[ib->length_dw++] = lower_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1599

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1614

static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1622

ib->ptr[ib->length_dw++] = lower_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1623

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1645

uint64_t pe,

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1651

ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1652

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

1183

uint64_t pe, uint64_t src,

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

1194

ib->ptr[ib->length_dw++] = lower_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

1195

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

1210

static void sdma_v4_4_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

1218

ib->ptr[ib->length_dw++] = lower_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

1219

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

1241

uint64_t pe,

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

1247

ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

1248

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1155

uint64_t pe, uint64_t src,

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1166

ib->ptr[ib->length_dw++] = lower_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1167

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1182

static void sdma_v5_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1190

ib->ptr[ib->length_dw++] = lower_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1191

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1213

uint64_t pe,

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1219

ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1220

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1054

uint64_t pe, uint64_t src,

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1065

ib->ptr[ib->length_dw++] = lower_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1066

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1081

static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1089

ib->ptr[ib->length_dw++] = lower_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1090

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1112

uint64_t pe,

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1118

ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1119

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

1061

uint64_t pe, uint64_t src,

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

1072

ib->ptr[ib->length_dw++] = lower_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

1073

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

1088

static void sdma_v6_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

1096

ib->ptr[ib->length_dw++] = lower_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

1097

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

1119

uint64_t pe,

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

1125

ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

1126

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

1077

uint64_t pe, uint64_t src,

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

1090

ib->ptr[ib->length_dw++] = lower_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

1091

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

1107

static void sdma_v7_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

1115

ib->ptr[ib->length_dw++] = lower_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

1116

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

1138

uint64_t pe,

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

1144

ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

1145

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

1067

uint64_t pe, uint64_t src,

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

1079

ib->ptr[ib->length_dw++] = lower_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

1080

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

1095

static void sdma_v7_1_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

1103

ib->ptr[ib->length_dw++] = lower_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

1104

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

1126

uint64_t pe,

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

1141

ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

1142

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/si_dma.c

323

uint64_t pe, uint64_t src,

drivers/gpu/drm/amd/amdgpu/si_dma.c

330

ib->ptr[ib->length_dw++] = lower_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/si_dma.c

332

ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;

drivers/gpu/drm/amd/amdgpu/si_dma.c

347

static void si_dma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,

drivers/gpu/drm/amd/amdgpu/si_dma.c

354

ib->ptr[ib->length_dw++] = lower_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/si_dma.c

355

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

drivers/gpu/drm/amd/amdgpu/si_dma.c

376

uint64_t pe,

drivers/gpu/drm/amd/amdgpu/si_dma.c

395

ib->ptr[ib->length_dw++] = pe; /* dst addr */

drivers/gpu/drm/amd/amdgpu/si_dma.c

396

ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;

drivers/gpu/drm/amd/amdgpu/si_dma.c

403

pe += ndw * 4;

drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c

588

u8 vs, pe;

drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c

592

pe = (training_lane & DP_TRAIN_PRE_EMPHASIS_MASK) >>

drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c

595

phy_cfg.dp.pre[lane] = pe;

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

956

char pe[8] = "0/0/0/0";

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

961

pe[i * 2] = '0' + phy_cfg->dp.pre[i];

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

965

pe[i * 2 - 1] = '\0';

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

970

vs, pe);

drivers/gpu/drm/bridge/synopsys/dw-dp.c

560

unsigned int *vs, *pe;

drivers/gpu/drm/bridge/synopsys/dw-dp.c

565

pe = train_set->pre_emphasis;

drivers/gpu/drm/bridge/synopsys/dw-dp.c

569

phy_cfg.dp.pre[i] = pe[i];

drivers/gpu/drm/bridge/synopsys/dw-dp.c

582

(pe[i] << DP_TRAIN_PRE_EMPHASIS_SHIFT);

drivers/gpu/drm/i915/gem/i915_gem_context.c

1199

struct i915_gem_proto_engine *pe)

drivers/gpu/drm/i915/gem/i915_gem_context.c

1213

switch (pe[n].type) {

drivers/gpu/drm/i915/gem/i915_gem_context.c

1215

ce = intel_context_create(pe[n].engine);

drivers/gpu/drm/i915/gem/i915_gem_context.c

1219

ce = intel_engine_create_virtual(pe[n].siblings,

drivers/gpu/drm/i915/gem/i915_gem_context.c

1220

pe[n].num_siblings, 0);

drivers/gpu/drm/i915/gem/i915_gem_context.c

1224

ce = intel_engine_create_parallel(pe[n].siblings,

drivers/gpu/drm/i915/gem/i915_gem_context.c

1225

pe[n].num_siblings,

drivers/gpu/drm/i915/gem/i915_gem_context.c

1226

pe[n].width);

drivers/gpu/drm/i915/gem/i915_gem_context.c

1231

GEM_WARN_ON(pe[n].type != I915_GEM_ENGINE_TYPE_INVALID);

drivers/gpu/drm/i915/gem/i915_gem_context.c

1242

ret = intel_context_set_gem(ce, ctx, pe->sseu);

drivers/gpu/drm/i915/gem/i915_gem_context.c

1248

ret = intel_context_set_gem(child, ctx, pe->sseu);

drivers/gpu/drm/i915/gem/i915_gem_context.c

1264

if (pe[n].type == I915_GEM_ENGINE_TYPE_PARALLEL) {

drivers/gpu/drm/i915/gem/i915_gem_context.c

843

struct i915_gem_proto_engine *pe;

drivers/gpu/drm/i915/gem/i915_gem_context.c

849

pe = &pc->user_engines[idx];

drivers/gpu/drm/i915/gem/i915_gem_context.c

852

if (pe->engine->class != RENDER_CLASS)

drivers/gpu/drm/i915/gem/i915_gem_context.c

855

sseu = &pe->sseu;

drivers/gpu/drm/imx/dc/dc-crtc.c

182

ret = pm_runtime_resume_and_get(dc_drm->pe->dev);

drivers/gpu/drm/imx/dc/dc-crtc.c

316

pm_runtime_put(dc_drm->pe->dev);

drivers/gpu/drm/imx/dc/dc-crtc.c

502

struct dc_pe *pe = dc_drm->pe;

drivers/gpu/drm/imx/dc/dc-crtc.c

513

dc_crtc->cf_cont = pe->cf_cont[crtc_index];

drivers/gpu/drm/imx/dc/dc-crtc.c

514

dc_crtc->cf_safe = pe->cf_safe[crtc_index];

drivers/gpu/drm/imx/dc/dc-crtc.c

515

dc_crtc->ed_cont = pe->ed_cont[crtc_index];

drivers/gpu/drm/imx/dc/dc-crtc.c

516

dc_crtc->ed_safe = pe->ed_safe[crtc_index];

drivers/gpu/drm/imx/dc/dc-drv.h

50

struct dc_pe *pe;

drivers/gpu/drm/imx/dc/dc-pe.c

100

struct dc_pe *pe = dev_get_drvdata(dev);

drivers/gpu/drm/imx/dc/dc-pe.c

102

clk_disable_unprepare(pe->clk_axi);

drivers/gpu/drm/imx/dc/dc-pe.c

109

struct dc_pe *pe = dev_get_drvdata(dev);

drivers/gpu/drm/imx/dc/dc-pe.c

112

ret = clk_prepare_enable(pe->clk_axi);

drivers/gpu/drm/imx/dc/dc-pe.c

118

for (i = 0; i < ARRAY_SIZE(pe->cf_safe); i++)

drivers/gpu/drm/imx/dc/dc-pe.c

119

dc_cf_init(pe->cf_safe[i]);

drivers/gpu/drm/imx/dc/dc-pe.c

121

for (i = 0; i < ARRAY_SIZE(pe->cf_cont); i++)

drivers/gpu/drm/imx/dc/dc-pe.c

122

dc_cf_init(pe->cf_cont[i]);

drivers/gpu/drm/imx/dc/dc-pe.c

124

for (i = 0; i < ARRAY_SIZE(pe->ed_safe); i++)

drivers/gpu/drm/imx/dc/dc-pe.c

125

dc_ed_init(pe->ed_safe[i]);

drivers/gpu/drm/imx/dc/dc-pe.c

127

for (i = 0; i < ARRAY_SIZE(pe->ed_cont); i++)

drivers/gpu/drm/imx/dc/dc-pe.c

128

dc_ed_init(pe->ed_cont[i]);

drivers/gpu/drm/imx/dc/dc-pe.c

130

for (i = 0; i < ARRAY_SIZE(pe->fu_disp); i++)

drivers/gpu/drm/imx/dc/dc-pe.c

131

pe->fu_disp[i]->ops.init(pe->fu_disp[i]);

drivers/gpu/drm/imx/dc/dc-pe.c

133

for (i = 0; i < ARRAY_SIZE(pe->lb); i++)

drivers/gpu/drm/imx/dc/dc-pe.c

134

dc_lb_init(pe->lb[i]);

drivers/gpu/drm/imx/dc/dc-pe.c

23

struct dc_pe *pe;

drivers/gpu/drm/imx/dc/dc-pe.c

26

pe = devm_kzalloc(dev, sizeof(*pe), GFP_KERNEL);

drivers/gpu/drm/imx/dc/dc-pe.c

27

if (!pe)

drivers/gpu/drm/imx/dc/dc-pe.c

30

pe->clk_axi = devm_clk_get(dev, NULL);

drivers/gpu/drm/imx/dc/dc-pe.c

31

if (IS_ERR(pe->clk_axi))

drivers/gpu/drm/imx/dc/dc-pe.c

32

return dev_err_probe(dev, PTR_ERR(pe->clk_axi),

drivers/gpu/drm/imx/dc/dc-pe.c

35

pe->dev = dev;

drivers/gpu/drm/imx/dc/dc-pe.c

37

dev_set_drvdata(dev, pe);

drivers/gpu/drm/imx/dc/dc-pe.c

43

dc_drm->pe = pe;

drivers/gpu/drm/imx/dc/dc-pe.c

56

struct dc_pe *pe = dc_drm->pe;

drivers/gpu/drm/imx/dc/dc-pe.c

60

pe->cf_safe[i] = dc_drm->cf_safe[i];

drivers/gpu/drm/imx/dc/dc-pe.c

61

pe->cf_cont[i] = dc_drm->cf_cont[i];

drivers/gpu/drm/imx/dc/dc-pe.c

62

pe->ed_safe[i] = dc_drm->ed_safe[i];

drivers/gpu/drm/imx/dc/dc-pe.c

63

pe->ed_cont[i] = dc_drm->ed_cont[i];

drivers/gpu/drm/imx/dc/dc-pe.c

67

pe->fu_disp[i] = dc_drm->fu_disp[i];

drivers/gpu/drm/imx/dc/dc-pe.c

70

pe->lb[i] = dc_drm->lb[i];

drivers/gpu/drm/imx/dc/dc-plane.c

218

dc_plane->fu = dc_drm->pe->fu_disp[plane->index];

drivers/gpu/drm/imx/dc/dc-plane.c

219

dc_plane->cf = dc_drm->pe->cf_cont[plane->index];

drivers/gpu/drm/imx/dc/dc-plane.c

220

dc_plane->lb = dc_drm->pe->lb[plane->index];

drivers/gpu/drm/imx/dc/dc-plane.c

221

dc_plane->ed = dc_drm->pe->ed_cont[plane->index];

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h

277

struct dpu_drm_pix_ext_v1 pe;

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

745

struct pixel_ext *pe,

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

809

src_w, pe->left, pe->right,

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

810

src_h, pe->top, pe->bottom);

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

851

struct pixel_ext pe = { { 0 } };

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

917

pe.left, pe.right, true);

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

919

pe.top, pe.bottom, false);

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

936

mdp5_hwpipe_mode_set(mdp5_kms, hwpipe, fb, &step, &pe,

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

942

mdp5_hwpipe_mode_set(mdp5_kms, right_hwpipe, fb, &step, &pe,

drivers/gpu/drm/nouveau/include/nvif/if0012.h

252

__u8 pe[4];

drivers/gpu/drm/nouveau/include/nvif/outp.h

110

int nvif_outp_dp_drive(struct nvif_outp *, u8 link_nr, u8 pe[4], u8 vs[4]);

drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dp.h

26

u8 pe;

drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dp.h

34

nvbios_dpcfg_match(struct nvkm_bios *, u16 outp, u8 pc, u8 vs, u8 pe,

drivers/gpu/drm/nouveau/nouveau_dp.c

372

u8 pe[4], vs[4];

drivers/gpu/drm/nouveau/nouveau_dp.c

378

pe[i] = drm_dp_get_adjust_request_pre_emphasis(stat, i) >>

drivers/gpu/drm/nouveau/nouveau_dp.c

384

ret = nvif_outp_dp_drive(&outp->outp, outp->dp.lt.nr, pe, vs);

drivers/gpu/drm/nouveau/nvif/outp.c

104

memcpy(args.pe, pe, sizeof(args.pe));

drivers/gpu/drm/nouveau/nvif/outp.c

97

nvif_outp_dp_drive(struct nvif_outp *outp, u8 link_nr, u8 pe[4], u8 vs[4])

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

181

ior->func->dp->drive(ior, i, ocfg.pc, ocfg.dc, ocfg.pe, ocfg.tx_pu);

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

473

nvkm_dp_drive(struct nvkm_outp *outp, u8 lanes, u8 pe[4], u8 vs[4])

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

477

.stat[4] = (pe[0] << 2) | (vs[0] << 0) |

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

478

(pe[1] << 6) | (vs[1] << 4),

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

479

.stat[5] = (pe[2] << 2) | (vs[2] << 0) |

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

480

(pe[3] << 6) | (vs[3] << 4),

drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c

64

g94_sor_dp_drive(struct nvkm_ior *sor, int ln, int pc, int dc, int pe, int pu)

drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c

78

nvkm_wr32(device, 0x61c120 + loff, data[1] | (pe << shift));

drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c

129

gf119_sor_dp_drive(struct nvkm_ior *sor, int ln, int pc, int dc, int pe, int pu)

drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c

143

nvkm_wr32(device, 0x61c120 + loff, data[1] | (pe << shift));

drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.c

34

gm200_sor_dp_drive(struct nvkm_ior *sor, int ln, int pc, int dc, int pe, int pu)

drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.c

50

nvkm_wr32(device, 0x61c120 + loff, data[1] | (pe << shift));

drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h

86

int dc, int pe, int tx_pu);

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.h

113

int (*drive)(struct nvkm_outp *, u8 lanes, u8 pe[4], u8 vs[4]);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

104

return outp->func->dp.drive(outp, args->v0.lanes, args->v0.pe, args->v0.vs);

drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c

182

info->pe = nvbios_rd08(bios, data + 0x03);

drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c

190

info->pe = nvbios_rd08(bios, data + 0x02);

drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c

195

info->pe = nvbios_rd08(bios, data + 0x01);

drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c

207

nvbios_dpcfg_match(struct nvkm_bios *bios, u16 outp, u8 pc, u8 vs, u8 pe,

drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c

216

idx = (pc * 10) + vsoff[vs] + pe;

drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c

226

nvbios_rd08(bios, data + 0x01) == pe)

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

945

r535_dp_drive(struct nvkm_outp *outp, u8 lanes, u8 pe[4], u8 vs[4])

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

958

ctrl->data[i] = NVVAL(NV0073_CTRL, DP_LANE_DATA, PREEMPHASIS, pe[i]) |

drivers/gpu/drm/radeon/cik_sdma.c

804

uint64_t pe, uint64_t src,

drivers/gpu/drm/radeon/cik_sdma.c

818

ib->ptr[ib->length_dw++] = lower_32_bits(pe);

drivers/gpu/drm/radeon/cik_sdma.c

819

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

drivers/gpu/drm/radeon/cik_sdma.c

821

pe += bytes;

drivers/gpu/drm/radeon/cik_sdma.c

842

uint64_t pe,

drivers/gpu/drm/radeon/cik_sdma.c

857

ib->ptr[ib->length_dw++] = pe;

drivers/gpu/drm/radeon/cik_sdma.c

858

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

drivers/gpu/drm/radeon/cik_sdma.c

860

for (; ndw > 0; ndw -= 2, --count, pe += 8) {

drivers/gpu/drm/radeon/cik_sdma.c

891

uint64_t pe,

drivers/gpu/drm/radeon/cik_sdma.c

910

ib->ptr[ib->length_dw++] = pe; /* dst addr */

drivers/gpu/drm/radeon/cik_sdma.c

911

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

drivers/gpu/drm/radeon/cik_sdma.c

920

pe += ndw * 8;

drivers/gpu/drm/radeon/ni_dma.c

316

uint64_t pe, uint64_t src,

drivers/gpu/drm/radeon/ni_dma.c

328

ib->ptr[ib->length_dw++] = lower_32_bits(pe);

drivers/gpu/drm/radeon/ni_dma.c

330

ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;

drivers/gpu/drm/radeon/ni_dma.c

333

pe += ndw * 4;

drivers/gpu/drm/radeon/ni_dma.c

354

uint64_t pe,

drivers/gpu/drm/radeon/ni_dma.c

369

ib->ptr[ib->length_dw++] = pe;

drivers/gpu/drm/radeon/ni_dma.c

370

ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;

drivers/gpu/drm/radeon/ni_dma.c

371

for (; ndw > 0; ndw -= 2, --count, pe += 8) {

drivers/gpu/drm/radeon/ni_dma.c

402

uint64_t pe,

drivers/gpu/drm/radeon/ni_dma.c

421

ib->ptr[ib->length_dw++] = pe; /* dst addr */

drivers/gpu/drm/radeon/ni_dma.c

422

ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;

drivers/gpu/drm/radeon/ni_dma.c

430

pe += ndw * 4;

drivers/gpu/drm/radeon/radeon.h

1863

uint64_t pe, uint64_t src,

drivers/gpu/drm/radeon/radeon.h

1867

uint64_t pe,

drivers/gpu/drm/radeon/radeon.h

1872

uint64_t pe,

drivers/gpu/drm/radeon/radeon.h

2704

#define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))

drivers/gpu/drm/radeon/radeon.h

2705

#define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))

drivers/gpu/drm/radeon/radeon.h

2706

#define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))

drivers/gpu/drm/radeon/radeon_asic.h

625

uint64_t pe, uint64_t src,

drivers/gpu/drm/radeon/radeon_asic.h

629

uint64_t pe,

drivers/gpu/drm/radeon/radeon_asic.h

634

uint64_t pe,

drivers/gpu/drm/radeon/radeon_asic.h

731

uint64_t pe, uint64_t src,

drivers/gpu/drm/radeon/radeon_asic.h

735

uint64_t pe,

drivers/gpu/drm/radeon/radeon_asic.h

740

uint64_t pe,

drivers/gpu/drm/radeon/radeon_asic.h

833

uint64_t pe, uint64_t src,

drivers/gpu/drm/radeon/radeon_asic.h

837

uint64_t pe,

drivers/gpu/drm/radeon/radeon_asic.h

842

uint64_t pe,

drivers/gpu/drm/radeon/radeon_trace.h

103

__entry->pe, __entry->addr, __entry->incr,

drivers/gpu/drm/radeon/radeon_trace.h

84

TP_PROTO(uint64_t pe, uint64_t addr, unsigned count,

drivers/gpu/drm/radeon/radeon_trace.h

86

TP_ARGS(pe, addr, count, incr, flags),

drivers/gpu/drm/radeon/radeon_trace.h

88

__field(u64, pe)

drivers/gpu/drm/radeon/radeon_trace.h

96

__entry->pe = pe;

drivers/gpu/drm/radeon/radeon_vm.c

359

uint64_t pe,

drivers/gpu/drm/radeon/radeon_vm.c

363

trace_radeon_vm_set_page(pe, addr, count, incr, flags);

drivers/gpu/drm/radeon/radeon_vm.c

367

radeon_asic_vm_copy_pages(rdev, ib, pe, src, count);

drivers/gpu/drm/radeon/radeon_vm.c

370

radeon_asic_vm_write_pages(rdev, ib, pe, addr,

drivers/gpu/drm/radeon/radeon_vm.c

374

radeon_asic_vm_set_pages(rdev, ib, pe, addr,

drivers/gpu/drm/radeon/si_dma.c

106

uint64_t pe,

drivers/gpu/drm/radeon/si_dma.c

120

ib->ptr[ib->length_dw++] = pe;

drivers/gpu/drm/radeon/si_dma.c

121

ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;

drivers/gpu/drm/radeon/si_dma.c

122

for (; ndw > 0; ndw -= 2, --count, pe += 8) {

drivers/gpu/drm/radeon/si_dma.c

153

uint64_t pe,

drivers/gpu/drm/radeon/si_dma.c

172

ib->ptr[ib->length_dw++] = pe; /* dst addr */

drivers/gpu/drm/radeon/si_dma.c

173

ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;

drivers/gpu/drm/radeon/si_dma.c

180

pe += ndw * 4;

drivers/gpu/drm/radeon/si_dma.c

70

uint64_t pe, uint64_t src,

drivers/gpu/drm/radeon/si_dma.c

80

ib->ptr[ib->length_dw++] = lower_32_bits(pe);

drivers/gpu/drm/radeon/si_dma.c

82

ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;

drivers/gpu/drm/radeon/si_dma.c

85

pe += bytes;

drivers/gpu/drm/tegra/dp.c

402

unsigned int lanes = link->lanes, *vs, *pe, *pc, i;

drivers/gpu/drm/tegra/dp.c

414

pe = request->pre_emphasis;

drivers/gpu/drm/tegra/dp.c

420

DP_TRAIN_PRE_EMPHASIS_LEVEL(pe[i]);

drivers/gpu/drm/tegra/sor.c

815

u8 pe = link->train.request.pre_emphasis[i];

drivers/gpu/drm/tegra/sor.c

819

voltage_swing |= soc->voltage_swing[pc][vs][pe] << shift;

drivers/gpu/drm/tegra/sor.c

820

pre_emphasis |= soc->pre_emphasis[pc][vs][pe] << shift;

drivers/gpu/drm/tegra/sor.c

821

post_cursor |= soc->post_cursor[pc][vs][pe] << shift;

drivers/gpu/drm/tegra/sor.c

823

if (sor->soc->tx_pu[pc][vs][pe] > tx_pu)

drivers/gpu/drm/tegra/sor.c

824

tx_pu = sor->soc->tx_pu[pc][vs][pe];

drivers/hwtracing/coresight/coresight-etm4x-sysfs.c

481

static DEVICE_ATTR_RW(pe);

drivers/hwtracing/stm/core.c

381

struct stm_pdrv_entry *pe;

drivers/hwtracing/stm/core.c

389

list_for_each_entry(pe, &stm_pdrv_head, entry) {

drivers/hwtracing/stm/core.c

390

if (!strcmp(name, pe->pdrv->name))

drivers/hwtracing/stm/core.c

391

return pe;

drivers/hwtracing/stm/core.c

399

struct stm_pdrv_entry *pe = NULL;

drivers/hwtracing/stm/core.c

409

pe = kzalloc_obj(*pe);

drivers/hwtracing/stm/core.c

410

if (!pe)

drivers/hwtracing/stm/core.c

414

pe->node_type = get_policy_node_type(pdrv->policy_attr);

drivers/hwtracing/stm/core.c

415

if (!pe->node_type)

drivers/hwtracing/stm/core.c

419

list_add_tail(&pe->entry, &stm_pdrv_head);

drivers/hwtracing/stm/core.c

420

pe->pdrv = pdrv;

drivers/hwtracing/stm/core.c

427

kfree(pe);

drivers/hwtracing/stm/core.c

435

struct stm_pdrv_entry *pe, *iter;

drivers/hwtracing/stm/core.c

439

list_for_each_entry_safe(pe, iter, &stm_pdrv_head, entry) {

drivers/hwtracing/stm/core.c

440

if (pe->pdrv == pdrv) {

drivers/hwtracing/stm/core.c

441

list_del(&pe->entry);

drivers/hwtracing/stm/core.c

443

if (pe->node_type) {

drivers/hwtracing/stm/core.c

444

kfree(pe->node_type->ct_attrs);

drivers/hwtracing/stm/core.c

445

kfree(pe->node_type);

drivers/hwtracing/stm/core.c

447

kfree(pe);

drivers/hwtracing/stm/core.c

470

const struct stm_pdrv_entry *pe;

drivers/hwtracing/stm/core.c

474

pe = __stm_lookup_protocol(name);

drivers/hwtracing/stm/core.c

475

if (pe && pe->pdrv && stm_get_protocol(pe->pdrv)) {

drivers/hwtracing/stm/core.c

476

*pdrv = pe->pdrv;

drivers/hwtracing/stm/core.c

477

*node_type = pe->node_type;

drivers/hwtracing/stm/core.c

482

return pe ? 0 : -ENOENT;

drivers/iommu/intel/pasid.c

184

struct pasid_entry *pe;

drivers/iommu/intel/pasid.c

186

pe = intel_pasid_get_entry(dev, pasid);

drivers/iommu/intel/pasid.c

187

if (WARN_ON(!pe))

drivers/iommu/intel/pasid.c

190

if (fault_ignore && pasid_pte_is_present(pe))

drivers/iommu/intel/pasid.c

191

pasid_clear_entry_with_fpd(pe);

drivers/iommu/intel/pasid.c

193

pasid_clear_entry(pe);

drivers/iommu/intel/pasid.h

100

static inline void pasid_clear_entry_with_fpd(struct pasid_entry *pe)

drivers/iommu/intel/pasid.h

102

WRITE_ONCE(pe->val[0], PASID_PTE_FPD);

drivers/iommu/intel/pasid.h

103

WRITE_ONCE(pe->val[1], 0);

drivers/iommu/intel/pasid.h

104

WRITE_ONCE(pe->val[2], 0);

drivers/iommu/intel/pasid.h

105

WRITE_ONCE(pe->val[3], 0);

drivers/iommu/intel/pasid.h

106

WRITE_ONCE(pe->val[4], 0);

drivers/iommu/intel/pasid.h

107

WRITE_ONCE(pe->val[5], 0);

drivers/iommu/intel/pasid.h

108

WRITE_ONCE(pe->val[6], 0);

drivers/iommu/intel/pasid.h

109

WRITE_ONCE(pe->val[7], 0);

drivers/iommu/intel/pasid.h

130

pasid_set_domain_id(struct pasid_entry *pe, u64 value)

drivers/iommu/intel/pasid.h

132

pasid_set_bits(&pe->val[1], GENMASK_ULL(15, 0), value);

drivers/iommu/intel/pasid.h

139

pasid_get_domain_id(struct pasid_entry *pe)

drivers/iommu/intel/pasid.h

141

return (u16)(READ_ONCE(pe->val[1]) & GENMASK_ULL(15, 0));

drivers/iommu/intel/pasid.h

149

pasid_set_slptr(struct pasid_entry *pe, u64 value)

drivers/iommu/intel/pasid.h

151

pasid_set_bits(&pe->val[0], VTD_PAGE_MASK, value);

drivers/iommu/intel/pasid.h

159

pasid_set_address_width(struct pasid_entry *pe, u64 value)

drivers/iommu/intel/pasid.h

161

pasid_set_bits(&pe->val[0], GENMASK_ULL(4, 2), value << 2);

drivers/iommu/intel/pasid.h

169

pasid_set_translation_type(struct pasid_entry *pe, u64 value)

drivers/iommu/intel/pasid.h

171

pasid_set_bits(&pe->val[0], GENMASK_ULL(8, 6), value << 6);

drivers/iommu/intel/pasid.h

178

static inline void pasid_set_fault_enable(struct pasid_entry *pe)

drivers/iommu/intel/pasid.h

180

pasid_set_bits(&pe->val[0], 1 << 1, 0);

drivers/iommu/intel/pasid.h

188

static inline void pasid_set_ssade(struct pasid_entry *pe)

drivers/iommu/intel/pasid.h

190

pasid_set_bits(&pe->val[0], 1 << 9, 1 << 9);

drivers/iommu/intel/pasid.h

198

static inline void pasid_clear_ssade(struct pasid_entry *pe)

drivers/iommu/intel/pasid.h

200

pasid_set_bits(&pe->val[0], 1 << 9, 0);

drivers/iommu/intel/pasid.h

208

static inline bool pasid_get_ssade(struct pasid_entry *pe)

drivers/iommu/intel/pasid.h

210

return pasid_get_bits(&pe->val[0]) & (1 << 9);

drivers/iommu/intel/pasid.h

217

static inline void pasid_set_sre(struct pasid_entry *pe)

drivers/iommu/intel/pasid.h

219

pasid_set_bits(&pe->val[2], 1 << 0, 1);

drivers/iommu/intel/pasid.h

226

static inline void pasid_set_wpe(struct pasid_entry *pe)

drivers/iommu/intel/pasid.h

228

pasid_set_bits(&pe->val[2], 1 << 4, 1 << 4);

drivers/iommu/intel/pasid.h

235

static inline void pasid_set_present(struct pasid_entry *pe)

drivers/iommu/intel/pasid.h

238

pasid_set_bits(&pe->val[0], 1 << 0, 1);

drivers/iommu/intel/pasid.h

248

static inline void pasid_clear_present(struct pasid_entry *pe)

drivers/iommu/intel/pasid.h

250

pasid_set_bits(&pe->val[0], 1 << 0, 0);

drivers/iommu/intel/pasid.h

258

static inline void pasid_set_page_snoop(struct pasid_entry *pe, bool value)

drivers/iommu/intel/pasid.h

260

pasid_set_bits(&pe->val[1], 1 << 23, value << 23);

drivers/iommu/intel/pasid.h

268

pasid_set_pgsnp(struct pasid_entry *pe)

drivers/iommu/intel/pasid.h

270

pasid_set_bits(&pe->val[1], 1ULL << 24, 1ULL << 24);

drivers/iommu/intel/pasid.h

278

pasid_set_flptr(struct pasid_entry *pe, u64 value)

drivers/iommu/intel/pasid.h

280

pasid_set_bits(&pe->val[2], VTD_PAGE_MASK, value);

drivers/iommu/intel/pasid.h

288

pasid_set_flpm(struct pasid_entry *pe, u64 value)

drivers/iommu/intel/pasid.h

290

pasid_set_bits(&pe->val[2], GENMASK_ULL(3, 2), value << 2);

drivers/iommu/intel/pasid.h

297

static inline void pasid_set_eafe(struct pasid_entry *pe)

drivers/iommu/intel/pasid.h

299

pasid_set_bits(&pe->val[2], 1 << 7, 1 << 7);

drivers/iommu/intel/pasid.h

88

static inline void pasid_clear_entry(struct pasid_entry *pe)

drivers/iommu/intel/pasid.h

90

WRITE_ONCE(pe->val[0], 0);

drivers/iommu/intel/pasid.h

91

WRITE_ONCE(pe->val[1], 0);

drivers/iommu/intel/pasid.h

92

WRITE_ONCE(pe->val[2], 0);

drivers/iommu/intel/pasid.h

93

WRITE_ONCE(pe->val[3], 0);

drivers/iommu/intel/pasid.h

94

WRITE_ONCE(pe->val[4], 0);

drivers/iommu/intel/pasid.h

95

WRITE_ONCE(pe->val[5], 0);

drivers/iommu/intel/pasid.h

96

WRITE_ONCE(pe->val[6], 0);

drivers/iommu/intel/pasid.h

97

WRITE_ONCE(pe->val[7], 0);

drivers/md/dm-snap.c

1636

struct dm_snap_pending_exception *pe = context;

drivers/md/dm-snap.c

1638

struct dm_snapshot *s = pe->snap;

drivers/md/dm-snap.c

1645

dm_exception_table_lock_init(s, pe->e.old_chunk, &lock);

drivers/md/dm-snap.c

1664

*e = pe->e;

drivers/md/dm-snap.c

1687

if (__chunk_is_tracked(s, pe->e.old_chunk)) {

drivers/md/dm-snap.c

1689

__check_for_conflicting_io(s, pe->e.old_chunk);

drivers/md/dm-snap.c

1695

dm_remove_exception(&pe->e);

drivers/md/dm-snap.c

1699

snapshot_bios = bio_list_get(&pe->snapshot_bios);

drivers/md/dm-snap.c

1700

origin_bios = bio_list_get(&pe->origin_bios);

drivers/md/dm-snap.c

1701

full_bio = pe->full_bio;

drivers/md/dm-snap.c

1703

full_bio->bi_end_io = pe->full_bio_end_io;

drivers/md/dm-snap.c

1719

free_pending_exception(pe);

drivers/md/dm-snap.c

1722

static void complete_exception(struct dm_snap_pending_exception *pe)

drivers/md/dm-snap.c

1724

struct dm_snapshot *s = pe->snap;

drivers/md/dm-snap.c

1727

s->store->type->commit_exception(s->store, &pe->e, !pe->copy_error,

drivers/md/dm-snap.c

1728

pending_complete, pe);

drivers/md/dm-snap.c

1737

struct dm_snap_pending_exception *pe = context;

drivers/md/dm-snap.c

1738

struct dm_snapshot *s = pe->snap;

drivers/md/dm-snap.c

1740

pe->copy_error = read_err || write_err;

drivers/md/dm-snap.c

1742

if (pe->exception_sequence == s->exception_complete_sequence) {

drivers/md/dm-snap.c

1746

complete_exception(pe);

drivers/md/dm-snap.c

1750

pe = rb_entry(next, struct dm_snap_pending_exception,

drivers/md/dm-snap.c

1752

if (pe->exception_sequence != s->exception_complete_sequence)

drivers/md/dm-snap.c

1756

rb_erase(&pe->out_of_order_node, &s->out_of_order_tree);

drivers/md/dm-snap.c

1757

complete_exception(pe);

drivers/md/dm-snap.c

1769

BUG_ON(pe->exception_sequence == pe2->exception_sequence);

drivers/md/dm-snap.c

1770

if (pe->exception_sequence < pe2->exception_sequence)

drivers/md/dm-snap.c

1776

rb_link_node(&pe->out_of_order_node, parent, p);

drivers/md/dm-snap.c

1777

rb_insert_color(&pe->out_of_order_node, &s->out_of_order_tree);

drivers/md/dm-snap.c

1785

static void start_copy(struct dm_snap_pending_exception *pe)

drivers/md/dm-snap.c

1787

struct dm_snapshot *s = pe->snap;

drivers/md/dm-snap.c

1795

src.sector = chunk_to_sector(s->store, pe->e.old_chunk);

drivers/md/dm-snap.c

1799

dest.sector = chunk_to_sector(s->store, pe->e.new_chunk);

drivers/md/dm-snap.c

1804

dm_kcopyd_copy(s->kcopyd_client, &src, 1, &dest, 0, copy_callback, pe);

drivers/md/dm-snap.c

1814

static void start_full_bio(struct dm_snap_pending_exception *pe,

drivers/md/dm-snap.c

1817

struct dm_snapshot *s = pe->snap;

drivers/md/dm-snap.c

1820

pe->full_bio = bio;

drivers/md/dm-snap.c

1821

pe->full_bio_end_io = bio->bi_end_io;

drivers/md/dm-snap.c

1825

copy_callback, pe);

drivers/md/dm-snap.c

1852

struct dm_snap_pending_exception *pe, chunk_t chunk)

drivers/md/dm-snap.c

1854

pe->e.old_chunk = chunk;

drivers/md/dm-snap.c

1855

bio_list_init(&pe->origin_bios);

drivers/md/dm-snap.c

1856

bio_list_init(&pe->snapshot_bios);

drivers/md/dm-snap.c

1857

pe->started = 0;

drivers/md/dm-snap.c

1858

pe->full_bio = NULL;

drivers/md/dm-snap.c

1861

if (s->store->type->prepare_exception(s->store, &pe->e)) {

drivers/md/dm-snap.c

1863

free_pending_exception(pe);

drivers/md/dm-snap.c

1867

pe->exception_sequence = s->exception_start_sequence++;

drivers/md/dm-snap.c

1870

dm_insert_exception(&s->pending, &pe->e);

drivers/md/dm-snap.c

1872

return pe;

drivers/md/dm-snap.c

1885

struct dm_snap_pending_exception *pe, chunk_t chunk)

drivers/md/dm-snap.c

1891

free_pending_exception(pe);

drivers/md/dm-snap.c

1895

return __insert_pending_exception(s, pe, chunk);

drivers/md/dm-snap.c

1945

struct dm_snap_pending_exception *pe = NULL;

drivers/md/dm-snap.c

2023

pe = __lookup_pending_exception(s, chunk);

drivers/md/dm-snap.c

2024

if (!pe) {

drivers/md/dm-snap.c

2026

pe = alloc_pending_exception(s);

drivers/md/dm-snap.c

2031

free_pending_exception(pe);

drivers/md/dm-snap.c

2036

pe = __find_pending_exception(s, pe, chunk);

drivers/md/dm-snap.c

2037

if (!pe) {

drivers/md/dm-snap.c

2057

remap_exception(s, &pe->e, bio, chunk);

drivers/md/dm-snap.c

2061

if (!pe->started && io_overlaps_chunk(s, bio)) {

drivers/md/dm-snap.c

2062

pe->started = 1;

drivers/md/dm-snap.c

2067

start_full_bio(pe, bio);

drivers/md/dm-snap.c

2071

bio_list_add(&pe->snapshot_bios, bio);

drivers/md/dm-snap.c

2073

if (!pe->started) {

drivers/md/dm-snap.c

2075

pe->started = 1;

drivers/md/dm-snap.c

2080

start_copy(pe);

drivers/md/dm-snap.c

2431

struct dm_snap_pending_exception *pe, *pe2;

drivers/md/dm-snap.c

2464

pe = __lookup_pending_exception(snap, chunk);

drivers/md/dm-snap.c

2465

if (!pe) {

drivers/md/dm-snap.c

2476

pe = alloc_pending_exception(snap);

drivers/md/dm-snap.c

2484

free_pending_exception(pe);

drivers/md/dm-snap.c

2488

pe = __insert_pending_exception(snap, pe, chunk);

drivers/md/dm-snap.c

2489

if (!pe) {

drivers/md/dm-snap.c

2497

free_pending_exception(pe);

drivers/md/dm-snap.c

2498

pe = pe2;

drivers/md/dm-snap.c

2510

bio_list_add(&pe->origin_bios, bio);

drivers/md/dm-snap.c

2513

if (!pe->started) {

drivers/md/dm-snap.c

2514

pe->started = 1;

drivers/md/dm-snap.c

2515

pe_to_start_last = pe;

drivers/md/dm-snap.c

2519

if (!pe->started) {

drivers/md/dm-snap.c

2520

pe->started = 1;

drivers/md/dm-snap.c

2521

pe_to_start_now = pe;

drivers/md/dm-snap.c

747

struct dm_snap_pending_exception *pe = mempool_alloc(&s->pending_pool,

drivers/md/dm-snap.c

751

pe->snap = s;

drivers/md/dm-snap.c

753

return pe;

drivers/md/dm-snap.c

756

static void free_pending_exception(struct dm_snap_pending_exception *pe)

drivers/md/dm-snap.c

758

struct dm_snapshot *s = pe->snap;

drivers/md/dm-snap.c

760

mempool_free(pe, &s->pending_pool);

drivers/misc/ocxl/link.c

108

static void read_irq(struct spa *spa, u64 *dsisr, u64 *dar, u64 *pe)

drivers/misc/ocxl/link.c

115

*pe = reg & SPA_PE_MASK;

drivers/misc/ocxl/link.c

131

trace_ocxl_fault_ack(spa->spa_mem, spa->xsl_fault.pe,

drivers/misc/ocxl/link.c

195

struct ocxl_process_element *pe;

drivers/misc/ocxl/link.c

203

pe = spa->spa_mem + pe_handle;

drivers/misc/ocxl/link.c

204

pid = be32_to_cpu(pe->pid);

drivers/misc/ocxl/link.c

250

spa->xsl_fault.pe = pe_handle;

drivers/misc/ocxl/link.c

545

struct ocxl_process_element *pe;

drivers/misc/ocxl/link.c

555

pe = spa->spa_mem + pe_handle;

drivers/misc/ocxl/link.c

557

if (pe->software_state) {

drivers/misc/ocxl/link.c

574

memset(pe, 0, sizeof(struct ocxl_process_element));

drivers/misc/ocxl/link.c

575

pe->config_state = cpu_to_be64(calculate_cfg_state(pidr == 0));

drivers/misc/ocxl/link.c

576

pe->pasid = cpu_to_be32(pasid << (31 - 19));

drivers/misc/ocxl/link.c

577

pe->bdf = cpu_to_be16(bdf);

drivers/misc/ocxl/link.c

578

pe->lpid = cpu_to_be32(mfspr(SPRN_LPID));

drivers/misc/ocxl/link.c

579

pe->pid = cpu_to_be32(pidr);

drivers/misc/ocxl/link.c

580

pe->tid = cpu_to_be32(tidr);

drivers/misc/ocxl/link.c

581

pe->amr = cpu_to_be64(amr);

drivers/misc/ocxl/link.c

582

pe->software_state = cpu_to_be32(SPA_PE_VALID);

drivers/misc/ocxl/link.c

635

struct ocxl_process_element *pe;

drivers/misc/ocxl/link.c

642

pe = spa->spa_mem + pe_handle;

drivers/misc/ocxl/link.c

646

pe->tid = cpu_to_be32(tid);

drivers/misc/ocxl/link.c

671

struct ocxl_process_element *pe;

drivers/misc/ocxl/link.c

697

pe = spa->spa_mem + pe_handle;

drivers/misc/ocxl/link.c

701

if (!(be32_to_cpu(pe->software_state) & SPA_PE_VALID)) {

drivers/misc/ocxl/link.c

707

be32_to_cpu(pe->pid), be32_to_cpu(pe->tid));

drivers/misc/ocxl/link.c

709

memset(pe, 0, sizeof(struct ocxl_process_element));

drivers/misc/ocxl/link.c

71

u64 pe;

drivers/misc/ocxl/trace.h

135

TP_PROTO(void *spa, u64 pe, u64 dsisr, u64 dar, u64 tfc),

drivers/misc/ocxl/trace.h

136

TP_ARGS(spa, pe, dsisr, dar, tfc),

drivers/misc/ocxl/trace.h

140

__field(u64, pe)

drivers/misc/ocxl/trace.h

148

__entry->pe = pe;

drivers/misc/ocxl/trace.h

156

__entry->pe,

drivers/misc/ocxl/trace.h

164

TP_PROTO(void *spa, u64 pe, u64 dsisr, u64 dar, u64 tfc),

drivers/misc/ocxl/trace.h

165

TP_ARGS(spa, pe, dsisr, dar, tfc)

drivers/misc/ocxl/trace.h

169

TP_PROTO(void *spa, u64 pe, u64 dsisr, u64 dar, u64 tfc),

drivers/misc/ocxl/trace.h

170

TP_ARGS(spa, pe, dsisr, dar, tfc)

drivers/net/ethernet/intel/ice/ice_switch.c

4754

u8 pe, qr;

drivers/net/ethernet/intel/ice/ice_switch.c

4759

for (pe = 0; pe < lkup_exts->n_val_words; pe++) {

drivers/net/ethernet/intel/ice/ice_switch.c

4762

if (ar[qr].off == be[pe].off &&

drivers/net/ethernet/intel/ice/ice_switch.c

4763

ar[qr].prot_id == be[pe].prot_id &&

drivers/net/ethernet/intel/ice/ice_switch.c

4764

cr[qr] == de[pe])

drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c

248

struct mvpp2_prs_entry pe;

drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c

255

mvpp2_prs_init_from_hw(priv, &pe, tid);

drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c

257

pmap = mvpp2_prs_tcam_port_map_get(&pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c

265

mvpp2_prs_tcam_data_byte_get(&pe, 2, &byte[0], &enable[0]);

drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c

266

mvpp2_prs_tcam_data_byte_get(&pe, 3, &byte[1], &enable[1]);

drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c

282

struct mvpp2_prs_entry pe;

drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c

287

mvpp2_prs_init_from_hw(port->priv, &pe, i);

drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c

289

pmap = mvpp2_prs_tcam_port_map_get(&pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c

303

struct mvpp2_prs_entry pe;

drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c

316

mvpp2_prs_init_from_hw(priv, &pe, tid);

drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c

318

pmap = mvpp2_prs_tcam_port_map_get(&pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c

326

mvpp2_prs_tcam_data_byte_get(&pe, index, &da[index],

drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c

352

struct mvpp2_prs_entry pe;

drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c

355

mvpp2_prs_init_from_hw(entry->priv, &pe, entry->tid);

drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c

357

pmap = mvpp2_prs_tcam_port_map_get(&pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c

370

struct mvpp2_prs_entry pe;

drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c

373

mvpp2_prs_init_from_hw(entry->priv, &pe, entry->tid);

drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c

375

ai = pe.tcam[MVPP2_PRS_TCAM_AI_WORD] & MVPP2_PRS_AI_MASK;

drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c

376

ai_mask = (pe.tcam[MVPP2_PRS_TCAM_AI_WORD] >> 16) & MVPP2_PRS_AI_MASK;

drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c

388

struct mvpp2_prs_entry pe;

drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c

392

mvpp2_prs_init_from_hw(entry->priv, &pe, entry->tid);

drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c

395

mvpp2_prs_tcam_data_byte_get(&pe, i, &data[i], &mask[i]);

drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c

407

struct mvpp2_prs_entry pe;

drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c

409

mvpp2_prs_init_from_hw(entry->priv, &pe, entry->tid);

drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c

411

seq_printf(s, "%*phN\n", 14, pe.sram);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1002

memset(&pe, 0, sizeof(pe));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1003

mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1004

pe.index = tid;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1008

mvpp2_prs_tcam_data_byte_set(&pe, 0, MVPP2_PRS_IPV4_MC,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1010

mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_MCAST,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1015

mvpp2_prs_tcam_data_byte_set(&pe, 0, mask, mask);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1016

mvpp2_prs_tcam_data_byte_set(&pe, 1, mask, mask);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1017

mvpp2_prs_tcam_data_byte_set(&pe, 2, mask, mask);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1018

mvpp2_prs_tcam_data_byte_set(&pe, 3, mask, mask);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1019

mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_BCAST,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1027

mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1029

mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1033

mvpp2_prs_sram_shift_set(&pe, -12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1035

mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1038

mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1041

mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1042

mvpp2_prs_hw_write(priv, &pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1051

struct mvpp2_prs_entry pe;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1063

memset(&pe, 0, sizeof(pe));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1064

mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1065

pe.index = tid;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1068

mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1069

mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1070

mvpp2_prs_sram_ri_update(&pe, ri, ri_mask);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1071

mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1075

mvpp2_prs_tcam_data_byte_set(&pe, 0, proto, MVPP2_PRS_TCAM_PROTO_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1076

mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1079

mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1082

mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1083

mvpp2_prs_hw_write(priv, &pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1091

struct mvpp2_prs_entry pe;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1102

memset(&pe, 0, sizeof(pe));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1103

mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1104

pe.index = tid;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1107

mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1108

mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_MCAST,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1110

mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1113

mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1115

mvpp2_prs_tcam_data_byte_set(&pe, 0, MVPP2_PRS_IPV6_MC,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1117

mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1119

mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1122

mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1123

mvpp2_prs_hw_write(priv, &pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1158

struct mvpp2_prs_entry pe;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1162

memset(&pe, 0, sizeof(pe));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1163

mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1164

pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1167

mvpp2_prs_tcam_port_map_set(&pe, 0);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

117

static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu)

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1170

mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1171

mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1174

mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1175

mvpp2_prs_hw_write(priv, &pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1182

struct mvpp2_prs_entry pe;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1184

memset(&pe, 0, sizeof(pe));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1186

pe.index = MVPP2_PE_MH_DEFAULT;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1187

mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1188

mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

119

pe->tcam[MVPP2_PRS_TCAM_LU_WORD] &= ~MVPP2_PRS_TCAM_LU(MVPP2_PRS_LU_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1190

mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1193

mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1196

mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1197

mvpp2_prs_hw_write(priv, &pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

120

pe->tcam[MVPP2_PRS_TCAM_LU_WORD] &= ~MVPP2_PRS_TCAM_LU_EN(MVPP2_PRS_LU_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1200

pe.index = MVPP2_PE_MH_SKIP_PRS;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1201

mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1202

mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1204

mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1205

mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1208

mvpp2_prs_tcam_port_map_set(&pe, 0);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

121

pe->tcam[MVPP2_PRS_TCAM_LU_WORD] |= MVPP2_PRS_TCAM_LU(lu & MVPP2_PRS_LU_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1211

mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1212

mvpp2_prs_hw_write(priv, &pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

122

pe->tcam[MVPP2_PRS_TCAM_LU_WORD] |= MVPP2_PRS_TCAM_LU_EN(MVPP2_PRS_LU_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1220

struct mvpp2_prs_entry pe;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1222

memset(&pe, 0, sizeof(pe));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1225

pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1226

mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1228

mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1230

mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1231

mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1234

mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1237

mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1238

mvpp2_prs_hw_write(priv, &pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1250

struct mvpp2_prs_entry pe;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

126

static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1283

memset(&pe, 0, sizeof(pe));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1284

mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1285

pe.index = MVPP2_PE_DSA_DEFAULT;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1286

mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1289

mvpp2_prs_sram_shift_set(&pe, 0, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1290

mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1293

mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1296

mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1298

mvpp2_prs_hw_write(priv, &pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

130

pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] &= ~MVPP2_PRS_TCAM_PORT_EN(BIT(port));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1304

struct mvpp2_prs_entry pe;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1306

memset(&pe, 0, sizeof(pe));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1309

pe.index = MVPP2_PE_VID_FLTR_DEFAULT;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1310

mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VID);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1312

mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_EDSA_VID_AI_BIT);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1315

mvpp2_prs_sram_shift_set(&pe, MVPP2_VLAN_TAG_LEN,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1319

mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

132

pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] |= MVPP2_PRS_TCAM_PORT_EN(BIT(port));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1321

mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1324

mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1327

mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1328

mvpp2_prs_hw_write(priv, &pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1331

memset(&pe, 0, sizeof(pe));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1334

pe.index = MVPP2_PE_VID_EDSA_FLTR_DEFAULT;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1335

mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VID);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1337

mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_EDSA_VID_AI_BIT,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1341

mvpp2_prs_sram_shift_set(&pe, MVPP2_VLAN_TAG_EDSA_LEN,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1345

mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1347

mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1350

mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1353

mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1354

mvpp2_prs_hw_write(priv, &pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

136

static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1360

struct mvpp2_prs_entry pe;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1369

memset(&pe, 0, sizeof(pe));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1370

mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1371

pe.index = tid;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1373

mvpp2_prs_match_etype(&pe, 0, ETH_P_PPP_SES);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1375

mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1377

mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1378

mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1382

mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1383

priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1384

priv->prs_shadow[pe.index].finish = false;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1385

mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1387

mvpp2_prs_hw_write(priv, &pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

139

pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] &= ~MVPP2_PRS_TCAM_PORT(MVPP2_PRS_PORT_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1395

memset(&pe, 0, sizeof(pe));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1396

mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1397

pe.index = tid;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1399

mvpp2_prs_match_etype(&pe, 0, ETH_P_ARP);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

140

pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] &= ~MVPP2_PRS_TCAM_PORT_EN(MVPP2_PRS_PORT_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1402

mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1403

mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1404

mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1407

mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

141

pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] |= MVPP2_PRS_TCAM_PORT_EN(~ports & MVPP2_PRS_PORT_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1412

mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1413

priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1414

priv->prs_shadow[pe.index].finish = true;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1415

mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1417

mvpp2_prs_hw_write(priv, &pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1425

memset(&pe, 0, sizeof(pe));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1426

mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1427

pe.index = tid;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1429

mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1432

mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1433

mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1434

mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1439

mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1444

mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1445

priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1446

priv->prs_shadow[pe.index].finish = true;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1447

mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

145

unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe)

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1451

mvpp2_prs_hw_write(priv, &pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1460

memset(&pe, 0, sizeof(pe));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1461

mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1462

pe.index = tid;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1464

mvpp2_prs_match_etype(&pe, 0, ETH_P_IP);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1465

mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

147

return (~pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] >> 24) & MVPP2_PRS_PORT_MASK;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1470

mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1471

mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1474

mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN +

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1478

mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1483

mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1484

priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1485

priv->prs_shadow[pe.index].finish = false;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1486

mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1488

mvpp2_prs_hw_write(priv, &pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1497

memset(&pe, 0, sizeof(pe));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1498

mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1499

pe.index = tid;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1501

mvpp2_prs_match_etype(&pe, 0, ETH_P_IPV6);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1504

mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 +

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1507

mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1508

mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

151

static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1511

mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1515

mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1516

priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1517

priv->prs_shadow[pe.index].finish = false;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1518

mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1520

mvpp2_prs_hw_write(priv, &pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1523

memset(&pe, 0, sizeof(struct mvpp2_prs_entry));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1524

mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1525

pe.index = MVPP2_PE_ETH_TYPE_UN;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1528

mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1531

mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1532

mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1533

mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1536

mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1541

mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1542

priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1543

priv->prs_shadow[pe.index].finish = true;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1544

mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1546

mvpp2_prs_hw_write(priv, &pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1560

struct mvpp2_prs_entry pe;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

157

pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] &= ~(0xff << pos);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

158

pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] &= ~(MVPP2_PRS_TCAM_EN(0xff) << pos);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1588

memset(&pe, 0, sizeof(pe));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1589

mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

159

pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] |= byte << pos;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1590

pe.index = MVPP2_PE_VLAN_DBL;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1592

mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VID);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1595

mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1596

mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_DOUBLE,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1599

mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_DBL_VLAN_AI_BIT,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

160

pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] |= MVPP2_PRS_TCAM_EN(enable << pos);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1602

mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1605

mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1606

mvpp2_prs_hw_write(priv, &pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1609

memset(&pe, 0, sizeof(pe));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1610

mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1611

pe.index = MVPP2_PE_VLAN_NONE;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1613

mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1614

mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1618

mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1621

mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1622

mvpp2_prs_hw_write(priv, &pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1630

struct mvpp2_prs_entry pe;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

164

void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1640

memset(&pe, 0, sizeof(pe));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1641

mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1642

pe.index = tid;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1644

mvpp2_prs_match_etype(&pe, 0, PPP_IP);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1645

mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1650

mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1651

mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1654

mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN +

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1658

mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1662

mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1667

mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1668

mvpp2_prs_hw_write(priv, &pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1677

memset(&pe, 0, sizeof(pe));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1678

mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1679

pe.index = tid;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1681

mvpp2_prs_match_etype(&pe, 0, PPP_IPV6);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1683

mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1684

mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1687

mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 +

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1691

mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1696

mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1697

mvpp2_prs_hw_write(priv, &pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

170

*byte = (pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] >> pos) & 0xff;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1705

memset(&pe, 0, sizeof(pe));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1706

mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1707

pe.index = tid;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1709

mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

171

*enable = (pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] >> (pos + 16)) & 0xff;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1713

mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1714

mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1716

mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1721

mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1722

mvpp2_prs_hw_write(priv, &pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1730

struct mvpp2_prs_entry pe;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

175

static bool mvpp2_prs_tcam_data_cmp(struct mvpp2_prs_entry *pe, int offs,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1763

memset(&pe, 0, sizeof(pe));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1764

mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1765

pe.index = MVPP2_PE_IP4_PROTO_UN;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1768

mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1769

mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1772

mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, -4,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1774

mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1775

mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1778

mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1781

mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1784

mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1785

mvpp2_prs_hw_write(priv, &pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1788

memset(&pe, 0, sizeof(pe));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1789

mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1790

pe.index = MVPP2_PE_IP4_ADDR_UN;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1793

mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1795

mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1799

mvpp2_prs_sram_shift_set(&pe, -12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

180

tcam_data = pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] & 0xffff;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1801

mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UCAST,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1803

mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1806

mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1809

mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1810

mvpp2_prs_hw_write(priv, &pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1818

struct mvpp2_prs_entry pe;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

185

static void mvpp2_prs_tcam_ai_update(struct mvpp2_prs_entry *pe,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1861

memset(&pe, 0, sizeof(pe));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1862

mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1863

pe.index = tid;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1866

mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1867

mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1868

mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN |

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1873

mvpp2_prs_tcam_data_byte_set(&pe, 1, 0x00, MVPP2_PRS_IPV6_HOP_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1874

mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1878

mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1879

mvpp2_prs_hw_write(priv, &pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1882

memset(&pe, 0, sizeof(pe));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1883

mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1884

pe.index = MVPP2_PE_IP6_PROTO_UN;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1887

mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1888

mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1889

mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1892

mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1896

mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1899

mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1902

mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1903

mvpp2_prs_hw_write(priv, &pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1906

memset(&pe, 0, sizeof(struct mvpp2_prs_entry));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1907

mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1908

pe.index = MVPP2_PE_IP6_EXT_PROTO_UN;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1911

mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1912

mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1913

mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1916

mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_EXT_AI_BIT,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1919

mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1922

mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1923

mvpp2_prs_hw_write(priv, &pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1926

memset(&pe, 0, sizeof(struct mvpp2_prs_entry));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1927

mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1928

pe.index = MVPP2_PE_IP6_ADDR_UN;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1931

mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1932

mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UCAST,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1934

mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1937

mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1939

mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1941

mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1944

mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1945

mvpp2_prs_hw_write(priv, &pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

195

pe->tcam[MVPP2_PRS_TCAM_AI_WORD] |= BIT(i);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1954

struct mvpp2_prs_entry pe;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1965

__mvpp2_prs_init_from_hw(port->priv, &pe, tid);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1967

mvpp2_prs_tcam_data_byte_get(&pe, 2, &byte[0], &enable[0]);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1968

mvpp2_prs_tcam_data_byte_get(&pe, 3, &byte[1], &enable[1]);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

197

pe->tcam[MVPP2_PRS_TCAM_AI_WORD] &= ~BIT(i);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1989

struct mvpp2_prs_entry pe;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

1992

memset(&pe, 0, sizeof(pe));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

200

pe->tcam[MVPP2_PRS_TCAM_AI_WORD] |= MVPP2_PRS_TCAM_AI_EN(enable);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2019

mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VID);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2020

pe.index = tid;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2023

mvpp2_prs_tcam_port_map_set(&pe, 0);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2025

__mvpp2_prs_init_from_hw(priv, &pe, tid);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2029

mvpp2_prs_tcam_port_set(&pe, port->id, true);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2032

mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2035

mvpp2_prs_sram_shift_set(&pe, shift, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2038

mvpp2_prs_match_vid(&pe, MVPP2_PRS_VID_TCAM_BYTE, vid);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

204

static int mvpp2_prs_tcam_ai_get(struct mvpp2_prs_entry *pe)

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2041

mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2044

mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2045

mvpp2_prs_hw_write(priv, &pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

206

return pe->tcam[MVPP2_PRS_TCAM_AI_WORD] & MVPP2_PRS_AI_MASK;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

210

static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2110

struct mvpp2_prs_entry pe;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2115

memset(&pe, 0, sizeof(pe));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2119

pe.index = tid;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2127

mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VID);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

213

mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2130

mvpp2_prs_tcam_port_map_set(&pe, 0);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2133

mvpp2_prs_tcam_port_set(&pe, port->id, true);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2136

mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2139

mvpp2_prs_sram_shift_set(&pe, shift, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

214

mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2142

mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2146

mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2149

mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2150

mvpp2_prs_hw_write(priv, &pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

218

static void mvpp2_prs_match_vid(struct mvpp2_prs_entry *pe, int offset,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

22

static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

221

mvpp2_prs_tcam_data_byte_set(pe, offset + 0, (vid & 0xf00) >> 8, 0xf);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2218

static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

222

mvpp2_prs_tcam_data_byte_set(pe, offset + 1, vid & 0xff, 0xff);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2225

mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2241

struct mvpp2_prs_entry pe;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2254

__mvpp2_prs_init_from_hw(priv, &pe, tid);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2255

entry_pmap = mvpp2_prs_tcam_port_map_get(&pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2257

if (mvpp2_prs_mac_range_equals(&pe, da, mask) &&

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

226

static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2272

struct mvpp2_prs_entry pe;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2275

memset(&pe, 0, sizeof(pe));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

229

pe->sram[MVPP2_BIT_TO_WORD(bit_num)] |= (val << (MVPP2_BIT_IN_WORD(bit_num)));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2294

pe.index = tid;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2297

mvpp2_prs_tcam_port_map_set(&pe, 0);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2299

__mvpp2_prs_init_from_hw(priv, &pe, tid);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2302

mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2305

mvpp2_prs_tcam_port_set(&pe, port->id, add);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2308

pmap = mvpp2_prs_tcam_port_map_get(&pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2313

mvpp2_prs_hw_inv(priv, pe.index);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2314

priv->prs_shadow[pe.index].valid = false;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2319

mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2324

mvpp2_prs_tcam_data_byte_set(&pe, len, da[len], 0xff);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

233

static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2338

mvpp2_prs_sram_ri_update(&pe, ri, MVPP2_PRS_RI_L2_CAST_MASK |

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2340

mvpp2_prs_shadow_ri_set(priv, pe.index, ri, MVPP2_PRS_RI_L2_CAST_MASK |

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2344

mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2348

priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_MAC_DEF;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2349

mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2350

mvpp2_prs_hw_write(priv, &pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

236

pe->sram[MVPP2_BIT_TO_WORD(bit_num)] &= ~(val << (MVPP2_BIT_IN_WORD(bit_num)));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2390

struct mvpp2_prs_entry pe;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

240

static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2405

__mvpp2_prs_init_from_hw(priv, &pe, tid);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2407

pmap = mvpp2_prs_tcam_port_map_get(&pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2415

mvpp2_prs_tcam_data_byte_get(&pe, index, &da[index],

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2490

struct mvpp2_prs_entry pe;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2494

memset(&pe, 0, sizeof(pe));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

250

mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_OFFS + i,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2506

pe.index = tid;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2511

mvpp2_prs_sram_ai_update(&pe, flow, MVPP2_PRS_FLOW_ID_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2512

mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2515

mvpp2_prs_tcam_data_byte_set(&pe, i, ri_byte[i],

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2519

mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2520

mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2521

mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2522

mvpp2_prs_hw_write(priv, &pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

253

mvpp2_prs_sram_bits_clear(pe,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2531

struct mvpp2_prs_entry pe;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2534

memset(&pe, 0, sizeof(pe));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2551

pe.index = tid;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2554

mvpp2_prs_sram_ai_update(&pe, port->id, MVPP2_PRS_FLOW_ID_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2555

mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2558

mvpp2_prs_shadow_set(port->priv, pe.index, MVPP2_PRS_LU_FLOWS);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2560

__mvpp2_prs_init_from_hw(port->priv, &pe, tid);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2563

mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2564

mvpp2_prs_tcam_port_map_set(&pe, (1 << port->id));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

2565

mvpp2_prs_hw_write(port->priv, &pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

257

mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

262

static int mvpp2_prs_sram_ri_get(struct mvpp2_prs_entry *pe)

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

264

return pe->sram[MVPP2_PRS_SRAM_RI_WORD];

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

268

static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

278

mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_OFFS + i,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

28

if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

281

mvpp2_prs_sram_bits_clear(pe,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

285

mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

290

static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe)

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

297

bits = (pe->sram[ai_off] >> ai_shift) |

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

298

(pe->sram[ai_off + 1] << (32 - ai_shift));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

306

static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

311

mvpp2_prs_sram_bits_clear(pe, sram_next_off,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

313

mvpp2_prs_sram_bits_set(pe, sram_next_off, lu);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

319

static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

32

pe->tcam[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

324

mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

327

mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

331

pe->sram[MVPP2_BIT_TO_WORD(MVPP2_PRS_SRAM_SHIFT_OFFS)] |=

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

335

mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

337

mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

340

mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

346

static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

35

mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

352

mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

355

mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

359

mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

361

mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

365

mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

367

mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

37

mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram[i]);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

370

mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

372

mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

376

mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

382

struct mvpp2_prs_entry pe;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

393

__mvpp2_prs_init_from_hw(priv, &pe, tid);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

394

bits = mvpp2_prs_sram_ai_get(&pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

40

mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

42

mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam[i]);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

425

struct mvpp2_prs_entry pe;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

428

memset(&pe, 0, sizeof(pe));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

431

pe.index = MVPP2_PE_FC_DROP;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

432

mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

437

mvpp2_prs_tcam_data_byte_set(&pe, len, da[len], 0xff);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

439

mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

442

mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

443

mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

446

mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

449

mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

450

mvpp2_prs_hw_write(priv, &pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

456

struct mvpp2_prs_entry pe;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

460

__mvpp2_prs_init_from_hw(priv, &pe, MVPP2_PE_DROP_ALL);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

463

memset(&pe, 0, sizeof(pe));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

464

mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

465

pe.index = MVPP2_PE_DROP_ALL;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

468

mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

471

mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

472

mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

475

mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

478

mvpp2_prs_tcam_port_map_set(&pe, 0);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

482

mvpp2_prs_tcam_port_set(&pe, port, add);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

484

mvpp2_prs_hw_write(priv, &pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

49

struct mvpp2_prs_entry *pe, int tid)

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

492

struct mvpp2_prs_entry pe;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

511

__mvpp2_prs_init_from_hw(priv, &pe, tid);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

513

memset(&pe, 0, sizeof(pe));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

514

mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

515

pe.index = tid;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

518

mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

521

mvpp2_prs_sram_ri_update(&pe, ri, MVPP2_PRS_RI_L2_CAST_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

524

mvpp2_prs_tcam_data_byte_set(&pe, 0, cast_match,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

528

mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

532

mvpp2_prs_tcam_port_map_set(&pe, 0);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

535

mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

539

mvpp2_prs_tcam_port_set(&pe, port, add);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

541

mvpp2_prs_hw_write(priv, &pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

556

struct mvpp2_prs_entry pe;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

569

__mvpp2_prs_init_from_hw(priv, &pe, tid);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

572

memset(&pe, 0, sizeof(pe));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

573

mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

574

pe.index = tid;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

577

mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_DSA);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

58

memset(pe, 0, sizeof(*pe));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

581

mvpp2_prs_tcam_data_byte_set(&pe, 0,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

587

mvpp2_prs_sram_ai_update(&pe, 1,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

59

pe->index = tid;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

590

mvpp2_prs_sram_ai_update(&pe, 0,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

594

mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_SINGLE,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

597

mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VID);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

600

mvpp2_prs_sram_shift_set(&pe, shift,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

604

mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

606

mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

610

mvpp2_prs_tcam_port_map_set(&pe, 0);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

614

mvpp2_prs_tcam_port_set(&pe, port, add);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

616

mvpp2_prs_hw_write(priv, &pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

62

mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

623

struct mvpp2_prs_entry pe;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

64

pe->tcam[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

640

__mvpp2_prs_init_from_hw(priv, &pe, tid);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

643

memset(&pe, 0, sizeof(pe));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

644

mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

645

pe.index = tid;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

648

mvpp2_prs_match_etype(&pe, 0, ETH_P_EDSA);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

649

mvpp2_prs_match_etype(&pe, 2, 0);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

651

mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DSA_MASK,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

654

mvpp2_prs_sram_shift_set(&pe, 2 + MVPP2_ETH_TYPE_LEN + shift,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

658

mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_DSA);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

66

if (pe->tcam[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK)

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

662

mvpp2_prs_tcam_data_byte_set(&pe,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

667

mvpp2_prs_sram_ai_update(&pe, 0,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

670

mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

673

mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

675

mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

678

mvpp2_prs_tcam_port_map_set(&pe, port_mask);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

682

mvpp2_prs_tcam_port_set(&pe, port, add);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

684

mvpp2_prs_hw_write(priv, &pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

690

struct mvpp2_prs_entry pe;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

70

pe->tcam[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

703

__mvpp2_prs_init_from_hw(priv, &pe, tid);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

704

match = mvpp2_prs_tcam_data_cmp(&pe, 0, tpid);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

709

ri_bits = mvpp2_prs_sram_ri_get(&pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

713

ai_bits = mvpp2_prs_tcam_ai_get(&pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

73

mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

732

struct mvpp2_prs_entry pe;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

736

memset(&pe, 0, sizeof(pe));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

75

pe->sram[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

756

__mvpp2_prs_init_from_hw(priv, &pe, tid_aux);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

757

ri_bits = mvpp2_prs_sram_ri_get(&pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

766

memset(&pe, 0, sizeof(pe));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

767

pe.index = tid;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

768

mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

770

mvpp2_prs_match_etype(&pe, 0, tpid);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

773

mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VID);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

776

mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

779

mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_SINGLE,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

783

mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_TRIPLE,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

786

mvpp2_prs_tcam_ai_update(&pe, ai, MVPP2_PRS_SRAM_AI_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

788

mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

790

__mvpp2_prs_init_from_hw(priv, &pe, tid);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

793

mvpp2_prs_tcam_port_map_set(&pe, port_map);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

795

mvpp2_prs_hw_write(priv, &pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

80

int mvpp2_prs_init_from_hw(struct mvpp2 *priv, struct mvpp2_prs_entry *pe,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

817

struct mvpp2_prs_entry pe;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

830

__mvpp2_prs_init_from_hw(priv, &pe, tid);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

832

match = mvpp2_prs_tcam_data_cmp(&pe, 0, tpid1) &&

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

833

mvpp2_prs_tcam_data_cmp(&pe, 4, tpid2);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

838

ri_mask = mvpp2_prs_sram_ri_get(&pe) & MVPP2_PRS_RI_VLAN_MASK;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

852

struct mvpp2_prs_entry pe;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

854

memset(&pe, 0, sizeof(pe));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

86

err = __mvpp2_prs_init_from_hw(priv, pe, tid);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

879

__mvpp2_prs_init_from_hw(priv, &pe, tid_aux);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

880

ri_bits = mvpp2_prs_sram_ri_get(&pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

890

memset(&pe, 0, sizeof(pe));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

891

mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

892

pe.index = tid;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

896

mvpp2_prs_match_etype(&pe, 0, tpid1);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

897

mvpp2_prs_match_etype(&pe, 4, tpid2);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

899

mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

901

mvpp2_prs_sram_shift_set(&pe, MVPP2_VLAN_TAG_LEN,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

903

mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_DOUBLE,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

905

mvpp2_prs_sram_ai_update(&pe, ai | MVPP2_PRS_DBL_VLAN_AI_BIT,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

908

mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

910

__mvpp2_prs_init_from_hw(priv, &pe, tid);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

914

mvpp2_prs_tcam_port_map_set(&pe, port_map);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

915

mvpp2_prs_hw_write(priv, &pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

924

struct mvpp2_prs_entry pe;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

937

memset(&pe, 0, sizeof(pe));

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

938

mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

939

pe.index = tid;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

942

mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

943

mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

946

mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, -4,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

948

mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

949

mvpp2_prs_sram_ri_update(&pe, ri, ri_mask | MVPP2_PRS_RI_IP_FRAG_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

951

mvpp2_prs_tcam_data_byte_set(&pe, 2, 0x00,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

953

mvpp2_prs_tcam_data_byte_set(&pe, 3, 0x00,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

956

mvpp2_prs_tcam_data_byte_set(&pe, 5, proto, MVPP2_PRS_TCAM_PROTO_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

957

mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

960

mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

963

mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

964

mvpp2_prs_hw_write(priv, &pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

972

pe.index = tid;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

974

pe.sram[MVPP2_PRS_SRAM_RI_WORD] = 0x0;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

975

pe.sram[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

976

mvpp2_prs_sram_ri_update(&pe, ri, ri_mask);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

978

mvpp2_prs_sram_ri_update(&pe, ri | MVPP2_PRS_RI_IP_FRAG_TRUE,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

981

mvpp2_prs_tcam_data_byte_set(&pe, 2, 0x00, 0x0);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

982

mvpp2_prs_tcam_data_byte_set(&pe, 3, 0x00, 0x0);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

985

mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

986

mvpp2_prs_hw_write(priv, &pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c

994

struct mvpp2_prs_entry pe;

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h

299

int mvpp2_prs_init_from_hw(struct mvpp2 *priv, struct mvpp2_prs_entry *pe,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h

302

unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe);

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h

304

void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe,

drivers/net/wireless/ath/ath10k/wmi.c

4059

struct pulse_event pe;

drivers/net/wireless/ath/ath10k/wmi.c

4117

pe.ts = tsf64;

drivers/net/wireless/ath/ath10k/wmi.c

4118

pe.freq = ch->center_freq;

drivers/net/wireless/ath/ath10k/wmi.c

4119

pe.width = width;

drivers/net/wireless/ath/ath10k/wmi.c

4120

pe.rssi = rssi;

drivers/net/wireless/ath/ath10k/wmi.c

4121

pe.chirp = (MS(reg0, RADAR_REPORT_REG0_PULSE_IS_CHIRP) != 0);

drivers/net/wireless/ath/ath10k/wmi.c

4124

pe.freq, pe.width, pe.rssi, pe.ts);

drivers/net/wireless/ath/ath10k/wmi.c

4128

if (!ar->dfs_detector->add_pulse(ar->dfs_detector, &pe, &rs)) {

drivers/net/wireless/ath/ath9k/dfs.c

202

struct pulse_event *pe)

drivers/net/wireless/ath/ath9k/dfs.c

266

pe->width = dur_to_usecs(sc->sc_ah, dur);

drivers/net/wireless/ath/ath9k/dfs.c

267

pe->rssi = rssi;

drivers/net/wireless/ath/ath9k/dfs.c

274

ath9k_dfs_process_radar_pulse(struct ath_softc *sc, struct pulse_event *pe)

drivers/net/wireless/ath/ath9k/dfs.c

280

if (!pd->add_pulse(pd, pe, NULL))

drivers/net/wireless/ath/ath9k/dfs.c

295

struct pulse_event pe;

drivers/net/wireless/ath/ath9k/dfs.c

331

pe.freq = ah->curchan->channel;

drivers/net/wireless/ath/ath9k/dfs.c

332

pe.ts = mactime;

drivers/net/wireless/ath/ath9k/dfs.c

333

if (!ath9k_postprocess_radar_event(sc, &ard, &pe))

drivers/net/wireless/ath/ath9k/dfs.c

336

if (pe.width > MIN_CHIRP_PULSE_WIDTH &&

drivers/net/wireless/ath/ath9k/dfs.c

337

pe.width < MAX_CHIRP_PULSE_WIDTH) {

drivers/net/wireless/ath/ath9k/dfs.c

341

pe.chirp = ath9k_check_chirping(sc, data, clen, is_ctl, is_ext);

drivers/net/wireless/ath/ath9k/dfs.c

343

pe.chirp = false;

drivers/net/wireless/ath/ath9k/dfs.c

349

ard.pulse_bw_info, pe.freq, pe.ts, pe.width, pe.rssi,

drivers/net/wireless/ath/ath9k/dfs.c

350

pe.ts - sc->dfs_prev_pulse_ts);

drivers/net/wireless/ath/ath9k/dfs.c

351

sc->dfs_prev_pulse_ts = pe.ts;

drivers/net/wireless/ath/ath9k/dfs.c

353

ath9k_dfs_process_radar_pulse(sc, &pe);

drivers/net/wireless/ath/ath9k/dfs.c

356

pe.freq += IS_CHAN_HT40PLUS(ah->curchan) ? 20 : -20;

drivers/net/wireless/ath/ath9k/dfs.c

357

ath9k_dfs_process_radar_pulse(sc, &pe);

drivers/net/wireless/ath/dfs_pattern_detector.h

100

struct pulse_event *pe,

drivers/net/wireless/ath/dfs_pri_detector.c

118

static void pool_put_pulse_elem(struct pulse_elem *pe)

drivers/net/wireless/ath/dfs_pri_detector.c

121

list_add(&pe->head, &pulse_pool);

drivers/net/wireless/ath/dfs_pri_detector.c

149

struct pulse_elem *pe = NULL;

drivers/net/wireless/ath/dfs_pri_detector.c

152

pe = list_first_entry(&pulse_pool, struct pulse_elem, head);

drivers/net/wireless/ath/dfs_pri_detector.c

153

list_del(&pe->head);

drivers/net/wireless/ath/dfs_pri_detector.c

157

return pe;

drivers/net/wireless/mediatek/mt76/mt7915/mcu.c

1084

struct ieee80211_he_cap_elem *pe = &sta->deflink.he_cap.he_cap_elem;

drivers/net/wireless/mediatek/mt76/mt7915/mcu.c

1088

HE_PHY(CAP3_SU_BEAMFORMER, pe->phy_cap_info[3]);

drivers/net/wireless/mediatek/mt76/mt7915/mcu.c

1091

HE_PHY(CAP4_SU_BEAMFORMEE, pe->phy_cap_info[4]);

drivers/net/wireless/mediatek/mt76/mt7915/mcu.c

1184

struct ieee80211_he_cap_elem *pe = &pc->he_cap_elem;

drivers/net/wireless/mediatek/mt76/mt7915/mcu.c

1197

pe->phy_cap_info[6]);

drivers/net/wireless/mediatek/mt76/mt7915/mcu.c

1199

pe->phy_cap_info[6]);

drivers/net/wireless/mediatek/mt76/mt7915/mcu.c

1203

pe->phy_cap_info[4]);

drivers/net/wireless/mediatek/mt76/mt7915/mcu.c

1212

if (pe->phy_cap_info[0] &

drivers/net/wireless/mediatek/mt76/mt7915/mcu.c

1220

if (pe->phy_cap_info[0] &

drivers/net/wireless/mediatek/mt76/mt7915/mcu.c

1234

pe->phy_cap_info[4]);

drivers/net/wireless/mediatek/mt76/mt7915/mcu.c

1329

struct ieee80211_he_cap_elem *pe = &sta->deflink.he_cap.he_cap_elem;

drivers/net/wireless/mediatek/mt76/mt7915/mcu.c

1332

pe->phy_cap_info[5]);

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

1537

struct ieee80211_eht_cap_elem_fixed *pe = &pc->eht_cap_elem;

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

1541

EHT_PHY(CAP0_SU_BEAMFORMER, pe->phy_cap_info[0]);

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

1544

EHT_PHY(CAP0_SU_BEAMFORMEE, pe->phy_cap_info[0]);

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

1548

struct ieee80211_he_cap_elem *pe = &link_sta->he_cap.he_cap_elem;

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

1552

HE_PHY(CAP3_SU_BEAMFORMER, pe->phy_cap_info[3]);

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

1555

HE_PHY(CAP4_SU_BEAMFORMEE, pe->phy_cap_info[4]);

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

1656

struct ieee80211_he_cap_elem *pe = &pc->he_cap_elem;

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

1672

pe->phy_cap_info[6]);

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

1674

pe->phy_cap_info[6]);

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

1678

pe->phy_cap_info[4]);

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

1688

if (pe->phy_cap_info[0] &

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

1696

if (pe->phy_cap_info[0] &

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

1710

pe->phy_cap_info[4]);

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

1721

struct ieee80211_eht_cap_elem_fixed *pe = &pc->eht_cap_elem;

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

1734

bf->trigger_su = EHT_PHY(CAP3_TRIG_SU_BF_FDBK, pe->phy_cap_info[3]);

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

1735

bf->trigger_mu = EHT_PHY(CAP3_TRIG_MU_BF_PART_BW_FDBK, pe->phy_cap_info[3]);

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

1737

sts = EHT_PHY(CAP0_BEAMFORMEE_SS_80MHZ_MASK, pe->phy_cap_info[0]) +

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

1738

(EHT_PHY(CAP1_BEAMFORMEE_SS_80MHZ_MASK, pe->phy_cap_info[1]) << 1);

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

1750

sts = EHT_PHY(CAP1_BEAMFORMEE_SS_160MHZ_MASK, pe->phy_cap_info[1]);

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

1761

sts = EHT_PHY(CAP1_BEAMFORMEE_SS_320MHZ_MASK, pe->phy_cap_info[1]);

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

1868

struct ieee80211_he_cap_elem *pe = &link_sta->he_cap.he_cap_elem;

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

1871

pe->phy_cap_info[5]);

drivers/nvme/target/fc.c

1115

if (!tgtport->pe)

drivers/nvme/target/fc.c

113

struct nvmet_fc_port_entry *pe;

drivers/nvme/target/fc.c

1252

struct nvmet_fc_port_entry *pe,

drivers/nvme/target/fc.c

1258

pe->tgtport = tgtport;

drivers/nvme/target/fc.c

1259

tgtport->pe = pe;

drivers/nvme/target/fc.c

1261

pe->port = port;

drivers/nvme/target/fc.c

1262

port->priv = pe;

drivers/nvme/target/fc.c

1264

pe->node_name = tgtport->fc_target_port.node_name;

drivers/nvme/target/fc.c

1265

pe->port_name = tgtport->fc_target_port.port_name;

drivers/nvme/target/fc.c

1266

INIT_LIST_HEAD(&pe->pe_list);

drivers/nvme/target/fc.c

1268

list_add_tail(&pe->pe_list, &nvmet_fc_portentry_list);

drivers/nvme/target/fc.c

1272

nvmet_fc_portentry_unbind(struct nvmet_fc_port_entry *pe)

drivers/nvme/target/fc.c

1277

if (pe->tgtport) {

drivers/nvme/target/fc.c

1278

nvmet_fc_tgtport_put(pe->tgtport);

drivers/nvme/target/fc.c

1279

pe->tgtport->pe = NULL;

drivers/nvme/target/fc.c

1281

list_del(&pe->pe_list);

drivers/nvme/target/fc.c

1293

struct nvmet_fc_port_entry *pe;

drivers/nvme/target/fc.c

1297

pe = tgtport->pe;

drivers/nvme/target/fc.c

1298

if (pe) {

drivers/nvme/target/fc.c

1299

nvmet_fc_tgtport_put(pe->tgtport);

drivers/nvme/target/fc.c

1300

pe->tgtport = NULL;

drivers/nvme/target/fc.c

1302

tgtport->pe = NULL;

drivers/nvme/target/fc.c

1317

struct nvmet_fc_port_entry *pe;

drivers/nvme/target/fc.c

1321

list_for_each_entry(pe, &nvmet_fc_portentry_list, pe_list) {

drivers/nvme/target/fc.c

1322

if (tgtport->fc_target_port.node_name == pe->node_name &&

drivers/nvme/target/fc.c

1323

tgtport->fc_target_port.port_name == pe->port_name) {

drivers/nvme/target/fc.c

1327

WARN_ON(pe->tgtport);

drivers/nvme/target/fc.c

1328

tgtport->pe = pe;

drivers/nvme/target/fc.c

1329

pe->tgtport = tgtport;

drivers/nvme/target/fc.c

2556

if (!tgtport->pe)

drivers/nvme/target/fc.c

2558

fod->req.port = tgtport->pe->port;

drivers/nvme/target/fc.c

2867

struct nvmet_fc_port_entry *pe;

drivers/nvme/target/fc.c

2884

pe = kzalloc_obj(*pe);

drivers/nvme/target/fc.c

2885

if (!pe)

drivers/nvme/target/fc.c

2897

if (!tgtport->pe) {

drivers/nvme/target/fc.c

2898

nvmet_fc_portentry_bind(tgtport, pe, port);

drivers/nvme/target/fc.c

2910

kfree(pe);

drivers/nvme/target/fc.c

2918

struct nvmet_fc_port_entry *pe = port->priv;

drivers/nvme/target/fc.c

2923

if (pe->tgtport && nvmet_fc_tgtport_get(pe->tgtport))

drivers/nvme/target/fc.c

2924

tgtport = pe->tgtport;

drivers/nvme/target/fc.c

2927

nvmet_fc_portentry_unbind(pe);

drivers/nvme/target/fc.c

2935

kfree(pe);

drivers/nvme/target/fc.c

2941

struct nvmet_fc_port_entry *pe = port->priv;

drivers/nvme/target/fc.c

2946

if (pe->tgtport && nvmet_fc_tgtport_get(pe->tgtport))

drivers/nvme/target/fc.c

2947

tgtport = pe->tgtport;

drivers/parisc/eisa.c

440

char *pe;

drivers/parisc/eisa.c

442

val = (int) simple_strtoul(cur, &pe, 0);

drivers/pci/hotplug/pnv_php.c

1018

pe = edev ? edev->pe : NULL;

drivers/pci/hotplug/pnv_php.c

1019

if (pe) {

drivers/pci/hotplug/pnv_php.c

1021

eeh_pe_mark_isolated(pe);

drivers/pci/hotplug/pnv_php.c

1023

eeh_pe_set_option(pe, EEH_OPT_FREEZE_PE);

drivers/pci/hotplug/pnv_php.c

916

struct eeh_pe *pe;

drivers/pci/hotplug/pnv_php.c

928

pe = edev ? edev->pe : NULL;

drivers/pci/hotplug/pnv_php.c

929

rc = eeh_pe_get_state(pe);

drivers/pci/hotplug/pnv_php.c

935

if (pe->state & EEH_PE_ISOLATED) {

drivers/pci/hotplug/pnv_php.c

939

pe->addr);

drivers/pci/hotplug/pnv_php.c

941

if (!eeh_unfreeze_pe(pe))

drivers/pci/hotplug/pnv_php.c

947

pe->addr);

drivers/pci/hotplug/pnv_php.c

951

pe->addr);

drivers/pci/hotplug/pnv_php.c

977

struct eeh_pe *pe;

drivers/pci/hotplug/rpaphp_pci.c

77

struct eeh_pe *pe;

drivers/pci/hotplug/rpaphp_pci.c

92

pe = eeh_dev_to_pe(pdn->edev);

drivers/pci/hotplug/rpaphp_pci.c

93

if (pe && (pe->state & EEH_PE_RECOVERING)) {

drivers/pinctrl/tegra/pinctrl-tegra124.c

1655

FUNCTION(pe),

drivers/pinctrl/tegra/pinctrl-tegra186.c

1331

TEGRA_PIN_FUNCTION(pe),

drivers/pinctrl/tegra/pinctrl-tegra210.c

1223

FUNCTION(pe),

drivers/scsi/aic94xx/aic94xx_sds.c

928

struct asd_ctrla_phy_entry *pe = &ps->phy_ent[i];

drivers/scsi/aic94xx/aic94xx_sds.c

932

if (*(u64 *)pe->sas_addr == 0) {

drivers/scsi/aic94xx/aic94xx_sds.c

937

memcpy(asd_ha->hw_prof.phy_desc[i].sas_addr, pe->sas_addr,

drivers/scsi/aic94xx/aic94xx_sds.c

940

(pe->sas_link_rates & 0xF0) >> 4;

drivers/scsi/aic94xx/aic94xx_sds.c

942

(pe->sas_link_rates & 0x0F);

drivers/scsi/aic94xx/aic94xx_sds.c

944

(pe->sata_link_rates & 0xF0) >> 4;

drivers/scsi/aic94xx/aic94xx_sds.c

946

(pe->sata_link_rates & 0x0F);

drivers/scsi/aic94xx/aic94xx_sds.c

947

asd_ha->hw_prof.phy_desc[i].flags = pe->flags;

drivers/scsi/isci/host.c

2217

&ihost->scu_registers->peg0.pe[i].tl,

drivers/scsi/isci/host.c

2218

&ihost->scu_registers->peg0.pe[i].ll);

drivers/scsi/isci/registers.h

1819

struct transport_link_layer_pair pe[4];

drivers/scsi/isci/registers.h

440

#define SMU_RESET_PROTOCOL_ENGINE(peg, pe) \

drivers/scsi/isci/registers.h

441

((1 << (pe)) << ((peg) * 8))

drivers/scsi/lpfc/lpfc_ct.c

3209

struct lpfc_fdmi_port_entry *pe;

drivers/scsi/lpfc/lpfc_ct.c

3280

memcpy(&rh->rpl.pe.PortName,

drivers/scsi/lpfc/lpfc_ct.c

3384

pe = (struct lpfc_fdmi_port_entry *)&CtReq->un;

drivers/scsi/lpfc/lpfc_ct.c

3385

memcpy((uint8_t *)&pe->PortName,

drivers/scsi/lpfc/lpfc_ct.c

3403

pe = (struct lpfc_fdmi_port_entry *)&CtReq->un;

drivers/scsi/lpfc/lpfc_ct.c

3404

memcpy((uint8_t *)&pe->PortName,

drivers/scsi/lpfc/lpfc_hw.h

1564

struct lpfc_fdmi_port_entry pe;

drivers/scsi/ncr53c8xx.c

665

char *pe;

drivers/scsi/ncr53c8xx.c

676

val = (int) simple_strtoul(pv, &pe, 0);

drivers/scsi/ncr53c8xx.c

681

if (pe && *pe == '/') {

drivers/scsi/ncr53c8xx.c

683

while (*pe && *pe != ARG_SEP &&

drivers/scsi/ncr53c8xx.c

685

driver_setup.tag_ctrl[i++] = *pe++;

drivers/thunderbolt/property.c

417

struct tb_property_dir_entry *pe;

drivers/thunderbolt/property.c

419

pe = (struct tb_property_dir_entry *)&block[start_offset];

drivers/thunderbolt/property.c

420

memcpy(pe->uuid, dir->uuid, sizeof(pe->uuid));

drivers/thunderbolt/property.c

421

entry = pe->entries;

drivers/tty/vt/selection.c

252

int pe)

drivers/tty/vt/selection.c

260

new_sel_end = pe;

drivers/tty/vt/selection.c

273

spc = is_space_on_vt(sel_pos(pe, unicode));

drivers/tty/vt/selection.c

274

for (new_sel_end = pe; ; pe += 2) {

drivers/tty/vt/selection.c

275

if ((spc && !is_space_on_vt(sel_pos(pe, unicode))) ||

drivers/tty/vt/selection.c

276

(!spc && !inword(sel_pos(pe, unicode))))

drivers/tty/vt/selection.c

278

new_sel_end = pe;

drivers/tty/vt/selection.c

279

if (!((pe + 2) % vc->vc_size_row))

drivers/tty/vt/selection.c

285

new_sel_end = rounddown(pe, vc->vc_size_row) +

drivers/tty/vt/selection.c

289

highlight_pointer(pe);

drivers/tty/vt/selection.c

302

for (pe = new_sel_end + 2; ; pe += 2)

drivers/tty/vt/selection.c

303

if (!is_space_on_vt(sel_pos(pe, unicode)) ||

drivers/tty/vt/selection.c

304

atedge(pe, vc->vc_size_row))

drivers/tty/vt/selection.c

306

if (is_space_on_vt(sel_pos(pe, unicode)))

drivers/tty/vt/selection.c

307

new_sel_end = pe;

drivers/tty/vt/selection.c

341

int ps, pe;

drivers/tty/vt/selection.c

364

pe = v->ye * vc->vc_size_row + (v->xe << 1);

drivers/tty/vt/selection.c

365

if (ps > pe) /* make vc_sel.start <= vc_sel.end */

drivers/tty/vt/selection.c

366

swap(ps, pe);

drivers/tty/vt/selection.c

373

return vc_do_selection(vc, v->sel_mode, ps, pe);

drivers/vdpa/mlx5/core/mr.c

508

u64 pe = U64_MAX;

drivers/vdpa/mlx5/core/mr.c

517

if (pe == map->start && pperm == map->perm) {

drivers/vdpa/mlx5/core/mr.c

518

pe = map->last + 1;

drivers/vdpa/mlx5/core/mr.c

521

if (pe < map->start) {

drivers/vdpa/mlx5/core/mr.c

525

nnuls = MLX5_DIV_ROUND_UP_POW2(map->start - pe,

drivers/vdpa/mlx5/core/mr.c

529

err = add_direct_chain(mvdev, mr, ps, pe - ps, pperm, iotlb);

drivers/vdpa/mlx5/core/mr.c

534

pe = map->last + 1;

drivers/vdpa/mlx5/core/mr.c

538

err = add_direct_chain(mvdev, mr, ps, pe - ps, pperm, iotlb);

drivers/vfio/vfio_iommu_spapr_tce.c

780

struct eeh_pe *pe;

drivers/vfio/vfio_iommu_spapr_tce.c

784

pe = eeh_iommu_group_to_pe(group);

drivers/vfio/vfio_iommu_spapr_tce.c

785

if (!pe)

drivers/vfio/vfio_iommu_spapr_tce.c

796

return eeh_pe_set_option(pe, EEH_OPT_DISABLE);

drivers/vfio/vfio_iommu_spapr_tce.c

798

return eeh_pe_set_option(pe, EEH_OPT_ENABLE);

drivers/vfio/vfio_iommu_spapr_tce.c

800

return eeh_pe_set_option(pe, EEH_OPT_THAW_MMIO);

drivers/vfio/vfio_iommu_spapr_tce.c

802

return eeh_pe_set_option(pe, EEH_OPT_THAW_DMA);

drivers/vfio/vfio_iommu_spapr_tce.c

804

return eeh_pe_get_state(pe);

drivers/vfio/vfio_iommu_spapr_tce.c

807

return eeh_pe_reset(pe, EEH_RESET_DEACTIVATE, true);

drivers/vfio/vfio_iommu_spapr_tce.c

809

return eeh_pe_reset(pe, EEH_RESET_HOT, true);

drivers/vfio/vfio_iommu_spapr_tce.c

811

return eeh_pe_reset(pe, EEH_RESET_FUNDAMENTAL, true);

drivers/vfio/vfio_iommu_spapr_tce.c

813

return eeh_pe_configure(pe);

drivers/vfio/vfio_iommu_spapr_tce.c

821

return eeh_pe_inject_err(pe, op.err.type, op.err.func,

fs/afs/server_list.c

159

struct afs_server_entry *se, *pe;

fs/afs/server_list.c

171

pe = list_entry(p, struct afs_server_entry, slink);

fs/afs/server_list.c

172

if (volume->vid <= pe->volume->vid)

fs/f2fs/acl.c

309

struct posix_acl_entry *pa, *pe;

fs/f2fs/acl.c

316

FOREACH_ACL_ENTRY(pa, acl, pe) {

fs/nfs_common/nfsacl.c

295

struct posix_acl_entry *pa, *pe,

fs/nfs_common/nfsacl.c

305

FOREACH_ACL_ENTRY(pa, acl, pe) {

fs/nfsd/nfs4acl.c

191

struct posix_acl_entry *pa, *pe;

fs/nfsd/nfs4acl.c

201

FOREACH_ACL_ENTRY(pa, acl, pe) {

fs/posix_acl.c

238

const struct posix_acl_entry *pa, *pe;

fs/posix_acl.c

242

FOREACH_ACL_ENTRY(pa, acl, pe) {

fs/posix_acl.c

307

const struct posix_acl_entry *pa, *pe;

fs/posix_acl.c

317

FOREACH_ACL_ENTRY(pa, acl, pe) {

fs/posix_acl.c

377

const struct posix_acl_entry *pa, *pe, *mask_obj;

fs/posix_acl.c

385

FOREACH_ACL_ENTRY(pa, acl, pe) {

fs/posix_acl.c

430

for (mask_obj = pa+1; mask_obj != pe; mask_obj++) {

fs/posix_acl.c

454

struct posix_acl_entry *pa, *pe;

fs/posix_acl.c

461

FOREACH_ACL_ENTRY(pa, acl, pe) {

fs/posix_acl.c

512

struct posix_acl_entry *pa, *pe;

fs/posix_acl.c

516

FOREACH_ACL_ENTRY(pa, acl, pe) {

fs/smb/client/cifssmb.c

3315

struct posix_acl_entry *pa, *pe;

fs/smb/client/cifssmb.c

3352

FOREACH_ACL_ENTRY(pa, kacl, pe) {

fs/smb/client/cifssmb.c

3399

const struct posix_acl_entry *pa, *pe;

fs/smb/client/cifssmb.c

3427

FOREACH_ACL_ENTRY(pa, acl, pe) {

include/linux/posix_acl.h

41

#define FOREACH_ACL_ENTRY(pa, acl, pe) \

include/linux/posix_acl.h

42

for(pa=(acl)->a_entries, pe=pa+(acl)->a_count; pa<pe; pa++)

include/net/ip_vs.h

1332

p->pe = NULL;

include/net/ip_vs.h

1485

int register_ip_vs_pe(struct ip_vs_pe *pe);

include/net/ip_vs.h

1486

int unregister_ip_vs_pe(struct ip_vs_pe *pe);

include/net/ip_vs.h

1491

#define ip_vs_pe_get(pe) \

include/net/ip_vs.h

1492

if (pe && pe->module) \

include/net/ip_vs.h

1493

__module_get(pe->module);

include/net/ip_vs.h

1495

#define ip_vs_pe_put(pe) \

include/net/ip_vs.h

1496

if (pe && pe->module) \

include/net/ip_vs.h

1497

module_put(pe->module);

include/net/ip_vs.h

557

const struct ip_vs_pe *pe;

include/net/ip_vs.h

618

const struct ip_vs_pe *pe;

include/net/ip_vs.h

700

struct ip_vs_pe __rcu *pe;

kernel/cgroup/pids.c

364

enum pidcg_event pe = PIDCG_MAX;

kernel/cgroup/pids.c

369

pe = PIDCG_FORKFAIL;

kernel/cgroup/pids.c

374

seq_printf(sf, "max %lld\n", (s64)atomic64_read(&events[pe]));

kernel/time/timer_list.c

353

struct proc_dir_entry *pe;

kernel/time/timer_list.c

355

pe = proc_create_seq_private("timer_list", 0400, NULL, &timer_list_sops,

kernel/time/timer_list.c

357

if (!pe)

kernel/trace/trace_events_filter.c

1205

struct filter_parse_error *pe,

kernel/trace/trace_events_filter.c

1209

int pos = pe->lasterr_pos;

kernel/trace/trace_events_filter.c

1230

if (pe->lasterr > 0) {

kernel/trace/trace_events_filter.c

1232

trace_seq_printf(s, "\nparse_error: %s\n", err_text[pe->lasterr]);

kernel/trace/trace_events_filter.c

1235

pe->lasterr, pe->lasterr_pos);

kernel/trace/trace_events_filter.c

1237

trace_seq_printf(s, "\nError: (%d)\n", pe->lasterr);

kernel/trace/trace_events_filter.c

1629

int pos, struct filter_parse_error *pe,

kernel/trace/trace_events_filter.c

1673

parse_error(pe, FILT_ERR_FIELD_NOT_FOUND, pos + i);

kernel/trace/trace_events_filter.c

1700

parse_error(pe, FILT_ERR_INVALID_OP, pos + i);

kernel/trace/trace_events_filter.c

1722

parse_error(pe, FILT_ERR_ILLEGAL_FIELD_OP, pos + i);

kernel/trace/trace_events_filter.c

1732

parse_error(pe, FILT_ERR_INVALID_OP, pos + i);

kernel/trace/trace_events_filter.c

1744

parse_error(pe, FILT_ERR_OPERAND_TOO_LONG, pos + i);

kernel/trace/trace_events_filter.c

1753

parse_error(pe, FILT_ERR_INVALID_VALUE, pos + i);

kernel/trace/trace_events_filter.c

1768

parse_error(pe, FILT_ERR_NO_FUNCTION, pos + i);

kernel/trace/trace_events_filter.c

1775

parse_error(pe, FILT_ERR_NO_FUNCTION, pos + i);

kernel/trace/trace_events_filter.c

1792

parse_error(pe, FILT_ERR_IP_FIELD_ONLY, pos + i);

kernel/trace/trace_events_filter.c

1818

parse_error(pe, FILT_ERR_OPERAND_TOO_LONG, pos + i);

kernel/trace/trace_events_filter.c

184

static void parse_error(struct filter_parse_error *pe, int err, int pos)

kernel/trace/trace_events_filter.c

1840

parse_error(pe, FILT_ERR_ILLEGAL_FIELD_OP, pos + i);

kernel/trace/trace_events_filter.c

1850

parse_error(pe, FILT_ERR_ILLEGAL_FIELD_OP, pos + i);

kernel/trace/trace_events_filter.c

1857

parse_error(pe, FILT_ERR_MISSING_BRACE_OPEN, pos + i);

kernel/trace/trace_events_filter.c

186

pe->lasterr = err;

kernel/trace/trace_events_filter.c

1867

parse_error(pe, FILT_ERR_MISSING_BRACE_CLOSE, pos + i);

kernel/trace/trace_events_filter.c

187

pe->lasterr_pos = pos;

kernel/trace/trace_events_filter.c

1872

parse_error(pe, FILT_ERR_INVALID_CPULIST, pos + i);

kernel/trace/trace_events_filter.c

1891

parse_error(pe, FILT_ERR_INVALID_CPULIST, pos + i);

kernel/trace/trace_events_filter.c

191

struct filter_parse_error *pe,

kernel/trace/trace_events_filter.c

1960

parse_error(pe, FILT_ERR_ILLEGAL_FIELD_OP, pos + i);

kernel/trace/trace_events_filter.c

1966

parse_error(pe, FILT_ERR_EXPECT_DIGIT, pos + i);

kernel/trace/trace_events_filter.c

1975

parse_error(pe, FILT_ERR_MISSING_QUOTE, pos + i);

kernel/trace/trace_events_filter.c

1983

parse_error(pe, FILT_ERR_OPERAND_TOO_LONG, pos + i);

kernel/trace/trace_events_filter.c

2028

parse_error(pe, FILT_ERR_EXPECT_STRING, pos + i);

kernel/trace/trace_events_filter.c

2033

parse_error(pe, FILT_ERR_ILLEGAL_FIELD_OP, pos + i);

kernel/trace/trace_events_filter.c

2047

parse_error(pe, FILT_ERR_OPERAND_TOO_LONG, pos + i);

kernel/trace/trace_events_filter.c

2060

parse_error(pe, FILT_ERR_ILLEGAL_INTVAL, pos + s);

kernel/trace/trace_events_filter.c

2076

parse_error(pe, FILT_ERR_INVALID_VALUE, pos + i);

kernel/trace/trace_events_filter.c

2207

struct filter_parse_error *pe)

kernel/trace/trace_events_filter.c

2219

parse_error(pe, FILT_ERR_MISSING_QUOTE, index);

kernel/trace/trace_events_filter.c

2222

parse_error(pe, FILT_ERR_TOO_MANY_OPEN, index);

kernel/trace/trace_events_filter.c

2225

parse_error(pe, FILT_ERR_TOO_MANY_CLOSE, index);

kernel/trace/trace_events_filter.c

2234

parse_pred, call, pe);

kernel/trace/trace_events_filter.c

2254

struct filter_parse_error *pe,

kernel/trace/trace_events_filter.c

2283

err = process_preds(file->event_call, filter_string, filter, pe);

kernel/trace/trace_events_filter.c

2286

parse_error(pe, FILT_ERR_BAD_SUBSYS_FILTER, 0);

kernel/trace/trace_events_filter.c

2287

append_filter_err(tr, pe, filter);

kernel/trace/trace_events_filter.c

2321

parse_error(pe, FILT_ERR_BAD_SUBSYS_FILTER, 0);

kernel/trace/trace_events_filter.c

2340

struct filter_parse_error *pe = NULL;

kernel/trace/trace_events_filter.c

2353

pe = kzalloc_obj(*pe);

kernel/trace/trace_events_filter.c

2355

if (!filter || !pe || err) {

kernel/trace/trace_events_filter.c

2356

kfree(pe);

kernel/trace/trace_events_filter.c

2363

*pse = pe;

kernel/trace/trace_events_filter.c

2368

static void create_filter_finish(struct filter_parse_error *pe)

kernel/trace/trace_events_filter.c

2370

kfree(pe);

kernel/trace/trace_events_filter.c

2396

struct filter_parse_error *pe = NULL;

kernel/trace/trace_events_filter.c

2403

err = create_filter_start(filter_string, set_str, &pe, filterp);

kernel/trace/trace_events_filter.c

2407

err = process_preds(call, filter_string, *filterp, pe);

kernel/trace/trace_events_filter.c

2409

append_filter_err(tr, pe, *filterp);

kernel/trace/trace_events_filter.c

2410

create_filter_finish(pe);

kernel/trace/trace_events_filter.c

2435

struct filter_parse_error *pe = NULL;

kernel/trace/trace_events_filter.c

2438

err = create_filter_start(filter_str, true, &pe, filterp);

kernel/trace/trace_events_filter.c

2440

err = process_system_preds(dir, dir->tr, pe, filter_str);

kernel/trace/trace_events_filter.c

2446

append_filter_err(dir->tr, pe, *filterp);

kernel/trace/trace_events_filter.c

2449

create_filter_finish(pe);

kernel/trace/trace_events_filter.c

472

struct filter_parse_error *pe)

kernel/trace/trace_events_filter.c

493

parse_error(pe, -ENOMEM, 0);

kernel/trace/trace_events_filter.c

498

parse_error(pe, -ENOMEM, 0);

kernel/trace/trace_events_filter.c

529

parse_error(pe, FILT_ERR_TOO_MANY_PREDS, next - str);

kernel/trace/trace_events_filter.c

536

len = parse_pred(next, data, ptr - str, pe, &prog[N].pred);

kernel/trace/trace_events_filter.c

564

parse_error(pe, FILT_ERR_TOO_MANY_PREDS,

kernel/trace/trace_events_filter.c

593

parse_error(pe, FILT_ERR_TOO_MANY_CLOSE, ptr - str);

kernel/trace/trace_events_filter.c

602

parse_error(pe, FILT_ERR_TOO_MANY_OPEN, ptr - str);

kernel/trace/trace_events_filter.c

609

parse_error(pe, FILT_ERR_NO_FILTER, ptr - str);

lib/crypto/des.c

622

static unsigned long des_ekey(u32 *pe, const u8 *k)

lib/crypto/des.c

633

pe[15 * 2 + 0] = DES_PC2(a, b, c, d); d = rs[d];

lib/crypto/des.c

634

pe[14 * 2 + 0] = DES_PC2(d, a, b, c); c = rs[c]; b = rs[b];

lib/crypto/des.c

635

pe[13 * 2 + 0] = DES_PC2(b, c, d, a); a = rs[a]; d = rs[d];

lib/crypto/des.c

636

pe[12 * 2 + 0] = DES_PC2(d, a, b, c); c = rs[c]; b = rs[b];

lib/crypto/des.c

637

pe[11 * 2 + 0] = DES_PC2(b, c, d, a); a = rs[a]; d = rs[d];

lib/crypto/des.c

638

pe[10 * 2 + 0] = DES_PC2(d, a, b, c); c = rs[c]; b = rs[b];

lib/crypto/des.c

639

pe[ 9 * 2 + 0] = DES_PC2(b, c, d, a); a = rs[a]; d = rs[d];

lib/crypto/des.c

640

pe[ 8 * 2 + 0] = DES_PC2(d, a, b, c); c = rs[c];

lib/crypto/des.c

641

pe[ 7 * 2 + 0] = DES_PC2(c, d, a, b); b = rs[b]; a = rs[a];

lib/crypto/des.c

642

pe[ 6 * 2 + 0] = DES_PC2(a, b, c, d); d = rs[d]; c = rs[c];

lib/crypto/des.c

643

pe[ 5 * 2 + 0] = DES_PC2(c, d, a, b); b = rs[b]; a = rs[a];

lib/crypto/des.c

644

pe[ 4 * 2 + 0] = DES_PC2(a, b, c, d); d = rs[d]; c = rs[c];

lib/crypto/des.c

645

pe[ 3 * 2 + 0] = DES_PC2(c, d, a, b); b = rs[b]; a = rs[a];

lib/crypto/des.c

646

pe[ 2 * 2 + 0] = DES_PC2(a, b, c, d); d = rs[d]; c = rs[c];

lib/crypto/des.c

647

pe[ 1 * 2 + 0] = DES_PC2(c, d, a, b); b = rs[b];

lib/crypto/des.c

648

pe[ 0 * 2 + 0] = DES_PC2(b, c, d, a);

lib/crypto/des.c

664

pe[15 * 2 + 1] = DES_PC2(a, b, c, d); d = rs[d];

lib/crypto/des.c

665

pe[14 * 2 + 1] = DES_PC2(d, a, b, c); c = rs[c]; b = rs[b];

lib/crypto/des.c

666

pe[13 * 2 + 1] = DES_PC2(b, c, d, a); a = rs[a]; d = rs[d];

lib/crypto/des.c

667

pe[12 * 2 + 1] = DES_PC2(d, a, b, c); c = rs[c]; b = rs[b];

lib/crypto/des.c

668

pe[11 * 2 + 1] = DES_PC2(b, c, d, a); a = rs[a]; d = rs[d];

lib/crypto/des.c

669

pe[10 * 2 + 1] = DES_PC2(d, a, b, c); c = rs[c]; b = rs[b];

lib/crypto/des.c

670

pe[ 9 * 2 + 1] = DES_PC2(b, c, d, a); a = rs[a]; d = rs[d];

lib/crypto/des.c

671

pe[ 8 * 2 + 1] = DES_PC2(d, a, b, c); c = rs[c];

lib/crypto/des.c

672

pe[ 7 * 2 + 1] = DES_PC2(c, d, a, b); b = rs[b]; a = rs[a];

lib/crypto/des.c

673

pe[ 6 * 2 + 1] = DES_PC2(a, b, c, d); d = rs[d]; c = rs[c];

lib/crypto/des.c

674

pe[ 5 * 2 + 1] = DES_PC2(c, d, a, b); b = rs[b]; a = rs[a];

lib/crypto/des.c

675

pe[ 4 * 2 + 1] = DES_PC2(a, b, c, d); d = rs[d]; c = rs[c];

lib/crypto/des.c

676

pe[ 3 * 2 + 1] = DES_PC2(c, d, a, b); b = rs[b]; a = rs[a];

lib/crypto/des.c

677

pe[ 2 * 2 + 1] = DES_PC2(a, b, c, d); d = rs[d]; c = rs[c];

lib/crypto/des.c

678

pe[ 1 * 2 + 1] = DES_PC2(c, d, a, b); b = rs[b];

lib/crypto/des.c

679

pe[ 0 * 2 + 1] = DES_PC2(b, c, d, a);

lib/crypto/des.c

683

a = pe[2 * d];

lib/crypto/des.c

684

b = pe[2 * d + 1];

lib/crypto/des.c

690

pe[2 * d] = a;

lib/crypto/des.c

691

pe[2 * d + 1] = b;

lib/crypto/des.c

713

static void dkey(u32 *pe, const u8 *k)

lib/crypto/des.c

724

pe[ 0 * 2] = DES_PC2(a, b, c, d); d = rs[d];

lib/crypto/des.c

725

pe[ 1 * 2] = DES_PC2(d, a, b, c); c = rs[c]; b = rs[b];

lib/crypto/des.c

726

pe[ 2 * 2] = DES_PC2(b, c, d, a); a = rs[a]; d = rs[d];

lib/crypto/des.c

727

pe[ 3 * 2] = DES_PC2(d, a, b, c); c = rs[c]; b = rs[b];

lib/crypto/des.c

728

pe[ 4 * 2] = DES_PC2(b, c, d, a); a = rs[a]; d = rs[d];

lib/crypto/des.c

729

pe[ 5 * 2] = DES_PC2(d, a, b, c); c = rs[c]; b = rs[b];

lib/crypto/des.c

730

pe[ 6 * 2] = DES_PC2(b, c, d, a); a = rs[a]; d = rs[d];

lib/crypto/des.c

731

pe[ 7 * 2] = DES_PC2(d, a, b, c); c = rs[c];

lib/crypto/des.c

732

pe[ 8 * 2] = DES_PC2(c, d, a, b); b = rs[b]; a = rs[a];

lib/crypto/des.c

733

pe[ 9 * 2] = DES_PC2(a, b, c, d); d = rs[d]; c = rs[c];

lib/crypto/des.c

734

pe[10 * 2] = DES_PC2(c, d, a, b); b = rs[b]; a = rs[a];

lib/crypto/des.c

735

pe[11 * 2] = DES_PC2(a, b, c, d); d = rs[d]; c = rs[c];

lib/crypto/des.c

736

pe[12 * 2] = DES_PC2(c, d, a, b); b = rs[b]; a = rs[a];

lib/crypto/des.c

737

pe[13 * 2] = DES_PC2(a, b, c, d); d = rs[d]; c = rs[c];

lib/crypto/des.c

738

pe[14 * 2] = DES_PC2(c, d, a, b); b = rs[b];

lib/crypto/des.c

739

pe[15 * 2] = DES_PC2(b, c, d, a);

lib/crypto/des.c

749

pe[ 0 * 2 + 1] = DES_PC2(a, b, c, d); d = rs[d];

lib/crypto/des.c

750

pe[ 1 * 2 + 1] = DES_PC2(d, a, b, c); c = rs[c]; b = rs[b];

lib/crypto/des.c

751

pe[ 2 * 2 + 1] = DES_PC2(b, c, d, a); a = rs[a]; d = rs[d];

lib/crypto/des.c

752

pe[ 3 * 2 + 1] = DES_PC2(d, a, b, c); c = rs[c]; b = rs[b];

lib/crypto/des.c

753

pe[ 4 * 2 + 1] = DES_PC2(b, c, d, a); a = rs[a]; d = rs[d];

lib/crypto/des.c

754

pe[ 5 * 2 + 1] = DES_PC2(d, a, b, c); c = rs[c]; b = rs[b];

lib/crypto/des.c

755

pe[ 6 * 2 + 1] = DES_PC2(b, c, d, a); a = rs[a]; d = rs[d];

lib/crypto/des.c

756

pe[ 7 * 2 + 1] = DES_PC2(d, a, b, c); c = rs[c];

lib/crypto/des.c

757

pe[ 8 * 2 + 1] = DES_PC2(c, d, a, b); b = rs[b]; a = rs[a];

lib/crypto/des.c

758

pe[ 9 * 2 + 1] = DES_PC2(a, b, c, d); d = rs[d]; c = rs[c];

lib/crypto/des.c

759

pe[10 * 2 + 1] = DES_PC2(c, d, a, b); b = rs[b]; a = rs[a];

lib/crypto/des.c

760

pe[11 * 2 + 1] = DES_PC2(a, b, c, d); d = rs[d]; c = rs[c];

lib/crypto/des.c

761

pe[12 * 2 + 1] = DES_PC2(c, d, a, b); b = rs[b]; a = rs[a];

lib/crypto/des.c

762

pe[13 * 2 + 1] = DES_PC2(a, b, c, d); d = rs[d]; c = rs[c];

lib/crypto/des.c

763

pe[14 * 2 + 1] = DES_PC2(c, d, a, b); b = rs[b];

lib/crypto/des.c

764

pe[15 * 2 + 1] = DES_PC2(b, c, d, a);

lib/crypto/des.c

768

a = pe[2 * d];

lib/crypto/des.c

769

b = pe[2 * d + 1];

lib/crypto/des.c

775

pe[2 * d] = a;

lib/crypto/des.c

776

pe[2 * d + 1] = b;

lib/crypto/des.c

825

u32 *pe = ctx->expkey;

lib/crypto/des.c

835

des_ekey(pe, key); pe += DES_EXPKEY_WORDS; key += DES_KEY_SIZE;

lib/crypto/des.c

836

dkey(pe, key); pe += DES_EXPKEY_WORDS; key += DES_KEY_SIZE;

lib/crypto/des.c

837

des_ekey(pe, key);

net/core/pktgen.c

3918

struct proc_dir_entry *pe;

net/core/pktgen.c

3946

pe = proc_create_data(t->tsk->comm, 0600, pn->proc_dir,

net/core/pktgen.c

3948

if (!pe) {

net/core/pktgen.c

4022

struct proc_dir_entry *pe;

net/core/pktgen.c

4033

pe = proc_create(PGCTRL, 0600, pn->proc_dir, &pktgen_proc_ops);

net/core/pktgen.c

4034

if (pe == NULL) {

net/netfilter/ipvs/ip_vs_conn.c

1141

len = strlen(cp->pe->name);

net/netfilter/ipvs/ip_vs_conn.c

1142

memcpy(pe_data + 1, cp->pe->name, len);

net/netfilter/ipvs/ip_vs_conn.c

1145

len += cp->pe->show_pe_data(cp, pe_data + len);

net/netfilter/ipvs/ip_vs_conn.c

127

if (p->pe_data && p->pe->hashkey_raw)

net/netfilter/ipvs/ip_vs_conn.c

128

return p->pe->hashkey_raw(p, ip_vs_conn_rnd, inverse) &

net/netfilter/ipvs/ip_vs_conn.c

149

if (cp->pe) {

net/netfilter/ipvs/ip_vs_conn.c

150

p.pe = cp->pe;

net/netfilter/ipvs/ip_vs_conn.c

358

if (unlikely(p->pe_data && p->pe->ct_match)) {

net/netfilter/ipvs/ip_vs_conn.c

361

if (p->pe == cp->pe && p->pe->ct_match(p, cp)) {

net/netfilter/ipvs/ip_vs_conn.c

816

ip_vs_pe_put(cp->pe);

net/netfilter/ipvs/ip_vs_conn.c

971

if (flags & IP_VS_CONN_F_TEMPLATE && p->pe) {

net/netfilter/ipvs/ip_vs_conn.c

972

ip_vs_pe_get(p->pe);

net/netfilter/ipvs/ip_vs_conn.c

973

cp->pe = p->pe;

net/netfilter/ipvs/ip_vs_conn.c

977

cp->pe = NULL;

net/netfilter/ipvs/ip_vs_core.c

1240

struct ip_vs_pe *pe;

net/netfilter/ipvs/ip_vs_core.c

1244

pe = rcu_dereference(svc->pe);

net/netfilter/ipvs/ip_vs_core.c

1245

if (pe && pe->conn_out)

net/netfilter/ipvs/ip_vs_core.c

1246

cp = pe->conn_out(svc, dest, skb, iph,

net/netfilter/ipvs/ip_vs_core.c

237

p->pe = rcu_dereference(svc->pe);

net/netfilter/ipvs/ip_vs_core.c

238

if (p->pe && p->pe->fill_param)

net/netfilter/ipvs/ip_vs_core.c

239

return p->pe->fill_param(p, skb);

net/netfilter/ipvs/ip_vs_ctl.c

1372

struct ip_vs_pe *pe = NULL;

net/netfilter/ipvs/ip_vs_ctl.c

1392

pe = ip_vs_pe_getbyname(u->pe_name);

net/netfilter/ipvs/ip_vs_ctl.c

1393

if (pe == NULL) {

net/netfilter/ipvs/ip_vs_ctl.c

1467

if (pe && pe->conn_out)

net/netfilter/ipvs/ip_vs_ctl.c

1471

RCU_INIT_POINTER(svc->pe, pe);

net/netfilter/ipvs/ip_vs_ctl.c

1472

pe = NULL;

net/netfilter/ipvs/ip_vs_ctl.c

1504

ip_vs_pe_put(pe);

net/netfilter/ipvs/ip_vs_ctl.c

1520

struct ip_vs_pe *pe = NULL, *old_pe = NULL;

net/netfilter/ipvs/ip_vs_ctl.c

1538

pe = ip_vs_pe_getbyname(u->pe_name);

net/netfilter/ipvs/ip_vs_ctl.c

1539

if (pe == NULL) {

net/netfilter/ipvs/ip_vs_ctl.c

1545

old_pe = pe;

net/netfilter/ipvs/ip_vs_ctl.c

1584

old_pe = rcu_dereference_protected(svc->pe, 1);

net/netfilter/ipvs/ip_vs_ctl.c

1585

if (pe != old_pe) {

net/netfilter/ipvs/ip_vs_ctl.c

1586

rcu_assign_pointer(svc->pe, pe);

net/netfilter/ipvs/ip_vs_ctl.c

1588

new_pe_conn_out = (pe && pe->conn_out) ? true : false;

net/netfilter/ipvs/ip_vs_ctl.c

1632

old_pe = rcu_dereference_protected(svc->pe, 1);

net/netfilter/ipvs/ip_vs_ctl.c

3319

struct ip_vs_pe *pe;

net/netfilter/ipvs/ip_vs_ctl.c

3344

pe = rcu_dereference_protected(svc->pe, 1);

net/netfilter/ipvs/ip_vs_ctl.c

3346

(pe && nla_put_string(skb, IPVS_SVC_ATTR_PE_NAME, pe->name)) ||

net/netfilter/ipvs/ip_vs_pe.c

101

list_del_rcu(&pe->n_list);

net/netfilter/ipvs/ip_vs_pe.c

107

pr_info("[%s] pe unregistered.\n", pe->name);

net/netfilter/ipvs/ip_vs_pe.c

22

struct ip_vs_pe *pe;

net/netfilter/ipvs/ip_vs_pe.c

28

list_for_each_entry_rcu(pe, &ip_vs_pe, n_list) {

net/netfilter/ipvs/ip_vs_pe.c

30

if (pe->module &&

net/netfilter/ipvs/ip_vs_pe.c

31

!try_module_get(pe->module)) {

net/netfilter/ipvs/ip_vs_pe.c

35

if (strcmp(pe_name, pe->name)==0) {

net/netfilter/ipvs/ip_vs_pe.c

38

return pe;

net/netfilter/ipvs/ip_vs_pe.c

40

module_put(pe->module);

net/netfilter/ipvs/ip_vs_pe.c

50

struct ip_vs_pe *pe;

net/netfilter/ipvs/ip_vs_pe.c

53

pe = __ip_vs_pe_getbyname(name);

net/netfilter/ipvs/ip_vs_pe.c

56

if (!pe) {

net/netfilter/ipvs/ip_vs_pe.c

58

pe = __ip_vs_pe_getbyname(name);

net/netfilter/ipvs/ip_vs_pe.c

61

return pe;

net/netfilter/ipvs/ip_vs_pe.c

65

int register_ip_vs_pe(struct ip_vs_pe *pe)

net/netfilter/ipvs/ip_vs_pe.c

78

if (strcmp(tmp->name, pe->name) == 0) {

net/netfilter/ipvs/ip_vs_pe.c

82

"in the system\n", __func__, pe->name);

net/netfilter/ipvs/ip_vs_pe.c

87

list_add_rcu(&pe->n_list, &ip_vs_pe);

net/netfilter/ipvs/ip_vs_pe.c

90

pr_info("[%s] pe registered.\n", pe->name);

net/netfilter/ipvs/ip_vs_pe.c

97

int unregister_ip_vs_pe(struct ip_vs_pe *pe)

net/netfilter/ipvs/ip_vs_sync.c

1190

ip_vs_pe_put(param.pe);

net/netfilter/ipvs/ip_vs_sync.c

658

pe_name_len = strnlen(cp->pe->name, IP_VS_PENAME_MAXLEN);

net/netfilter/ipvs/ip_vs_sync.c

765

memcpy(p, cp->pe->name, pe_name_len);

net/netfilter/ipvs/ip_vs_sync.c

814

p->pe = __ip_vs_pe_getbyname(buff);

net/netfilter/ipvs/ip_vs_sync.c

815

if (!p->pe) {

net/netfilter/ipvs/ip_vs_sync.c

827

module_put(p->pe->module);

net/smc/smc_pnet.c

729

struct smc_pnetids_ndev_entry *pe;

net/smc/smc_pnet.c

733

list_for_each_entry(pe, &sn->pnetids_ndev.list, list) {

net/smc/smc_pnet.c

734

if (smc_pnet_match(pnetid, pe->pnetid)) {

net/smc/smc_pnet.c

748

struct smc_pnetids_ndev_entry *pe, *pi;

net/smc/smc_pnet.c

750

pe = kzalloc_obj(*pe);

net/smc/smc_pnet.c

751

if (!pe)

net/smc/smc_pnet.c

758

kfree(pe);

net/smc/smc_pnet.c

762

refcount_set(&pe->refcnt, 1);

net/smc/smc_pnet.c

763

memcpy(pe->pnetid, pnetid, SMC_MAX_PNETID_LEN);

net/smc/smc_pnet.c

764

list_add_tail(&pe->list, &sn->pnetids_ndev.list);

net/smc/smc_pnet.c

774

struct smc_pnetids_ndev_entry *pe, *pe2;

net/smc/smc_pnet.c

777

list_for_each_entry_safe(pe, pe2, &sn->pnetids_ndev.list, list) {

net/smc/smc_pnet.c

778

if (smc_pnet_match(pnetid, pe->pnetid)) {

net/smc/smc_pnet.c

779

if (refcount_dec_and_test(&pe->refcnt)) {

net/smc/smc_pnet.c

780

list_del(&pe->list);

net/smc/smc_pnet.c

781

kfree(pe);

net/smc/smc_pnet.c

829

struct smc_pnetids_ndev_entry *pe, *temp_pe;

net/smc/smc_pnet.c

832

list_for_each_entry_safe(pe, temp_pe, &sn->pnetids_ndev.list, list) {

net/smc/smc_pnet.c

833

list_del(&pe->list);

net/smc/smc_pnet.c

834

kfree(pe);

scripts/genksyms/parse.y

36

remove_list(struct string_list **pb, struct string_list **pe)

scripts/genksyms/parse.y

38

struct string_list *b = *pb, *e = *pe;

tools/perf/pmu-events/empty-pmu-events.c

2857

static void decompress_event(int offset, struct pmu_event *pe)

tools/perf/pmu-events/empty-pmu-events.c

2861

pe->name = (*p == '\0' ? NULL : p);

tools/perf/pmu-events/empty-pmu-events.c

2863

pe->topic = (*p == '\0' ? NULL : p);

tools/perf/pmu-events/empty-pmu-events.c

2865

pe->desc = (*p == '\0' ? NULL : p);

tools/perf/pmu-events/empty-pmu-events.c

2867

pe->event = (*p == '\0' ? NULL : p);

tools/perf/pmu-events/empty-pmu-events.c

2869

pe->compat = (*p == '\0' ? NULL : p);

tools/perf/pmu-events/empty-pmu-events.c

2871

pe->deprecated = *p - '0';

tools/perf/pmu-events/empty-pmu-events.c

2873

pe->perpkg = *p - '0';

tools/perf/pmu-events/empty-pmu-events.c

2875

pe->unit = (*p == '\0' ? NULL : p);

tools/perf/pmu-events/empty-pmu-events.c

2877

pe->retirement_latency_mean = (*p == '\0' ? NULL : p);

tools/perf/pmu-events/empty-pmu-events.c

2879

pe->retirement_latency_min = (*p == '\0' ? NULL : p);

tools/perf/pmu-events/empty-pmu-events.c

2881

pe->retirement_latency_max = (*p == '\0' ? NULL : p);

tools/perf/pmu-events/empty-pmu-events.c

2883

pe->long_desc = (*p == '\0' ? NULL : p);

tools/perf/pmu-events/empty-pmu-events.c

2923

struct pmu_event pe = {

tools/perf/pmu-events/empty-pmu-events.c

2928

decompress_event(pmu->entries[i].offset, &pe);

tools/perf/pmu-events/empty-pmu-events.c

2929

if (!pe.name)

tools/perf/pmu-events/empty-pmu-events.c

2931

ret = fn(&pe, table, data);

tools/perf/pmu-events/empty-pmu-events.c

2944

struct pmu_event pe = {

tools/perf/pmu-events/empty-pmu-events.c

2952

decompress_event(pmu->entries[mid].offset, &pe);

tools/perf/pmu-events/empty-pmu-events.c

2954

if (!pe.name && !name)

tools/perf/pmu-events/empty-pmu-events.c

2957

if (!pe.name && name) {

tools/perf/pmu-events/empty-pmu-events.c

2961

if (pe.name && !name) {

tools/perf/pmu-events/empty-pmu-events.c

2966

cmp = strcasecmp(pe.name, name);

tools/perf/pmu-events/empty-pmu-events.c

2976

return fn ? fn(&pe, table, data) : 0;

tools/perf/pmu-events/pmu-events.h

86

typedef int (*pmu_event_iter_fn)(const struct pmu_event *pe,

tools/perf/tests/bp_signal.c

105

struct perf_event_attr pe;

tools/perf/tests/bp_signal.c

108

memset(&pe, 0, sizeof(struct perf_event_attr));

tools/perf/tests/bp_signal.c

109

pe.type = PERF_TYPE_BREAKPOINT;

tools/perf/tests/bp_signal.c

110

pe.size = sizeof(struct perf_event_attr);

tools/perf/tests/bp_signal.c

112

pe.config = 0;

tools/perf/tests/bp_signal.c

113

pe.bp_type = is_x ? HW_BREAKPOINT_X : HW_BREAKPOINT_W;

tools/perf/tests/bp_signal.c

114

pe.bp_addr = (unsigned long) addr;

tools/perf/tests/bp_signal.c

115

pe.bp_len = is_x ? default_breakpoint_len() : sizeof(long);

tools/perf/tests/bp_signal.c

117

pe.sample_period = 1;

tools/perf/tests/bp_signal.c

118

pe.sample_type = PERF_SAMPLE_IP;

tools/perf/tests/bp_signal.c

119

pe.wakeup_events = 1;

tools/perf/tests/bp_signal.c

121

pe.disabled = 1;

tools/perf/tests/bp_signal.c

122

pe.exclude_kernel = 1;

tools/perf/tests/bp_signal.c

123

pe.exclude_hv = 1;

tools/perf/tests/bp_signal.c

125

fd = sys_perf_event_open(&pe, 0, -1, -1,

tools/perf/tests/bp_signal.c

128

pr_debug("failed opening event %llx\n", pe.config);

tools/perf/tests/bp_signal_overflow.c

100

pe.exclude_hv = 1;

tools/perf/tests/bp_signal_overflow.c

102

fd = sys_perf_event_open(&pe, 0, -1, -1,

tools/perf/tests/bp_signal_overflow.c

105

pr_debug("failed opening event %llx\n", pe.config);

tools/perf/tests/bp_signal_overflow.c

65

struct perf_event_attr pe;

tools/perf/tests/bp_signal_overflow.c

85

memset(&pe, 0, sizeof(struct perf_event_attr));

tools/perf/tests/bp_signal_overflow.c

86

pe.type = PERF_TYPE_BREAKPOINT;

tools/perf/tests/bp_signal_overflow.c

87

pe.size = sizeof(struct perf_event_attr);

tools/perf/tests/bp_signal_overflow.c

89

pe.config = 0;

tools/perf/tests/bp_signal_overflow.c

90

pe.bp_type = HW_BREAKPOINT_X;

tools/perf/tests/bp_signal_overflow.c

91

pe.bp_addr = (unsigned long) test_function;

tools/perf/tests/bp_signal_overflow.c

92

pe.bp_len = default_breakpoint_len();

tools/perf/tests/bp_signal_overflow.c

94

pe.sample_period = THRESHOLD;

tools/perf/tests/bp_signal_overflow.c

95

pe.sample_type = PERF_SAMPLE_IP;

tools/perf/tests/bp_signal_overflow.c

96

pe.wakeup_events = 1;

tools/perf/tests/bp_signal_overflow.c

98

pe.disabled = 1;

tools/perf/tests/bp_signal_overflow.c

99

pe.exclude_kernel = 1;

tools/perf/tests/pmu-events.c

379

static int test__pmu_event_table_core_callback(const struct pmu_event *pe,

tools/perf/tests/pmu-events.c

387

if (strcmp(pe->pmu, "default_core"))

tools/perf/tests/pmu-events.c

396

if (strcmp(pe->name, event->name))

tools/perf/tests/pmu-events.c

401

if (compare_pmu_events(pe, event))

tools/perf/tests/pmu-events.c

404

pr_debug("testing event table %s: pass\n", pe->name);

tools/perf/tests/pmu-events.c

407

pr_err("testing event table: could not find event %s\n", pe->name);

tools/perf/tests/pmu-events.c

413

static int test__pmu_event_table_sys_callback(const struct pmu_event *pe,

tools/perf/tests/pmu-events.c

427

if (strcmp(pe->name, event->name))

tools/perf/tests/pmu-events.c

432

if (compare_pmu_events(pe, event))

tools/perf/tests/pmu-events.c

435

pr_debug("testing sys event table %s: pass\n", pe->name);

tools/perf/tests/pmu-events.c

438

pr_debug("testing sys event table: could not find event %s\n", pe->name);

tools/perf/util/intel-pt.c

2578

struct intel_pt_pebs_event *pe;

tools/perf/util/intel-pt.c

2590

pe = &ptq->pebs[hw_id];

tools/perf/util/intel-pt.c

2591

if (!pe->evsel) {

tools/perf/util/intel-pt.c

2597

err = intel_pt_do_synth_pebs_sample(ptq, pe->evsel, pe->id, pe->data_src_fmt);

tools/perf/util/pmu.c

1053

static int pmu_add_cpu_aliases_map_callback(const struct pmu_event *pe,

tools/perf/util/pmu.c

1059

perf_pmu__new_alias(pmu, pe->name, pe->desc, pe->event, /*val_fd=*/ -1,

tools/perf/util/pmu.c

1060

pe, EVENT_SRC_CPU_JSON);

tools/perf/util/pmu.c

1088

static int pmu_add_sys_aliases_iter_fn(const struct pmu_event *pe,

tools/perf/util/pmu.c

1094

if (!pe->compat || !pe->pmu) {

tools/perf/util/pmu.c

1099

if (!perf_pmu__match_wildcard_uncore(pmu->name, pe->pmu) &&

tools/perf/util/pmu.c

1100

!perf_pmu__match_wildcard_uncore(pmu->alias_name, pe->pmu)) {

tools/perf/util/pmu.c

1105

if (pmu_uncore_identifier_match(pe->compat, pmu->id)) {

tools/perf/util/pmu.c

1108

pe->name,

tools/perf/util/pmu.c

1109

pe->desc,

tools/perf/util/pmu.c

1110

pe->event,

tools/perf/util/pmu.c

1112

pe,

tools/perf/util/pmu.c

515

static int update_alias(const struct pmu_event *pe,

tools/perf/util/pmu.c

523

assign_str(pe->name, "desc", &data->alias->desc, pe->desc);

tools/perf/util/pmu.c

524

assign_str(pe->name, "long_desc", &data->alias->long_desc, pe->long_desc);

tools/perf/util/pmu.c

525

assign_str(pe->name, "topic", &data->alias->topic, pe->topic);

tools/perf/util/pmu.c

526

data->alias->per_pkg = pe->perpkg;

tools/perf/util/pmu.c

527

if (pe->event) {

tools/perf/util/pmu.c

530

data->alias->legacy_terms = strdup(pe->event);

tools/perf/util/pmu.c

533

data->alias->terms = strdup(pe->event);

tools/perf/util/pmu.c

536

if (!ret && pe->unit) {

tools/perf/util/pmu.c

539

ret = perf_pmu__convert_scale(pe->unit, &unit, &data->alias->scale);

tools/perf/util/pmu.c

543

if (!ret && pe->retirement_latency_mean) {

tools/perf/util/pmu.c

544

ret = parse_double(pe->retirement_latency_mean, NULL,

tools/perf/util/pmu.c

547

if (!ret && pe->retirement_latency_min) {

tools/perf/util/pmu.c

548

ret = parse_double(pe->retirement_latency_min, NULL,

tools/perf/util/pmu.c

551

if (!ret && pe->retirement_latency_max) {

tools/perf/util/pmu.c

552

ret = parse_double(pe->retirement_latency_max, NULL,

tools/perf/util/pmu.c

560

const struct pmu_event *pe, enum event_source src)

tools/perf/util/pmu.c

572

if (pe) {

tools/perf/util/pmu.c

573

long_desc = pe->long_desc;

tools/perf/util/pmu.c

574

topic = pe->topic;

tools/perf/util/pmu.c

575

unit = pe->unit;

tools/perf/util/pmu.c

576

perpkg = pe->perpkg;

tools/perf/util/pmu.c

577

deprecated = pe->deprecated;

tools/perf/util/pmu.c

578

if (pe->pmu && strcmp(pe->pmu, "default_core"))

tools/perf/util/pmu.c

579

pmu_name = pe->pmu;

tools/perf/util/pmu.c

595

if (!ret && pe && pe->retirement_latency_mean) {

tools/perf/util/pmu.c

596

ret = parse_double(pe->retirement_latency_mean, NULL,

tools/perf/util/pmu.c

599

if (!ret && pe && pe->retirement_latency_min) {

tools/perf/util/pmu.c

600

ret = parse_double(pe->retirement_latency_min, NULL,

tools/perf/util/pmu.c

603

if (!ret && pe && pe->retirement_latency_max) {

tools/perf/util/pmu.c

604

ret = parse_double(pe->retirement_latency_max, NULL,

tools/perf/util/python.c

299

tracepoint_field(const struct pyrf_event *pe, struct tep_format_field *field)

tools/perf/util/python.c

302

void *data = pe->sample.raw_data;

tools/testing/selftests/net/nettest.c

2017

struct protoent *pe;

tools/testing/selftests/net/nettest.c

2086

pe = getprotobyname(optarg);

tools/testing/selftests/net/nettest.c

2087

if (pe) {

tools/testing/selftests/net/nettest.c

2088

args.protocol = pe->p_proto;

tools/testing/selftests/resctrl/resctrl_val.c

100

perf_event_open(&imc_counters_config[i].pe, -1, cpu_no, -1,

tools/testing/selftests/resctrl/resctrl_val.c

105

imc_counters_config[i].pe.config);

tools/testing/selftests/resctrl/resctrl_val.c

34

struct perf_event_attr pe;

tools/testing/selftests/resctrl/resctrl_val.c

46

memset(&imc_counters_config[i].pe, 0,

tools/testing/selftests/resctrl/resctrl_val.c

48

imc_counters_config[i].pe.type = imc_counters_config[i].type;

tools/testing/selftests/resctrl/resctrl_val.c

49

imc_counters_config[i].pe.size = sizeof(struct perf_event_attr);

tools/testing/selftests/resctrl/resctrl_val.c

50

imc_counters_config[i].pe.disabled = 1;

tools/testing/selftests/resctrl/resctrl_val.c

51

imc_counters_config[i].pe.inherit = 1;

tools/testing/selftests/resctrl/resctrl_val.c

52

imc_counters_config[i].pe.exclude_guest = 0;

tools/testing/selftests/resctrl/resctrl_val.c

53

imc_counters_config[i].pe.config =

tools/testing/selftests/resctrl/resctrl_val.c

56

imc_counters_config[i].pe.sample_type = PERF_SAMPLE_IDENTIFIER;

tools/testing/selftests/resctrl/resctrl_val.c

57

imc_counters_config[i].pe.read_format =

tools/testing/selftests/user_events/perf_test.c

134

struct perf_event_attr pe = {0};

tools/testing/selftests/user_events/perf_test.c

159

pe.type = PERF_TYPE_TRACEPOINT;

tools/testing/selftests/user_events/perf_test.c

160

pe.size = sizeof(pe);

tools/testing/selftests/user_events/perf_test.c

161

pe.config = id;

tools/testing/selftests/user_events/perf_test.c

162

pe.sample_type = PERF_SAMPLE_RAW;

tools/testing/selftests/user_events/perf_test.c

163

pe.sample_period = 1;

tools/testing/selftests/user_events/perf_test.c

164

pe.wakeup_events = 1;

tools/testing/selftests/user_events/perf_test.c

167

fd = perf_event_open(&pe, 0, -1, -1, 0);

tools/testing/selftests/user_events/perf_test.c

199

struct perf_event_attr pe = {0};

tools/testing/selftests/user_events/perf_test.c

221

pe.type = PERF_TYPE_TRACEPOINT;

tools/testing/selftests/user_events/perf_test.c

222

pe.size = sizeof(pe);

tools/testing/selftests/user_events/perf_test.c

223

pe.config = id;

tools/testing/selftests/user_events/perf_test.c

224

pe.sample_type = PERF_SAMPLE_RAW;

tools/testing/selftests/user_events/perf_test.c

225

pe.sample_period = 1;

tools/testing/selftests/user_events/perf_test.c

226

pe.wakeup_events = 1;

tools/testing/selftests/user_events/perf_test.c

229

fd = perf_event_open(&pe, 0, -1, -1, 0);

tools/testing/selftests/user_events/perf_test.c

32

static long perf_event_open(struct perf_event_attr *pe, pid_t pid,

tools/testing/selftests/user_events/perf_test.c

35

return syscall(__NR_perf_event_open, pe, pid, cpu, group_fd, flags);