out_be64
DEF_MMIO_OUT_D(out_be64, 64, std);
out_be64(addr, swab64(val));
out_be64(addr, val);
out_be64(xd->trig_mmio, 0);
out_be64((u64 *)(&spin_table->addr_h),
out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND);
out_be64(&priv2->slb_index_W, slbe);
out_be64(&priv2->slb_esid_RW, 0);
out_be64(&priv2->slb_vsid_RW, slb->vsid);
out_be64(&priv2->slb_esid_RW, slb->esid);
out_be64(&priv2->spu_chnlcntptr_RW, zero_list[i].channel);
out_be64(&priv2->spu_chnldata_RW, 0);
out_be64(&priv2->spu_chnlcntptr_RW, count_list[i].channel);
out_be64(&priv2->spu_chnlcnt_RW, count_list[i].count);
out_be64(&priv2->slb_invalidate_all_W, 0UL);
out_be64(&priv2->spu_cfg_RW, tmp);
out_be64(&priv2->spu_cfg_RW, tmp);
out_be64(&ctx->spu->priv2->spu_privcntl_RW, val);
out_be64(&prob->mfc_ea_W, cmd->ea);
out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND);
out_be64(mfc_cntl, MFC_CNTL_PURGE_DMA_REQUEST);
out_be64(mfc_cntl, 0);
out_be64(&priv2->spu_chnlcntptr_RW, 1);
out_be64(&priv2->spu_chnldata_RW, 0UL);
out_be64(&priv2->spu_chnlcntptr_RW, idx);
out_be64(&priv2->spu_chnldata_RW, 0UL);
out_be64(&priv2->spu_chnlcnt_RW, 0UL);
out_be64(&priv2->spu_chnlcntptr_RW, idx);
out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
out_be64(&priv2->spu_privcntl_RW, csa->priv2.spu_privcntl_RW);
out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE);
out_be64(&priv2->puq[i].mfc_cq_data0_RW,
out_be64(&priv2->puq[i].mfc_cq_data1_RW,
out_be64(&priv2->puq[i].mfc_cq_data2_RW,
out_be64(&priv2->puq[i].mfc_cq_data3_RW,
out_be64(&priv2->spuq[i].mfc_cq_data0_RW,
out_be64(&priv2->spuq[i].mfc_cq_data1_RW,
out_be64(&priv2->spuq[i].mfc_cq_data2_RW,
out_be64(&priv2->spuq[i].mfc_cq_data3_RW,
out_be64(&priv2->spu_tag_status_query_RW,
out_be64(&priv2->spu_cmd_buf1_RW, csa->priv2.spu_cmd_buf1_RW);
out_be64(&priv2->spu_cmd_buf2_RW, csa->priv2.spu_cmd_buf2_RW);
out_be64(&priv2->spu_atomic_status_RW, csa->priv2.spu_atomic_status_RW);
out_be64(&priv2->spu_chnlcntptr_RW, idx);
out_be64(&priv2->spu_chnldata_RW, csa->spu_chnldata_RW[idx]);
out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[idx]);
out_be64(&priv2->spu_chnlcntptr_RW, idx);
out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
out_be64(&priv2->spu_lslr_RW, csa->priv2.spu_lslr_RW);
out_be64(&priv2->spu_cfg_RW, csa->priv2.spu_cfg_RW);
out_be64(&priv2->spu_chnlcntptr_RW, 29UL);
out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[29]);
out_be64(&priv2->spu_chnldata_RW, csa->spu_mailbox_data[i]);
out_be64(&priv2->mfc_control_RW, csa->priv2.mfc_control_RW);
out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE);
out_be64(&priv2->spu_privcntl_RW, 4LL);
out_be64(&priv2->spu_privcntl_RW, SPU_PRIVCNT_LOAD_REQUEST_NORMAL);
out_be64(&priv2->mfc_control_RW,
out_be64(&prob->spc_mssync_RW, 1UL);
out_be64(&priv2->mfc_control_RW,
out_be64(&priv2->spu_privcntl_RW, 0UL);
out_be64(&priv2->spu_lslr_RW, LS_ADDR_MASK);
out_be64(&priv2->spu_chnlcntptr_RW, 1);
out_be64(&priv2->spu_chnlcntptr_RW, idx);
out_be64(&priv2->spu_chnldata_RW, 0UL);
out_be64(&priv2->spu_chnlcnt_RW, 0UL);
out_be64(&priv2->spu_chnlcntptr_RW, 29UL);
out_be64(&priv2->spu_chnlcnt_RW, 0UL);
out_be64(&priv2->spu_chnlcntptr_RW, 21UL);
out_be64(&priv2->spu_chnlcntptr_RW, idx);
out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESUME_DMA_QUEUE);
out_be64(&prob->mfc_ea_W, ea);
out_be64(&prob->mfc_union_W.all64, command.all64);
out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE |
out_be64(phb->regs + offset, val);
out_be64(arva + PNV_OCXL_ATSD_AVA, val);
out_be64(arva + PNV_OCXL_ATSD_LNCH, val);
out_be64(regptr, val);
out_be64(regptr, val);
out_be64(xd->trig_mmio, 0);
out_be64(xd->eoi_mmio + offset, data);
out_be64(xd->trig_mmio, 0);
#define fsl_iowrite64be(v, p) out_be64(p, v)
out_be64(spa->reg_tfc, reg);