pciefd_can_writereg
pciefd_can_writereg(priv, CANFD_CTL_RST_BIT, PCIEFD_REG_CAN_RX_CTL_SET);
pciefd_can_writereg(priv, (u32)priv->rx_dma_laddr,
pciefd_can_writereg(priv, dma_addr_h, PCIEFD_REG_CAN_RX_DMA_ADDR_H);
pciefd_can_writereg(priv, CANFD_CTL_UNC_BIT, PCIEFD_REG_CAN_RX_CTL_CLR);
pciefd_can_writereg(priv, CANFD_CTL_RST_BIT, PCIEFD_REG_CAN_RX_CTL_SET);
pciefd_can_writereg(priv, 0, PCIEFD_REG_CAN_RX_DMA_ADDR_L);
pciefd_can_writereg(priv, 0, PCIEFD_REG_CAN_RX_DMA_ADDR_H);
pciefd_can_writereg(priv, CANFD_CTL_RST_BIT, PCIEFD_REG_CAN_TX_CTL_SET);
pciefd_can_writereg(priv, (u32)priv->tx_dma_laddr,
pciefd_can_writereg(priv, dma_addr_h, PCIEFD_REG_CAN_TX_DMA_ADDR_H);
pciefd_can_writereg(priv, CANFD_CTL_UNC_BIT, PCIEFD_REG_CAN_TX_CTL_CLR);
pciefd_can_writereg(priv, CANFD_CTL_RST_BIT, PCIEFD_REG_CAN_TX_CTL_SET);
pciefd_can_writereg(priv, 0, PCIEFD_REG_CAN_TX_DMA_ADDR_L);
pciefd_can_writereg(priv, 0, PCIEFD_REG_CAN_TX_DMA_ADDR_H);
pciefd_can_writereg(priv, priv->irq_tag, PCIEFD_REG_CAN_RX_CTL_ACK);
pciefd_can_writereg(priv, CANFD_CTL_RST_BIT, PCIEFD_REG_CAN_TX_CTL_CLR);
pciefd_can_writereg(priv, (CANFD_CTL_IRQ_TL_DEF) << 8 |
pciefd_can_writereg(priv, CANFD_CTL_RST_BIT,
pciefd_can_writereg(priv, !CANFD_MISC_TS_RST,
pciefd_can_writereg(priv, CANFD_CTL_IEN_BIT,
pciefd_can_writereg(priv, *(u32 *)ucan->cmd_buffer,
pciefd_can_writereg(priv, *(u32 *)(ucan->cmd_buffer + 4),
pciefd_can_writereg(priv, CANFD_CTL_IEN_BIT,
pciefd_can_writereg(priv, 1, PCIEFD_REG_CAN_TX_REQ_ACC);
pciefd_can_writereg(priv, CANFD_MISC_TS_RST, PCIEFD_REG_CAN_MISC);
pciefd_can_writereg(priv, CANFD_CLK_SEL_80MHZ,