arch/arm/mach-dove/pcie.c

117

struct pcie_port *pp = sys->private_data;

arch/arm/mach-dove/pcie.c

180

struct pcie_port *pp = sys->private_data;

arch/arm/mach-dove/pcie.c

197

struct pcie_port *pp = &pcie_port[num_pcie_ports++];

arch/arm/mach-dove/pcie.c

31

static struct pcie_port pcie_port[2];

arch/arm/mach-dove/pcie.c

37

struct pcie_port *pp;

arch/arm/mach-dove/pcie.c

43

pp = &pcie_port[nr];

arch/arm/mach-dove/pcie.c

81

static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)

arch/arm/mach-dove/pcie.c

97

struct pcie_port *pp = sys->private_data;

arch/arm/mach-mv78xx0/pcie.c

100

struct pcie_port *pp;

arch/arm/mach-mv78xx0/pcie.c

106

pp = &pcie_port[nr];

arch/arm/mach-mv78xx0/pcie.c

125

static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)

arch/arm/mach-mv78xx0/pcie.c

141

struct pcie_port *pp = sys->private_data;

arch/arm/mach-mv78xx0/pcie.c

161

struct pcie_port *pp = sys->private_data;

arch/arm/mach-mv78xx0/pcie.c

224

struct pcie_port *pp = sys->private_data;

arch/arm/mach-mv78xx0/pcie.c

242

struct pcie_port *pp = &pcie_port[num_pcie_ports++];

arch/arm/mach-mv78xx0/pcie.c

33

static struct pcie_port pcie_port[8];

arch/arm/mach-mv78xx0/pcie.c

75

struct pcie_port *pp = pcie_port + i;

arch/mips/pci/pcie-octeon.c

1016

uint64_t write_address = (cvmx_pcie_get_mem_base_address(pcie_port) + 0x100000) | (1ull<<63);

arch/mips/pci/pcie-octeon.c

1035

cvmx_write_csr(CVMX_PEXP_NPEI_DBG_SELECT, (pcie_port) ? 0xd7fc : 0xcffc);

arch/mips/pci/pcie-octeon.c

105

static inline uint64_t cvmx_pcie_get_io_base_address(int pcie_port)

arch/mips/pci/pcie-octeon.c

1050

cvmx_write_csr(CVMX_PEXP_NPEI_DBG_SELECT, (pcie_port) ? 0xd00f : 0xc80f);

arch/mips/pci/pcie-octeon.c

1057

cvmx_dprintf("PCIe: Port %d aligning TLP counters as workaround to maintain ordering\n", pcie_port);

arch/mips/pci/pcie-octeon.c

1072

(pcie_port == 1))

arch/mips/pci/pcie-octeon.c

1080

pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));

arch/mips/pci/pcie-octeon.c

1081

cvmx_dprintf("PCIe: Port %d link active, %d lanes\n", pcie_port, pciercx_cfg032.s.nlw);

arch/mips/pci/pcie-octeon.c

1095

static int __cvmx_pcie_rc_initialize_link_gen2(int pcie_port)

arch/mips/pci/pcie-octeon.c

1103

pem_ctl_status.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(pcie_port));

arch/mips/pci/pcie-octeon.c

1105

cvmx_write_csr(CVMX_PEMX_CTL_STATUS(pcie_port), pem_ctl_status.u64);

arch/mips/pci/pcie-octeon.c

1113

pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));

arch/mips/pci/pcie-octeon.c

1124

pciercx_cfg448.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG448(pcie_port));

arch/mips/pci/pcie-octeon.c

1139

cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG448(pcie_port), pciercx_cfg448.u32);

arch/mips/pci/pcie-octeon.c

114

pcie_addr.io.port = pcie_port;

arch/mips/pci/pcie-octeon.c

1153

static int __cvmx_pcie_rc_initialize_gen2(int pcie_port)

arch/mips/pci/pcie-octeon.c

1179

qlmx_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(pcie_port));

arch/mips/pci/pcie-octeon.c

1182

pr_notice("PCIe: Port %d is disabled, skipping.\n", pcie_port);

arch/mips/pci/pcie-octeon.c

1191

pr_notice("PCIe: Port %d is SRIO, skipping.\n", pcie_port);

arch/mips/pci/pcie-octeon.c

1194

pr_notice("PCIe: Port %d is SGMII, skipping.\n", pcie_port);

arch/mips/pci/pcie-octeon.c

1197

pr_notice("PCIe: Port %d is XAUI, skipping.\n", pcie_port);

arch/mips/pci/pcie-octeon.c

1205

pr_notice("PCIe: Port %d is unknown, skipping.\n", pcie_port);

arch/mips/pci/pcie-octeon.c

1209

sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(pcie_port));

arch/mips/pci/pcie-octeon.c

1211

pr_notice("PCIe: Port %d is SRIO, skipping.\n", pcie_port);

arch/mips/pci/pcie-octeon.c

1221

cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);

arch/mips/pci/pcie-octeon.c

1222

cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);

arch/mips/pci/pcie-octeon.c

1223

cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);

arch/mips/pci/pcie-octeon.c

1224

cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);

arch/mips/pci/pcie-octeon.c

1225

cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);

arch/mips/pci/pcie-octeon.c

1226

cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);

arch/mips/pci/pcie-octeon.c

1227

cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);

arch/mips/pci/pcie-octeon.c

1228

cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);

arch/mips/pci/pcie-octeon.c

1229

cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);

arch/mips/pci/pcie-octeon.c

1230

cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);

arch/mips/pci/pcie-octeon.c

1231

cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);

arch/mips/pci/pcie-octeon.c

1232

cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);

arch/mips/pci/pcie-octeon.c

1233

cvmx_helper_qlm_jtag_update(pcie_port);

arch/mips/pci/pcie-octeon.c

1237

mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(pcie_port));

arch/mips/pci/pcie-octeon.c

1239

pr_notice("PCIe: Port %d in endpoint mode.\n", pcie_port);

arch/mips/pci/pcie-octeon.c

1245

if (pcie_port) {

arch/mips/pci/pcie-octeon.c

126

static inline uint64_t cvmx_pcie_get_io_size(int pcie_port)

arch/mips/pci/pcie-octeon.c

1262

if (pcie_port)

arch/mips/pci/pcie-octeon.c

1274

if (pcie_port)

arch/mips/pci/pcie-octeon.c

1281

if (pcie_port) {

arch/mips/pci/pcie-octeon.c

1299

if (CVMX_WAIT_FOR_FIELD64(CVMX_MIO_RST_CTLX(pcie_port), union cvmx_mio_rst_ctlx, rst_done, ==, 1, 10000)) {

arch/mips/pci/pcie-octeon.c

1300

pr_notice("PCIe: Port %d stuck in reset, skipping.\n", pcie_port);

arch/mips/pci/pcie-octeon.c

1305

pemx_bist_status.u64 = cvmx_read_csr(CVMX_PEMX_BIST_STATUS(pcie_port));

arch/mips/pci/pcie-octeon.c

1307

pr_notice("PCIe: BIST FAILED for port %d (0x%016llx)\n", pcie_port, CAST64(pemx_bist_status.u64));

arch/mips/pci/pcie-octeon.c

1308

pemx_bist_status2.u64 = cvmx_read_csr(CVMX_PEMX_BIST_STATUS2(pcie_port));

arch/mips/pci/pcie-octeon.c

1313

pr_notice("PCIe: BIST2 FAILED for port %d (0x%016llx)\n", pcie_port, CAST64(pemx_bist_status2.u64));

arch/mips/pci/pcie-octeon.c

1316

__cvmx_pcie_rc_initialize_config_space(pcie_port);

arch/mips/pci/pcie-octeon.c

1319

pciercx_cfg515.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG515(pcie_port));

arch/mips/pci/pcie-octeon.c

1321

cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG515(pcie_port), pciercx_cfg515.u32);

arch/mips/pci/pcie-octeon.c

1324

if (__cvmx_pcie_rc_initialize_link_gen2(pcie_port)) {

arch/mips/pci/pcie-octeon.c

1331

pciercx_cfg031.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG031(pcie_port));

arch/mips/pci/pcie-octeon.c

1333

cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG031(pcie_port), pciercx_cfg031.u32);

arch/mips/pci/pcie-octeon.c

1334

if (__cvmx_pcie_rc_initialize_link_gen2(pcie_port)) {

arch/mips/pci/pcie-octeon.c

1335

pr_notice("PCIe: Link timeout on port %d, probably the slot is empty\n", pcie_port);

arch/mips/pci/pcie-octeon.c

1348

mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */

arch/mips/pci/pcie-octeon.c

1364

for (i = 12 + pcie_port * 4; i < 16 + pcie_port * 4; i++) {

arch/mips/pci/pcie-octeon.c

1376

cvmx_write_csr(CVMX_PEMX_P2P_BARX_START(i, pcie_port), -1);

arch/mips/pci/pcie-octeon.c

1377

cvmx_write_csr(CVMX_PEMX_P2P_BARX_END(i, pcie_port), -1);

arch/mips/pci/pcie-octeon.c

1381

cvmx_write_csr(CVMX_PEMX_P2N_BAR0_START(pcie_port), 0);

arch/mips/pci/pcie-octeon.c

1389

cvmx_write_csr(CVMX_PEMX_P2N_BAR2_START(pcie_port), 0);

arch/mips/pci/pcie-octeon.c

139

static inline uint64_t cvmx_pcie_get_mem_base_address(int pcie_port)

arch/mips/pci/pcie-octeon.c

1398

pemx_bar_ctl.u64 = cvmx_read_csr(CVMX_PEMX_BAR_CTL(pcie_port));

arch/mips/pci/pcie-octeon.c

1403

cvmx_write_csr(CVMX_PEMX_BAR_CTL(pcie_port), pemx_bar_ctl.u64);

arch/mips/pci/pcie-octeon.c

1404

sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(pcie_port));

arch/mips/pci/pcie-octeon.c

1409

cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(pcie_port), sli_ctl_portx.u64);

arch/mips/pci/pcie-octeon.c

1412

cvmx_write_csr(CVMX_PEMX_P2N_BAR1_START(pcie_port), CVMX_PCIE_BAR1_RC_BASE);

arch/mips/pci/pcie-octeon.c

1421

cvmx_write_csr(CVMX_PEMX_BAR1_INDEXX(i, pcie_port), bar1_index.u64);

arch/mips/pci/pcie-octeon.c

1430

pemx_ctl_status.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(pcie_port));

arch/mips/pci/pcie-octeon.c

1432

cvmx_write_csr(CVMX_PEMX_CTL_STATUS(pcie_port), pemx_ctl_status.u64);

arch/mips/pci/pcie-octeon.c

1435

pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));

arch/mips/pci/pcie-octeon.c

1436

pr_notice("PCIe: Port %d link active, %d lanes, speed gen%d\n", pcie_port, pciercx_cfg032.s.nlw, pciercx_cfg032.s.ls);

arch/mips/pci/pcie-octeon.c

1448

static int cvmx_pcie_rc_initialize(int pcie_port)

arch/mips/pci/pcie-octeon.c

1452

result = __cvmx_pcie_rc_initialize_gen1(pcie_port);

arch/mips/pci/pcie-octeon.c

1454

result = __cvmx_pcie_rc_initialize_gen2(pcie_port);

arch/mips/pci/pcie-octeon.c

146

pcie_addr.mem.subdid = 3 + pcie_port;

arch/mips/pci/pcie-octeon.c

1543

static int octeon_pcie_read_config(unsigned int pcie_port, struct pci_bus *bus,

arch/mips/pci/pcie-octeon.c

1556

BUG_ON(pcie_port >= ARRAY_SIZE(enable_pcie_bus_num_war));

arch/mips/pci/pcie-octeon.c

1562

if (enable_pcie_bus_num_war[pcie_port])

arch/mips/pci/pcie-octeon.c

1566

pciercx_cfg006.u32 = cvmx_pcie_cfgx_read(pcie_port,

arch/mips/pci/pcie-octeon.c

1567

CVMX_PCIERCX_CFG006(pcie_port));

arch/mips/pci/pcie-octeon.c

1572

cvmx_pcie_cfgx_write(pcie_port,

arch/mips/pci/pcie-octeon.c

1573

CVMX_PCIERCX_CFG006(pcie_port),

arch/mips/pci/pcie-octeon.c

158

static inline uint64_t cvmx_pcie_get_mem_size(int pcie_port)

arch/mips/pci/pcie-octeon.c

1674

" size=%d ", pcie_port, bus_number, devfn, reg, size);

arch/mips/pci/pcie-octeon.c

1678

*val = cvmx_pcie_config_read32(pcie_port, bus_number,

arch/mips/pci/pcie-octeon.c

1682

*val = cvmx_pcie_config_read16(pcie_port, bus_number,

arch/mips/pci/pcie-octeon.c

1686

*val = cvmx_pcie_config_read8(pcie_port, bus_number,

arch/mips/pci/pcie-octeon.c

172

static uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset)

arch/mips/pci/pcie-octeon.c

1736

static int octeon_pcie_write_config(unsigned int pcie_port, struct pci_bus *bus,

arch/mips/pci/pcie-octeon.c

1742

BUG_ON(pcie_port >= ARRAY_SIZE(enable_pcie_bus_num_war));

arch/mips/pci/pcie-octeon.c

1744

if ((bus->parent == NULL) && (enable_pcie_bus_num_war[pcie_port]))

arch/mips/pci/pcie-octeon.c

1748

" reg=0x%03x size=%d val=%08x\n", pcie_port, bus_number, devfn,

arch/mips/pci/pcie-octeon.c

1754

cvmx_pcie_config_write32(pcie_port, bus_number, devfn >> 3,

arch/mips/pci/pcie-octeon.c

1758

cvmx_pcie_config_write16(pcie_port, bus_number, devfn >> 3,

arch/mips/pci/pcie-octeon.c

1762

cvmx_pcie_config_write8(pcie_port, bus_number, devfn >> 3,

arch/mips/pci/pcie-octeon.c

178

cvmx_write_csr(CVMX_PESCX_CFG_RD(pcie_port), pescx_cfg_rd.u64);

arch/mips/pci/pcie-octeon.c

179

pescx_cfg_rd.u64 = cvmx_read_csr(CVMX_PESCX_CFG_RD(pcie_port));

arch/mips/pci/pcie-octeon.c

185

cvmx_write_csr(CVMX_PEMX_CFG_RD(pcie_port), pemx_cfg_rd.u64);

arch/mips/pci/pcie-octeon.c

186

pemx_cfg_rd.u64 = cvmx_read_csr(CVMX_PEMX_CFG_RD(pcie_port));

arch/mips/pci/pcie-octeon.c

199

static void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset,

arch/mips/pci/pcie-octeon.c

207

cvmx_write_csr(CVMX_PESCX_CFG_WR(pcie_port), pescx_cfg_wr.u64);

arch/mips/pci/pcie-octeon.c

213

cvmx_write_csr(CVMX_PEMX_CFG_WR(pcie_port), pemx_cfg_wr.u64);

arch/mips/pci/pcie-octeon.c

228

static inline uint64_t __cvmx_pcie_build_config_addr(int pcie_port, int bus,

arch/mips/pci/pcie-octeon.c

236

cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG006(pcie_port));

arch/mips/pci/pcie-octeon.c

241

cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));

arch/mips/pci/pcie-octeon.c

251

pcie_addr.config.port = pcie_port;

arch/mips/pci/pcie-octeon.c

271

static uint8_t cvmx_pcie_config_read8(int pcie_port, int bus, int dev,

arch/mips/pci/pcie-octeon.c

275

__cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);

arch/mips/pci/pcie-octeon.c

293

static uint16_t cvmx_pcie_config_read16(int pcie_port, int bus, int dev,

arch/mips/pci/pcie-octeon.c

297

__cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);

arch/mips/pci/pcie-octeon.c

315

static uint32_t cvmx_pcie_config_read32(int pcie_port, int bus, int dev,

arch/mips/pci/pcie-octeon.c

319

__cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);

arch/mips/pci/pcie-octeon.c

336

static void cvmx_pcie_config_write8(int pcie_port, int bus, int dev, int fn,

arch/mips/pci/pcie-octeon.c

340

__cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);

arch/mips/pci/pcie-octeon.c

355

static void cvmx_pcie_config_write16(int pcie_port, int bus, int dev, int fn,

arch/mips/pci/pcie-octeon.c

359

__cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);

arch/mips/pci/pcie-octeon.c

374

static void cvmx_pcie_config_write32(int pcie_port, int bus, int dev, int fn,

arch/mips/pci/pcie-octeon.c

378

__cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);

arch/mips/pci/pcie-octeon.c

388

static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)

arch/mips/pci/pcie-octeon.c

408

pciercx_cfg030.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG030(pcie_port));

arch/mips/pci/pcie-octeon.c

431

cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG030(pcie_port), pciercx_cfg030.u32);

arch/mips/pci/pcie-octeon.c

447

if (pcie_port)

arch/mips/pci/pcie-octeon.c

462

prt_cfg.u64 = cvmx_read_csr(CVMX_DPI_SLI_PRTX_CFG(pcie_port));

arch/mips/pci/pcie-octeon.c

467

cvmx_write_csr(CVMX_DPI_SLI_PRTX_CFG(pcie_port), prt_cfg.u64);

arch/mips/pci/pcie-octeon.c

469

sli_s2m_portx_ctl.u64 = cvmx_read_csr(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port));

arch/mips/pci/pcie-octeon.c

471

cvmx_write_csr(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port), sli_s2m_portx_ctl.u64);

arch/mips/pci/pcie-octeon.c

475

pciercx_cfg070.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG070(pcie_port));

arch/mips/pci/pcie-octeon.c

478

cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG070(pcie_port), pciercx_cfg070.u32);

arch/mips/pci/pcie-octeon.c

486

pciercx_cfg001.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG001(pcie_port));

arch/mips/pci/pcie-octeon.c

491

cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG001(pcie_port), pciercx_cfg001.u32);

arch/mips/pci/pcie-octeon.c

495

cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG066(pcie_port), 0);

arch/mips/pci/pcie-octeon.c

497

cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG069(pcie_port), 0);

arch/mips/pci/pcie-octeon.c

501

pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));

arch/mips/pci/pcie-octeon.c

503

cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG032(pcie_port), pciercx_cfg032.u32);

arch/mips/pci/pcie-octeon.c

518

cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG006(pcie_port), pciercx_cfg006.u32);

arch/mips/pci/pcie-octeon.c

529

cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG008(pcie_port), pciercx_cfg008.u32);

arch/mips/pci/pcie-octeon.c

538

pciercx_cfg009.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG009(pcie_port));

arch/mips/pci/pcie-octeon.c

539

pciercx_cfg010.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG010(pcie_port));

arch/mips/pci/pcie-octeon.c

540

pciercx_cfg011.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG011(pcie_port));

arch/mips/pci/pcie-octeon.c

545

cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG009(pcie_port), pciercx_cfg009.u32);

arch/mips/pci/pcie-octeon.c

546

cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG010(pcie_port), pciercx_cfg010.u32);

arch/mips/pci/pcie-octeon.c

547

cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG011(pcie_port), pciercx_cfg011.u32);

arch/mips/pci/pcie-octeon.c

553

pciercx_cfg035.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG035(pcie_port));

arch/mips/pci/pcie-octeon.c

558

cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG035(pcie_port), pciercx_cfg035.u32);

arch/mips/pci/pcie-octeon.c

564

pciercx_cfg075.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG075(pcie_port));

arch/mips/pci/pcie-octeon.c

568

cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG075(pcie_port), pciercx_cfg075.u32);

arch/mips/pci/pcie-octeon.c

574

pciercx_cfg034.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG034(pcie_port));

arch/mips/pci/pcie-octeon.c

578

cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG034(pcie_port), pciercx_cfg034.u32);

arch/mips/pci/pcie-octeon.c

590

static int __cvmx_pcie_rc_initialize_link_gen1(int pcie_port)

arch/mips/pci/pcie-octeon.c

599

pciercx_cfg452.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG452(pcie_port));

arch/mips/pci/pcie-octeon.c

600

pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port));

arch/mips/pci/pcie-octeon.c

607

cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG452(pcie_port), pciercx_cfg452.u32);

arch/mips/pci/pcie-octeon.c

616

pciercx_cfg455.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG455(pcie_port));

arch/mips/pci/pcie-octeon.c

618

cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG455(pcie_port), pciercx_cfg455.u32);

arch/mips/pci/pcie-octeon.c

622

if (OCTEON_IS_MODEL(OCTEON_CN52XX) && (pcie_port == 1)) {

arch/mips/pci/pcie-octeon.c

624

cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port), pescx_ctl_status.u64);

arch/mips/pci/pcie-octeon.c

628

pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port));

arch/mips/pci/pcie-octeon.c

630

cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port), pescx_ctl_status.u64);

arch/mips/pci/pcie-octeon.c

643

cvmx_dprintf("PCIe: Port %d link timeout\n", pcie_port);

arch/mips/pci/pcie-octeon.c

647

pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));

arch/mips/pci/pcie-octeon.c

661

pciercx_cfg448.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG448(pcie_port));

arch/mips/pci/pcie-octeon.c

676

cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG448(pcie_port), pciercx_cfg448.u32);

arch/mips/pci/pcie-octeon.c

697

static int __cvmx_pcie_rc_initialize_gen1(int pcie_port)

arch/mips/pci/pcie-octeon.c

719

if ((pcie_port == 0) && !npei_ctl_status.s.host_mode) {

arch/mips/pci/pcie-octeon.c

720

cvmx_dprintf("PCIe: Port %d in endpoint mode\n", pcie_port);

arch/mips/pci/pcie-octeon.c

730

if ((pcie_port == 1) && npei_dbg_data.cn52xx.qlm0_link_width) {

arch/mips/pci/pcie-octeon.c

762

if (pcie_port == 0) {

arch/mips/pci/pcie-octeon.c

793

if (pcie_port)

arch/mips/pci/pcie-octeon.c

805

if (pcie_port)

arch/mips/pci/pcie-octeon.c

812

if (pcie_port) {

arch/mips/pci/pcie-octeon.c

836

pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));

arch/mips/pci/pcie-octeon.c

838

cvmx_write_csr(CVMX_PESCX_CTL_STATUS2(pcie_port), pescx_ctl_status2.u64);

arch/mips/pci/pcie-octeon.c

842

if (CVMX_WAIT_FOR_FIELD64(CVMX_PESCX_CTL_STATUS2(pcie_port),

arch/mips/pci/pcie-octeon.c

844

cvmx_dprintf("PCIe: Port %d isn't clocked, skipping.\n", pcie_port);

arch/mips/pci/pcie-octeon.c

854

pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));

arch/mips/pci/pcie-octeon.c

856

cvmx_dprintf("PCIe: Port %d stuck in reset, skipping.\n", pcie_port);

arch/mips/pci/pcie-octeon.c

865

pescx_bist_status2.u64 = cvmx_read_csr(CVMX_PESCX_BIST_STATUS2(pcie_port));

arch/mips/pci/pcie-octeon.c

868

pcie_port);

arch/mips/pci/pcie-octeon.c

873

pescx_bist_status.u64 = cvmx_read_csr(CVMX_PESCX_BIST_STATUS(pcie_port));

arch/mips/pci/pcie-octeon.c

876

pcie_port, CAST64(pescx_bist_status.u64));

arch/mips/pci/pcie-octeon.c

879

__cvmx_pcie_rc_initialize_config_space(pcie_port);

arch/mips/pci/pcie-octeon.c

882

if (__cvmx_pcie_rc_initialize_link_gen1(pcie_port)) {

arch/mips/pci/pcie-octeon.c

884

pcie_port);

arch/mips/pci/pcie-octeon.c

896

mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */

arch/mips/pci/pcie-octeon.c

910

for (i = 12 + pcie_port * 4; i < 16 + pcie_port * 4; i++) {

arch/mips/pci/pcie-octeon.c

921

cvmx_write_csr(CVMX_PESCX_P2P_BARX_START(i, pcie_port), -1);

arch/mips/pci/pcie-octeon.c

922

cvmx_write_csr(CVMX_PESCX_P2P_BARX_END(i, pcie_port), -1);

arch/mips/pci/pcie-octeon.c

926

cvmx_write_csr(CVMX_PESCX_P2N_BAR0_START(pcie_port), 0);

arch/mips/pci/pcie-octeon.c

929

cvmx_write_csr(CVMX_PESCX_P2N_BAR1_START(pcie_port), CVMX_PCIE_BAR1_RC_BASE);

arch/mips/pci/pcie-octeon.c

937

base = pcie_port ? 16 : 0;

arch/mips/pci/pcie-octeon.c

95

static int cvmx_pcie_rc_initialize(int pcie_port);

arch/mips/pci/pcie-octeon.c

959

cvmx_write_csr(CVMX_PESCX_P2N_BAR2_START(pcie_port), 0);

arch/mips/pci/pcie-octeon.c

970

if (pcie_port) {

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

1074

CN23XX_SLI_MAC_PF_INT_SUM64(oct->pcie_port, oct->pf_num);

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

1077

CN23XX_SLI_MAC_PF_INT_ENB64(oct->pcie_port, oct->pf_num);

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

134

u16 mac_no = oct->pcie_port;

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

254

reg_val = (u64)oct->pcie_port << CN23XX_PKT_INPUT_CTL_MAC_NUM_POS;

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

543

u16 mac_no = oct->pcie_port;

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

879

oct, CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx));

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

882

CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx));

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

884

oct, CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx));

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

893

CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx));

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

896

oct, CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx)));

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

902

CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx));

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

908

oct, CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx));

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

979

oct->pcie_port = (octeon_read_csr(oct, CN23XX_SLI_MAC_NUMBER)) & 0xff;

drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

982

oct->pcie_port);

drivers/net/ethernet/cavium/liquidio/cn66xx_device.c

112

r64 = octeon_read_csr64(oct, CN6XXX_SLI_S2M_PORTX_CTL(oct->pcie_port));

drivers/net/ethernet/cavium/liquidio/cn66xx_device.c

114

octeon_write_csr64(oct, CN6XXX_SLI_S2M_PORTX_CTL(oct->pcie_port), r64);

drivers/net/ethernet/cavium/liquidio/cn66xx_device.c

117

r64 = lio_pci_readq(oct, CN6XXX_DPI_SLI_PRTX_CFG(oct->pcie_port));

drivers/net/ethernet/cavium/liquidio/cn66xx_device.c

119

lio_pci_writeq(oct, r64, CN6XXX_DPI_SLI_PRTX_CFG(oct->pcie_port));

drivers/net/ethernet/cavium/liquidio/cn66xx_device.c

167

(oct->pcie_port * 0x5555555555555555ULL));

drivers/net/ethernet/cavium/liquidio/cn66xx_device.c

200

(oct->pcie_port * 0x5555555555555555ULL));

drivers/net/ethernet/cavium/liquidio/cn66xx_device.c

420

bar1 = lio_pci_readq(oct, CN6XXX_BAR1_REG(idx, oct->pcie_port));

drivers/net/ethernet/cavium/liquidio/cn66xx_device.c

422

CN6XXX_BAR1_REG(idx, oct->pcie_port));

drivers/net/ethernet/cavium/liquidio/cn66xx_device.c

423

bar1 = lio_pci_readq(oct, CN6XXX_BAR1_REG(idx, oct->pcie_port));

drivers/net/ethernet/cavium/liquidio/cn66xx_device.c

431

CN6XXX_BAR1_REG(idx, oct->pcie_port));

drivers/net/ethernet/cavium/liquidio/cn66xx_device.c

433

bar1 = lio_pci_readq(oct, CN6XXX_BAR1_REG(idx, oct->pcie_port));

drivers/net/ethernet/cavium/liquidio/cn66xx_device.c

440

lio_pci_writeq(oct, mask, CN6XXX_BAR1_REG(idx, oct->pcie_port));

drivers/net/ethernet/cavium/liquidio/cn66xx_device.c

445

return (u32)lio_pci_readq(oct, CN6XXX_BAR1_REG(idx, oct->pcie_port));

drivers/net/ethernet/cavium/liquidio/cn66xx_device.c

494

oct->pcie_port = octeon_read_csr(oct, CN6XXX_SLI_MAC_NUMBER) & 0xff;

drivers/net/ethernet/cavium/liquidio/cn66xx_device.c

496

dev_dbg(&oct->pci_dev->dev, "Using PCIE Port %d\n", oct->pcie_port);

drivers/net/ethernet/cavium/liquidio/cn66xx_device.c

647

bar0_pciaddr + CN6XXX_SLI_INT_ENB64(oct->pcie_port);

drivers/net/ethernet/cavium/liquidio/cn66xx_device.c

89

r64 = lio_pci_readq(oct, CN6XXX_DPI_SLI_PRTX_CFG(oct->pcie_port));

drivers/net/ethernet/cavium/liquidio/cn66xx_device.c

91

lio_pci_writeq(oct, r64, CN6XXX_DPI_SLI_PRTX_CFG(oct->pcie_port));

drivers/net/ethernet/cavium/liquidio/lio_ethtool.c

2553

reg = CN23XX_SLI_PKT_MAC_RINFO64(oct->pcie_port, oct->pf_num);

drivers/net/ethernet/cavium/liquidio/lio_ethtool.c

2556

reg, oct->pcie_port, oct->pf_num,

drivers/net/ethernet/cavium/liquidio/lio_ethtool.c

2560

reg = CN23XX_SLI_MAC_PF_INT_ENB64(oct->pcie_port, oct->pf_num);

drivers/net/ethernet/cavium/liquidio/lio_ethtool.c

2563

reg, oct->pcie_port, oct->pf_num,

drivers/net/ethernet/cavium/liquidio/lio_ethtool.c

2567

reg = CN23XX_SLI_MAC_PF_INT_SUM64(oct->pcie_port, oct->pf_num);

drivers/net/ethernet/cavium/liquidio/lio_ethtool.c

2570

reg, oct->pcie_port, oct->pf_num,

drivers/net/ethernet/cavium/liquidio/lio_ethtool.c

2579

reg = 0x27300 + oct->pcie_port * CN23XX_MAC_INT_OFFSET +

drivers/net/ethernet/cavium/liquidio/lio_ethtool.c

2583

oct->pcie_port, oct->pf_num, (u64)octeon_read_csr64(oct, reg));

drivers/net/ethernet/cavium/liquidio/lio_ethtool.c

2586

reg = 0x27200 + oct->pcie_port * CN23XX_MAC_INT_OFFSET +

drivers/net/ethernet/cavium/liquidio/lio_ethtool.c

2590

reg, oct->pcie_port, oct->pf_num,

drivers/net/ethernet/cavium/liquidio/lio_ethtool.c

2976

reg = lio_pci_readq(oct, CN6XXX_BAR1_REG(i, oct->pcie_port));

drivers/net/ethernet/cavium/liquidio/lio_ethtool.c

2978

CN6XXX_BAR1_REG(i, oct->pcie_port), i, reg);

drivers/net/ethernet/cavium/liquidio/liquidio_common.h

565

u64 pcie_port:3;

drivers/net/ethernet/cavium/liquidio/liquidio_common.h

569

u64 pcie_port:3;

drivers/net/ethernet/cavium/liquidio/octeon_device.h

463

u16 pcie_port;

drivers/net/ethernet/cavium/liquidio/octeon_nic.c

68

rdp->pcie_port = oct->pcie_port;

drivers/net/ethernet/cavium/liquidio/request_manager.c

632

rdp->pcie_port = oct->pcie_port;

drivers/net/ethernet/cavium/liquidio/request_manager.c

669

rdp->pcie_port = oct->pcie_port;

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

188

if (oct->pcie_port)

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

218

val = octep_read_csr64(oct, CN93_SDP_MAC_PF_RING_CTL(oct->pcie_port));

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

917

oct->pcie_port = octep_read_csr64(oct, CN93_SDP_MAC_NUMBER) & 0xff;

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

919

"Octeon device using PCIE Port %d\n", oct->pcie_port);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

212

if (oct->pcie_port)

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

243

val = octep_read_csr64(oct, CNXK_SDP_MAC_PF_RING_CTL(oct->pcie_port));

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

244

dev_info(&pdev->dev, "SDP_MAC_PF_RING_CTL[%d]:0x%llx\n", oct->pcie_port, val);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

953

oct->pcie_port = octep_read_csr64(oct, CNXK_SDP_MAC_NUMBER) & 0xff;

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

955

"Octeon device using PCIE Port %d\n", oct->pcie_port);

drivers/net/ethernet/marvell/octeon_ep/octep_main.h

273

u16 pcie_port;

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_main.h

261

u16 pcie_port;

drivers/phy/hisilicon/phy-hi3670-pcie.c

561

struct device_node *pcie_port;

drivers/phy/hisilicon/phy-hi3670-pcie.c

565

pcie_port = of_get_child_by_name(dev->parent->of_node, "pcie");

drivers/phy/hisilicon/phy-hi3670-pcie.c

566

if (!pcie_port) {

drivers/phy/hisilicon/phy-hi3670-pcie.c

572

pcie_dev = bus_find_device_by_of_node(&platform_bus_type, pcie_port);