pci_write_reg
pci_write_reg(chan, bcr1, SH4_PCIBCR1);
pci_write_reg(chan, mcr, SH4_PCIMCR);
pci_write_reg(chan, 0x0c000000, SH7751_PCICONF5);
pci_write_reg(chan, 0xd0000000, SH7751_PCICONF6);
pci_write_reg(chan, 0x0c000000, SH4_PCILAR0);
pci_write_reg(chan, 0x00000000, SH4_PCILAR1);
pci_write_reg(chan, bcr1, SH4_PCIBCR1);
pci_write_reg(chan, 0x0000c3ff, SH4_PCIINTM);
pci_write_reg(chan, 0x0000380f, SH4_PCIAINTM);
pci_write_reg(chan, 0xfb900047, SH7751_PCICONF1);
pci_write_reg(chan, 0xab000001, SH7751_PCICONF4);
pci_write_reg(chan, mcr, SH4_PCIMCR);
pci_write_reg(chan, 0x0c000000, SH7751_PCICONF5);
pci_write_reg(chan, 0xd0000000, SH7751_PCICONF6);
pci_write_reg(chan, 0x0c000000, SH4_PCILAR0);
pci_write_reg(chan, 0x00000000, SH4_PCILAR1);
pci_write_reg(chan, CONFIG_CMD(bus, devfn, where), SH4_PCIPAR);
pci_write_reg(chan, CONFIG_CMD(bus, devfn, where), SH4_PCIPAR);
pci_write_reg(chan, data, SH4_PCIPDR);
pci_write_reg(chan, *data, PCI_REG(reg));
pci_write_reg(chan, pci_read_reg(chan, SH4A_PCIEERRFR), SH4A_PCIEERRFR);
pci_write_reg(chan, (bus->number << 24) | (dev << 19) |
pci_write_reg(chan, (1 << 31) | (type << 8), SH4A_PCIEPCTLR);
pci_write_reg(chan, *data, SH4A_PCIEPDR);
pci_write_reg(chan, 0, SH4A_PCIEPCTLR);
pci_write_reg(chan, word, SH4_PCIPINT);
pci_write_reg(chan, word, SH7751_PCICONF1);
pci_write_reg(chan, word, SH7751_PCICONF2);
pci_write_reg(chan, word, SH4_PCILSR0);
pci_write_reg(chan, word, SH4_PCILAR0);
pci_write_reg(chan, word, SH7751_PCICONF5);
pci_write_reg(chan, word , SH4_PCIMBR);
pci_write_reg(chan, word, SH4_PCIIOBR);
pci_write_reg(chan, word, SH4_PCIWCR1);
pci_write_reg(chan, word, SH4_PCIWCR2);
pci_write_reg(chan, word, SH4_PCIWCR3);
pci_write_reg(chan, word, SH4_PCIMCR);
pci_write_reg(chan, word, SH4_PCICR);
pci_write_reg(chan, word, SH4_PCIBCR1);
pci_write_reg(chan, word, SH4_PCIBCR2);
pci_write_reg(chan, 0, SH4_PCICLKR);
pci_write_reg(chan, data, SH4A_PCIEPHYDOUTR);
pci_write_reg(chan, phyaddr, SH4A_PCIEPHYADRR);
pci_write_reg(chan, 0, SH4A_PCIEPHYDOUTR);
pci_write_reg(chan, 0, SH4A_PCIEPHYADRR);
pci_write_reg(chan, 1, SH4A_PCIESRSTR);
pci_write_reg(chan, 0, SH4A_PCIETCTLR);
pci_write_reg(chan, 0, SH4A_PCIESRSTR);
pci_write_reg(chan, 0, SH4A_PCIETXVC0SR);
pci_write_reg(chan, PCI_CLASS_BRIDGE_PCI_NORMAL << 8, SH4A_PCIEIDSETR1);
pci_write_reg(chan, data, SH4A_PCIEEXPCAP0);
pci_write_reg(chan, PCI_EXP_LNKCAP_DLLLARC, SH4A_PCIEEXPCAP3);
pci_write_reg(chan, data, SH4A_PCIEEXPCAP4);
pci_write_reg(chan, data, SH4A_PCIEEXPCAP5);
pci_write_reg(chan, data, SH4A_PCIETLCTLR);
pci_write_reg(chan, data, SH4A_PCIEMACCTLR);
pci_write_reg(chan, memstart + SZ_512M, SH4A_PCIELAR1);
pci_write_reg(chan, ((memsize - SZ_512M) - SZ_256) | 1,
pci_write_reg(chan, 0, SH4A_PCIELAR1);
pci_write_reg(chan, 0, SH4A_PCIELAMR1);
pci_write_reg(chan, memstart, SH4A_PCIELAR0);
pci_write_reg(chan, (memsize - SZ_256) | 1, SH4A_PCIELAMR0);
pci_write_reg(chan, data, SH4A_PCIETCTLR);
pci_write_reg(chan, data, SH4A_PCIEDLINTENR);
pci_write_reg(chan, data, SH4A_PCIEMACCTLR);
pci_write_reg(chan, data, SH4A_PCIEPCICONF1);
pci_write_reg(chan, 0x80888000, SH4A_PCIETXVC0DCTLR);
pci_write_reg(chan, 0x00222000, SH4A_PCIERXVC0DCTLR);
pci_write_reg(chan, 0x00000000, SH4A_PCIEPTCTLR(win));
pci_write_reg(chan, mask << 18, SH4A_PCIEPAMR(win));
pci_write_reg(chan, upper_32_bits(res->start),
pci_write_reg(chan, lower_32_bits(res->start),
pci_write_reg(chan, mask, SH4A_PCIEPTCTLR(win));