drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

274

static const struct dce_opp_registers opp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

275

opp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

276

opp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

277

opp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

278

opp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

279

opp_regs(4),

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

280

opp_regs(5)

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

695

ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

303

static const struct dce_opp_registers opp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

304

opp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

305

opp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

306

opp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

307

opp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

308

opp_regs(4),

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

309

opp_regs(5)

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

719

ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

312

static const struct dce_opp_registers opp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

313

opp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

314

opp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

315

opp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

316

opp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

317

opp_regs(4),

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

318

opp_regs(5)

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

695

ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

321

static const struct dce_opp_registers opp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

322

opp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

323

opp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

324

opp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

325

opp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

326

opp_regs(4),

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

327

opp_regs(5)

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

437

ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

291

static const struct dce_opp_registers opp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

292

opp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

293

opp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

294

opp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

295

opp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

296

opp_regs(4),

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

297

opp_regs(5)

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

530

ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

290

static const struct dce_opp_registers opp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

291

opp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

292

opp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

293

opp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

294

opp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

295

opp_regs(4),

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

296

opp_regs(5)

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

536

ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

319

static const struct dcn10_opp_registers opp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

320

opp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

321

opp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

322

opp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

323

opp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

644

&opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

380

static const struct dcn20_opp_registers opp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

381

opp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

382

opp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

383

opp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

384

opp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

385

opp_regs(4),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

386

opp_regs(5),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

810

&opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

440

static const struct dcn201_opp_registers opp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

441

opp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

442

opp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

676

&opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1071

&opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

242

static const struct dcn20_opp_registers opp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

243

opp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

244

opp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

245

opp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

246

opp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

247

opp_regs(4),

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

248

opp_regs(5),

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

483

static const struct dcn20_opp_registers opp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

484

opp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

485

opp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

486

opp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

487

opp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

488

opp_regs(4),

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

489

opp_regs(5)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

825

&opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

429

static const struct dcn20_opp_registers opp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

430

opp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

431

opp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

432

opp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

433

opp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

747

&opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

675

static const struct dcn20_opp_registers opp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

676

opp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

677

opp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

678

opp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

679

opp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

680

opp_regs(4)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

700

dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

653

static const struct dcn20_opp_registers opp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

654

opp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

655

opp_regs(1)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

675

dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1007

&opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

543

static const struct dcn20_opp_registers opp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

544

opp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

545

opp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

546

opp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

547

opp_regs(3)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1042

&opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

549

static const struct dcn20_opp_registers opp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

550

opp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

551

opp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

552

opp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

553

opp_regs(3)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1006

&opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

546

static const struct dcn20_opp_registers opp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

547

opp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

548

opp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

549

opp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

550

opp_regs(3)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

537

static const struct dcn20_opp_registers opp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

538

opp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

539

opp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

540

opp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

541

opp_regs(3)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

999

&opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1056

#define REG_STRUCT opp_regs

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1063

&opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

425

static struct dcn20_opp_registers opp_regs[4];

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1044

#define REG_STRUCT opp_regs

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1051

&opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

418

static struct dcn20_opp_registers opp_regs[4];

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

437

static struct dcn35_opp_registers opp_regs[4];

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

902

#define REG_STRUCT opp_regs

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

909

&opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

417

static struct dcn35_opp_registers opp_regs[4];

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

882

#define REG_STRUCT opp_regs

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

889

&opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

418

static struct dcn35_opp_registers opp_regs[4];

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

889

#define REG_STRUCT opp_regs

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

896

&opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1046

#define REG_STRUCT opp_regs

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1053

&opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

398

static struct dcn20_opp_registers opp_regs[4];

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1080

#define REG_STRUCT opp_regs

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1086

&opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

370

static struct dcn20_opp_registers opp_regs[4];

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1115

#define REG_STRUCT opp_regs

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1122

&opp_regs[inst], &opp_shift, &opp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

394

static struct dcn20_opp_registers opp_regs[4];