pch_dbg
pch_dbg(adap, "Fast mode enabled\n");
pch_dbg(adap,
pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR));
pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
pch_dbg(adap, "Receive NACK for slave address setting\n");
pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL),
pch_dbg(adap, "writing %x to Data register\n", buf[wrcount]);
pch_dbg(adap, "return=%d\n", wrcount);
pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR));
pch_dbg(adap, "adap->p_adapter_info->pch_i2c_suspended is %d\n",
pch_dbg(adap,