omap2_prm_write_mod_reg
omap2_prm_write_mod_reg(wkst, module, regs);
omap2_prm_write_mod_reg(v, module, idx);
omap2_prm_write_mod_reg(vp->tranxdone_status,
omap2_prm_write_mod_reg(val, OMAP3430_GR_MOD, offset);
omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
omap2_prm_write_mod_reg(saved_mask[0], OCP_MOD,
omap2_prm_write_mod_reg(wkst, module, wkst_off);
omap2_prm_write_mod_reg(
omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
omap2_prm_write_mod_reg(en_uart4_mask |
omap2_prm_write_mod_reg(grpsel_uart4_mask |
omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD,
omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD,
omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
omap2_prm_write_mod_reg(0, pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST);