parent_index
node->parent_index = (level > CPUINFO_LVL_ROOT)
node->parent_index = -1;
node->parent_index =
node = &t->nodes[node->parent_index];
int parent_index;
index = parent_index(sel, parent_sel);
index = parent_index(sel, parent_sel);
int parent_index;
.parent_index = -1,
.parent_index = -1,
.parent_index = MAX9485_CLKOUT,
.parent_index = MAX9485_CLKOUT,
int parent_index = max9485_clks[i].parent_index;
if (parent_index > 0) {
&drvdata->hw[parent_index].init.name;
static int scmi_clk_set_parent(struct clk_hw *hw, u8 parent_index)
return scmi_proto_clk_ops->parent_set(clk->ph, clk->id, parent_index);
clk->parent_index = msg.data.resp.parent;
clk->parent_index = index;
u8 parent_index;
clk->parent_index);
ret = clk_scu_set_parent(&clk->hw, clk->parent_index);
clk->parent_index, !ret ? "success" : "failed");
if (mux->data->parent_index) {
if (mux->data->parent_index[i] == val)
if (mux->data->parent_index)
index = mux->data->parent_index[index];
.parent_index = _paridx, \
const u8 *parent_index;
.parent_index = _paridx, \
parent = clk_hw_get_parent_by_index(hw, item->parent_index);
item->parent_index);
if (item->parent_index == index)
mux_val = _get_mux_val(mix, item->parent_index);
item->parent_index);
_get_mux_val(mix, item->parent_index),
u8 parent_index;
int parent_index)
if (parent_index < 0) {
parent_index = reg >> cm->shift;
parent_index &= (1 << cm->width) - 1;
if (parent_index == cm->fixed_predivs[i].index)
if (parent_index == cm->var_predivs[i].index) {
int parent_index,
return parent_rate / ccu_mux_get_prediv(common, cm, parent_index);
int parent_index,
return parent_rate * ccu_mux_get_prediv(common, cm, parent_index);
int parent_index,
.parent_index = i,
factors_req.parent_index =
u8 parent_index;
if (req->parent_index == SUN6I_AHB1_PARENT_PLL6) {
if (req->parent_index == SUN6I_AHB1_PARENT_PLL6)
u8 parent_index, shift;
parent_index = clk_super_get_parent(hw);
if ((parent_index == mux->div2_index) ||
(parent_index == mux->pllx_index)) {
if (emc_get_parent(&tegra->hw) == timing->parent_index &&
car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_SRC(timing->parent_index);
if (emc_parent_clk_sources[timing->parent_index] !=
tegra->timings[timing_index].parent_index])
if (emc_parent_clk_sources[timing->parent_index] !=
tegra->timings[timing_index].parent_index])
emc_parent_clk_sources[timing->parent_index] &&
timing->parent_index = 0xff;
timing->parent_index = i;
u8 parent_index;
clk->parent_index = 0;
u8 parent_index;
u8 old_index = clk->parent_index;
clk->parent_index = index;
return clk->parent_index;
unsigned int parent_index, uint64_t key)
if (parent_index > 0) {
dm_block_t left_b = value64(parent, parent_index - 1);
return rebalance_left(s, vt, parent_index, key);
if (parent_index < (nr_parent - 1)) {
dm_block_t right_b = value64(parent, parent_index + 1);
return rebalance_right(s, vt, parent_index, key);
(parent_index == 0) || (parent_index + 1 == nr_parent)) {
return split_one_into_two(s, parent_index, vt, key);
return split_two_into_three(s, parent_index, vt, key);
static int split_one_into_two(struct shadow_spine *s, unsigned int parent_index,
r = insert_at(sizeof(__le64), pn, parent_index + 1,
static int split_two_into_three(struct shadow_spine *s, unsigned int parent_index,
if (parent_index == 0) {
r = shadow_child(s->info, vt, pn, parent_index + 1, &right);
middle_index = parent_index;
r = shadow_child(s->info, vt, pn, parent_index - 1, &left);
unsigned int parent_index, uint64_t key)
r = shadow_child(s->info, vt, parent, parent_index - 1, &sib);
*key_ptr(parent, parent_index) = right->keys[0];
unsigned int parent_index, uint64_t key)
r = shadow_child(s->info, vt, parent, parent_index + 1, &sib);
*key_ptr(parent, parent_index + 1) = right->keys[0];
refclk_driver->parent_index = cdns_torrent_refclk_driver_get_parent(hw);
return cdns_torrent_refclk_driver_set_parent(hw, refclk_driver->parent_index);
u8 parent_index;
int parent_index, int index)
return index * graph->nodes_count + parent_index;
int parent_index, int index)
parent_index);
int parent_index, int index)
parent_index);