ocp_reg_set_bits
ocp_reg_set_bits(tp, OCP_PHY_PATCH_CMD, PATCH_REQUEST);
ocp_reg_set_bits(tp, OCP_EEE_CONFIG2,
ocp_reg_set_bits(tp, OCP_EEE_CFG, EEE10_EN);
ocp_reg_set_bits(tp, OCP_POWER_CFG, EN_ALDPS);
ocp_reg_set_bits(tp, OCP_POWER_CFG, EEE_CLKDIV_EN);
ocp_reg_set_bits(tp, OCP_DOWN_SPEED, EN_10M_BGOFF);
ocp_reg_set_bits(tp, OCP_POWER_CFG, EN_10M_PLLOFF);
ocp_reg_set_bits(tp, OCP_NCTL_CFG, PGA_RETURN_EN);
ocp_reg_set_bits(tp, OCP_POWER_CFG, EEE_CLKDIV_EN);
ocp_reg_set_bits(tp, OCP_DOWN_SPEED,
ocp_reg_set_bits(tp, 0xad4e, BIT(4));
ocp_reg_set_bits(tp, 0xad18, BIT(10));
ocp_reg_set_bits(tp, 0xad1a, 0x3ff);
ocp_reg_set_bits(tp, 0xad1c, 0x3ff);
ocp_reg_set_bits(tp, 0xad16, 0x3ff);
ocp_reg_set_bits(tp, 0xd068, BIT(13));
ocp_reg_set_bits(tp, OCP_10GBT_CTRL, RTL_ADV2_5G_F_R);
ocp_reg_set_bits(tp, OCP_INTR_EN, INTR_SPEED_FORCE);
ocp_reg_set_bits(tp, 0xc402, BIT(10));
ocp_reg_set_bits(tp, 0xbc08, BIT(3) | BIT(2));
ocp_reg_set_bits(tp, 0xacda, 0xff00);
ocp_reg_set_bits(tp, 0xacde, 0xf000);
ocp_reg_set_bits(tp, 0xbf4c, BIT(1));
ocp_reg_set_bits(tp, 0xbcca, BIT(9) | BIT(8));
ocp_reg_set_bits(tp, 0xb896, BIT(0));
ocp_reg_set_bits(tp, 0xa86a, BIT(0));
ocp_reg_set_bits(tp, 0xa6f0, BIT(0));
ocp_reg_set_bits(tp, OCP_INTR_EN, INTR_SPEED_FORCE);
ocp_reg_set_bits(tp, 0xa430, BIT(0) | BIT(1));
ocp_reg_set_bits(tp, 0xa654, BIT(11));
ocp_reg_set_bits(tp, 0xb648, BIT(14));
ocp_reg_set_bits(tp, 0xad94, BIT(5));
ocp_reg_set_bits(tp, 0xada0, BIT(1));
ocp_reg_set_bits(tp, 0xad9c, BIT(5));
ocp_reg_set_bits(tp, 0xb648, BIT(6));
ocp_reg_set_bits(tp, 0xaec2, BIT(12));
ocp_reg_set_bits(tp, 0xb576, BIT(0));
ocp_reg_set_bits(tp, 0xbf0c, 0x7 << 11);
ocp_reg_set_bits(tp, OCP_POWER_CFG, EEE_CLKDIV_EN);