ov5645
struct ov5645 *ov5645;
ov5645 = devm_kzalloc(dev, sizeof(struct ov5645), GFP_KERNEL);
if (!ov5645)
ov5645->i2c_client = client;
ov5645->dev = dev;
&ov5645->ep);
if (ov5645->ep.bus_type != V4L2_MBUS_CSI2_DPHY)
ov5645->xclk = devm_v4l2_sensor_clk_get_legacy(dev, NULL, false, 0);
if (IS_ERR(ov5645->xclk))
return dev_err_probe(dev, PTR_ERR(ov5645->xclk),
xclk_freq = clk_get_rate(ov5645->xclk);
ov5645->supplies[i].supply = ov5645_supply_name[i];
ov5645->supplies);
ov5645->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_HIGH);
if (IS_ERR(ov5645->enable_gpio))
return dev_err_probe(dev, PTR_ERR(ov5645->enable_gpio),
ov5645->rst_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
if (IS_ERR(ov5645->rst_gpio))
return dev_err_probe(dev, PTR_ERR(ov5645->rst_gpio),
v4l2_ctrl_handler_init(&ov5645->ctrls, 9);
v4l2_ctrl_new_std(&ov5645->ctrls, &ov5645_ctrl_ops,
v4l2_ctrl_new_std(&ov5645->ctrls, &ov5645_ctrl_ops,
v4l2_ctrl_new_std(&ov5645->ctrls, &ov5645_ctrl_ops,
v4l2_ctrl_new_std(&ov5645->ctrls, &ov5645_ctrl_ops,
v4l2_ctrl_new_std(&ov5645->ctrls, &ov5645_ctrl_ops,
v4l2_ctrl_new_std_menu(&ov5645->ctrls, &ov5645_ctrl_ops,
v4l2_ctrl_new_std_menu_items(&ov5645->ctrls, &ov5645_ctrl_ops,
ov5645->pixel_clock = v4l2_ctrl_new_std(&ov5645->ctrls,
ov5645->link_freq = v4l2_ctrl_new_int_menu(&ov5645->ctrls,
if (ov5645->link_freq)
ov5645->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
ov5645->sd.ctrl_handler = &ov5645->ctrls;
if (ov5645->ctrls.error) {
ret = ov5645->ctrls.error;
static inline struct ov5645 *to_ov5645(struct v4l2_subdev *sd)
v4l2_i2c_subdev_init(&ov5645->sd, client, &ov5645_subdev_ops);
ov5645->sd.internal_ops = &ov5645_internal_ops;
ov5645->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
ov5645->pad.flags = MEDIA_PAD_FL_SOURCE;
ov5645->sd.dev = dev;
ov5645->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
ret = media_entity_pads_init(&ov5645->sd.entity, 1, &ov5645->pad);
return container_of(sd, struct ov5645, sd);
ret = ov5645_read_reg(ov5645, OV5645_CHIP_ID_HIGH, &chip_id_high);
ret = ov5645_read_reg(ov5645, OV5645_CHIP_ID_LOW, &chip_id_low);
ret = ov5645_read_reg(ov5645, OV5645_AEC_PK_MANUAL,
&ov5645->aec_pk_manual);
ret = ov5645_read_reg(ov5645, OV5645_TIMING_TC_REG20,
&ov5645->timing_tc_reg20);
ret = ov5645_read_reg(ov5645, OV5645_TIMING_TC_REG21,
&ov5645->timing_tc_reg21);
ov5645->sd.state_lock = ov5645->ctrls.lock;
ret = v4l2_subdev_init_finalize(&ov5645->sd);
ret = v4l2_async_register_subdev_sensor(&ov5645->sd);
v4l2_subdev_cleanup(&ov5645->sd);
media_entity_cleanup(&ov5645->sd.entity);
v4l2_ctrl_handler_free(&ov5645->ctrls);
struct ov5645 *ov5645 = to_ov5645(sd);
v4l2_async_unregister_subdev(&ov5645->sd);
media_entity_cleanup(&ov5645->sd.entity);
v4l2_ctrl_handler_free(&ov5645->ctrls);
pm_runtime_disable(ov5645->dev);
if (!pm_runtime_status_suspended(ov5645->dev))
ov5645_set_power_off(ov5645->dev);
pm_runtime_set_suspended(ov5645->dev);
static int ov5645_write_reg(struct ov5645 *ov5645, u16 reg, u8 val)
ret = i2c_master_send(ov5645->i2c_client, regbuf, 3);
dev_err(ov5645->dev, "%s: write reg error %d: reg=%x, val=%x\n",
static int ov5645_read_reg(struct ov5645 *ov5645, u16 reg, u8 *val)
ret = i2c_master_send(ov5645->i2c_client, regbuf, 2);
dev_err(ov5645->dev, "%s: write reg error %d: reg=%x\n",
ret = i2c_master_recv(ov5645->i2c_client, val, 1);
dev_err(ov5645->dev, "%s: read reg error %d: reg=%x\n",
static int ov5645_set_aec_mode(struct ov5645 *ov5645, u32 mode)
u8 val = ov5645->aec_pk_manual;
ret = ov5645_write_reg(ov5645, OV5645_AEC_PK_MANUAL, val);
ov5645->aec_pk_manual = val;
static int ov5645_set_agc_mode(struct ov5645 *ov5645, u32 enable)
u8 val = ov5645->aec_pk_manual;
ret = ov5645_write_reg(ov5645, OV5645_AEC_PK_MANUAL, val);
ov5645->aec_pk_manual = val;
static int ov5645_set_register_array(struct ov5645 *ov5645,
ret = ov5645_write_reg(ov5645, settings->reg, settings->val);
struct ov5645 *ov5645 = to_ov5645(sd);
ov5645_write_reg(ov5645, OV5645_IO_MIPI_CTRL00, 0x58);
gpiod_set_value_cansleep(ov5645->rst_gpio, 1);
gpiod_set_value_cansleep(ov5645->enable_gpio, 0);
regulator_bulk_disable(OV5645_NUM_SUPPLIES, ov5645->supplies);
struct ov5645 *ov5645 = to_ov5645(sd);
clk_disable_unprepare(ov5645->xclk);
struct ov5645 *ov5645 = to_ov5645(sd);
ret = regulator_bulk_enable(OV5645_NUM_SUPPLIES, ov5645->supplies);
ret = clk_prepare_enable(ov5645->xclk);
dev_err(ov5645->dev, "clk prepare enable failed\n");
regulator_bulk_disable(OV5645_NUM_SUPPLIES, ov5645->supplies);
gpiod_set_value_cansleep(ov5645->enable_gpio, 1);
gpiod_set_value_cansleep(ov5645->rst_gpio, 0);
ret = ov5645_set_register_array(ov5645, ov5645_global_init_setting,
dev_err(ov5645->dev, "could not set init registers\n");
clk_disable_unprepare(ov5645->xclk);
static int ov5645_set_saturation(struct ov5645 *ov5645, s32 value)
ret = ov5645_write_reg(ov5645, OV5645_SDE_SAT_U, reg_value);
return ov5645_write_reg(ov5645, OV5645_SDE_SAT_V, reg_value);
static int ov5645_set_hflip(struct ov5645 *ov5645, s32 value)
u8 val = ov5645->timing_tc_reg21;
ret = ov5645_write_reg(ov5645, OV5645_TIMING_TC_REG21, val);
ov5645->timing_tc_reg21 = val;
static int ov5645_set_vflip(struct ov5645 *ov5645, s32 value)
u8 val = ov5645->timing_tc_reg20;
ret = ov5645_write_reg(ov5645, OV5645_TIMING_TC_REG20, val);
ov5645->timing_tc_reg20 = val;
static int ov5645_set_test_pattern(struct ov5645 *ov5645, s32 value)
return ov5645_write_reg(ov5645, OV5645_PRE_ISP_TEST_SETTING_1, val);
static int ov5645_set_awb(struct ov5645 *ov5645, s32 enable_auto)
return ov5645_write_reg(ov5645, OV5645_AWB_MANUAL_CONTROL, val);
struct ov5645 *ov5645 = container_of(ctrl->handler,
struct ov5645, ctrls);
if (!pm_runtime_get_if_in_use(ov5645->dev))
ret = ov5645_set_saturation(ov5645, ctrl->val);
ret = ov5645_set_awb(ov5645, ctrl->val);
ret = ov5645_set_agc_mode(ov5645, ctrl->val);
ret = ov5645_set_aec_mode(ov5645, ctrl->val);
ret = ov5645_set_test_pattern(ov5645, ctrl->val);
ret = ov5645_set_hflip(ov5645, ctrl->val);
ret = ov5645_set_vflip(ov5645, ctrl->val);
pm_runtime_put_autosuspend(ov5645->dev);
struct ov5645 *ov5645 = to_ov5645(sd);
ret = __v4l2_ctrl_s_ctrl_int64(ov5645->pixel_clock,
ret = __v4l2_ctrl_s_ctrl(ov5645->link_freq,
ov5645->current_mode = new_mode;
struct ov5645 *ov5645 = to_ov5645(sd);
ret = pm_runtime_resume_and_get(ov5645->dev);
ret = ov5645_set_register_array(ov5645,
ov5645->current_mode->data,
ov5645->current_mode->data_size);
dev_err(ov5645->dev, "could not set mode %dx%d\n",
ov5645->current_mode->width,
ov5645->current_mode->height);
ret = __v4l2_ctrl_handler_setup(&ov5645->ctrls);
dev_err(ov5645->dev, "could not sync v4l2 controls\n");
ret = ov5645_write_reg(ov5645, OV5645_IO_MIPI_CTRL00, 0x45);
ret = ov5645_write_reg(ov5645, OV5645_SYSTEM_CTRL0,
pm_runtime_put_sync(ov5645->dev);
struct ov5645 *ov5645 = to_ov5645(sd);
ret = ov5645_write_reg(ov5645, OV5645_IO_MIPI_CTRL00, 0x40);
ret = ov5645_write_reg(ov5645, OV5645_SYSTEM_CTRL0,
pm_runtime_put_autosuspend(ov5645->dev);