drivers/crypto/marvell/octeontx2/otx2_cpt_common.h

203

int otx2_cpt_write_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,

drivers/crypto/marvell/octeontx2/otx2_cpt_devlink.c

68

return otx2_cpt_write_af_reg(&cptpf->afpf_mbox, pdev,

drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c

124

EXPORT_SYMBOL_NS_GPL(otx2_cpt_write_af_reg, "CRYPTO_DEV_OCTEONTX2_CPT");

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

126

ret = otx2_cpt_write_af_reg(lfs->mbox, lfs->pdev,

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

65

ret = otx2_cpt_write_af_reg(lfs->mbox, lfs->pdev,

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

86

ret = otx2_cpt_write_af_reg(lfs->mbox, lfs->pdev,

drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c

1249

otx2_cpt_write_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_CTL,

drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c

1256

otx2_cpt_write_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_CTX_FLUSH_TIMER,

drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c

1268

otx2_cpt_write_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_DIAG,

drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c

165

return otx2_cpt_write_af_reg(&cptpf->afpf_mbox, cptpf->pdev,

drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c

178

ret = otx2_cpt_write_af_reg(&cptpf->afpf_mbox, cptpf->pdev,

drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c

241

ret = otx2_cpt_write_af_reg(&cptpf->afpf_mbox,

drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c

275

ret = otx2_cpt_write_af_reg(&cptpf->afpf_mbox,

drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c

327

ret = otx2_cpt_write_af_reg(&cptpf->afpf_mbox,