drivers/crypto/marvell/octeontx2/otx2_cpt_common.h

201

int otx2_cpt_read_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,

drivers/crypto/marvell/octeontx2/otx2_cpt_devlink.c

44

otx2_cpt_read_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_CTL, &reg_val,

drivers/crypto/marvell/octeontx2/otx2_cpt_devlink.c

64

otx2_cpt_read_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_CTL,

drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c

111

EXPORT_SYMBOL_NS_GPL(otx2_cpt_read_af_reg, "CRYPTO_DEV_OCTEONTX2_CPT");

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

118

ret = otx2_cpt_read_af_reg(lfs->mbox, lfs->pdev,

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

57

ret = otx2_cpt_read_af_reg(lfs->mbox, lfs->pdev,

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

78

ret = otx2_cpt_read_af_reg(lfs->mbox, lfs->pdev,

drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c

601

otx2_cpt_read_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_CTL, &reg_val,

drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c

629

ret = otx2_cpt_read_af_reg(&cptpf->afpf_mbox, cptpf->pdev,

drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c

1241

otx2_cpt_read_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_CTL, &reg_val,

drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c

1266

otx2_cpt_read_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_DIAG,

drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c

1313

ret = otx2_cpt_read_af_reg(&cptpf->afpf_mbox,

drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c

232

ret = otx2_cpt_read_af_reg(&cptpf->afpf_mbox, cptpf->pdev,

drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c

258

ret = otx2_cpt_read_af_reg(&cptpf->afpf_mbox,

drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c

318

ret = otx2_cpt_read_af_reg(&cptpf->afpf_mbox, cptpf->pdev,