drivers/gpu/drm/amd/display/dc/core/dc.c

7122

state->optc[i].optc_dsc_mode = 1; /* DSC enabled */

drivers/gpu/drm/amd/display/dc/core/dc.c

7126

state->optc[i].optc_dsc_mode = 0;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2282

enum optc_dsc_mode optc_dsc_mode = OPTC_DSC_DISABLED;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2292

optc_dsc_mode = dsc_optc_cfg->is_pixel_format_444 ?

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2298

tg->funcs->set_dsc_config(tg, optc_dsc_mode, bytes_per_pixel, slice_width);

drivers/gpu/drm/amd/display/dc/dc.h

3219

uint32_t optc_dsc_mode; /* OPTC_DATA_FORMAT_CONTROL->OPTC_DSC_MODE from dsc_mode parameter */

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

281

enum optc_dsc_mode dsc_mode,

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

304

enum optc_dsc_mode dsc_mode,

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

393

enum optc_dsc_mode dsc_mode,

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

351

enum optc_dsc_mode dsc_mode,

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

355

enum optc_dsc_mode dsc_mode,

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

125

optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

130

optc_dsc_mode,

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

86

enum optc_dsc_mode optc_dsc_mode;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1047

enum optc_dsc_mode optc_dsc_mode;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1090

optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1094

optc_dsc_mode,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

343

enum optc_dsc_mode optc_dsc_mode;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

381

optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

386

optc_dsc_mode,

drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h

247

enum optc_dsc_mode dsc_mode,

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

474

enum optc_dsc_mode dsc_mode,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

833

enum optc_dsc_mode optc_dsc_mode;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

863

optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

871

optc_dsc_mode,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

882

optc_dsc_mode,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

133

enum optc_dsc_mode dsc_mode,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

102

enum optc_dsc_mode dsc_mode,

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

185

enum optc_dsc_mode dsc_mode,

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

352

enum optc_dsc_mode dsc_mode,